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__int64 __usercall si_pmu_set_lpoclk@<rax>(char a1@<al>, __int64 a2@<rdi>, __int64 a3@<rsi>, char a4)

{

__int64 v4; // rbx

__int64 v5; // r14

__int64 result; // rax

int v7; // er13

int v8; // er15

bool v9; // zf

__int64 v10; // r15

__int64 v11; // rsi

int v12; // ecx

__int64 v13; // r15

__int64 v14; // rsi

__int64 v15; // rax

__int64 v16; // rax

unsigned int v17; // ebx

__int64 v18; // rsi

__int64 v19; // rdi

__int64 v20; // rax

__int64 v21; // rax

int v22; // eax

__int64 v23; // rsi

__int64 v24; // rdi

__int64 v25; // rax

unsigned int v26; // ebx

__int64 v27; // rsi

__int64 v28; // rdi

__int64 v29; // rax

int v30; // eax

char v30; // ST00_1

signed __int64 v31; // rdx

int v31; // eax

__int64 v32; // rax

signed __int64 v32; // rdx

unsigned int v33; // ebx

__int64 v33; // rax

__int64 v34; // rsi

unsigned int v34; // ebx

__int64 v35; // rdi

__int64 v35; // rsi

__int64 v36; // rax

__int64 v36; // rdi

char v37; // [rsp-8h] [rbp-30h]

__int64 v37; // rax

char v38; // [rsp-8h] [rbp-30h]

v37 = a1;

v38 = a1;

v4 = a3;

v5 = a2;

result = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");

if ( (_DWORD)result )

{

v7 = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");

v8 = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");

result = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");

if ( v7 & 0x8000000 )

{

v12 = *(_DWORD *)(a2 + 60);

if ( v12 != 43602 && v12 != 43462 )

{

si_pmu_chipcontrol(a2, 0LL, 0x200000LL, 0x200000LL);

si_gci_chipcontrol(a2, 6LL, 2LL, 2LL);

}

else

{

si_pmu_chipcontrol(a2, 2LL, 0x40000000LL, ~(32 * (_DWORD)result) & 0x40000000);

}

v13 = a3;

if ( *(_DWORD *)(a2 + 20) >= 35 && *(_BYTE *)(a2 + 28) & 0x40 )

v14 = (unsigned int)si_findcoreidx(a2, 2087LL, 0LL);

else

v14 = 0LL;

v15 = si_corereg_addr(a2, v14, 1544LL);

v16 = read_bpt_reg(v4, v15, 4LL);

if ( !(v16 & 0x100) )

{

v17 = 0;

{

IODelay(1000LL);

if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )

{

v19 = v5;

v18 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);

}

else

{

v18 = 0LL;

v19 = v5;

}

v20 = si_corereg_addr(v19, v18, 1544LL);

v21 = read_bpt_reg(v13, v20, 4LL);

++v17;

}

while ( !(v21 & 0x100) && v17 < 0x3E8 );

if ( v17 >= 0x3E8 )

{

osl_wificc_logDebug((unsigned __int64)"External LPO is not available\n");

return osl_printf("External LPO is not available\n", a4);

}

IODelay(1000LL);

v22 = *(_DWORD *)(v5 + 60);

if ( v22 != 43602 && v22 != 43462 )

{

si_gci_chipcontrol(v5, 6LL, 8LL, 8LL);

si_gci_chipcontrol(v5, 6LL, 4LL, 0LL);

IODelay(1000LL);

if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )

{

v24 = v5;

v23 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);

}

else

{

v23 = 0LL;

v24 = v5;

}

v25 = si_corereg_addr(v24, v23, 1536LL);

if ( read_bpt_reg(v13, v25, 4LL) & 1 )

{

v26 = 0;

{

IODelay(1000LL);

if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )

{

v28 = v5;

v27 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);

}

else

{

v27 = 0LL;

v28 = v5;

}

v29 = si_corereg_addr(v28, v27, 1536LL);

++v26;

}

while ( read_bpt_reg(v13, v29, 4LL) & 1 && v26 < 0x3E8 );

if ( v26 >= 0x3E8 )

{

osl_wificc_logDebug((unsigned __int64)"External LPO is not set\n");

osl_printf("External LPO is not set\n", v37);

osl_printf("External LPO is not set\n", v38);

v30 = *(_DWORD *)(v5 + 60);

osl_panic("32KHz LPO Clock not running", v30);

if ( v30 == 43602 || v30 == 43462 )

v31 = *(_DWORD *)(v5 + 60);

if ( v31 == 43602 || v31 == 43462 )

return si_pmu_chipcontrol(v5, 2LL, 0x80000LL, 0LL);

v31 = 8LL;

v32 = 8LL;

return si_gci_chipcontrol(v5, 6LL, v31, 0LL);

return si_gci_chipcontrol(v5, 6LL, v32, 0LL);

}

else

{

si_pmu_chipcontrol(v5, 2LL, 0x80000LL, 0x80000LL);

}

result = *(unsigned int *)(v5 + 60);

if ( (_DWORD)result != 43462 && (_DWORD)result != 43602 )

{

si_pmu_chipcontrol(v5, 0LL, 0x100000LL, 0LL);

v31 = 1LL;

v32 = 1LL;

return si_gci_chipcontrol(v5, 6LL, v31, 0LL);

return si_gci_chipcontrol(v5, 6LL, v32, 0LL);

}

else

{

v9 = (v8 & 0x4000000) == 0;

v10 = a3;

if ( !v9 )

{

result = *(unsigned int *)(a2 + 60);

if ( (_DWORD)result != 43462 && (_DWORD)result != 43602 )

{

si_pmu_chipcontrol(a2, 0LL, 0x100000LL, 0x100000LL);

si_gci_chipcontrol(a2, 6LL, 1LL, 1LL);

IODelay(1000LL);

si_gci_chipcontrol(a2, 6LL, 4LL, 4LL);

si_gci_chipcontrol(a2, 6LL, 8LL, 0LL);

IODelay(1000LL);

if ( *(_DWORD *)(a2 + 20) >= 35 && *(_BYTE *)(a2 + 28) & 0x40 )

v11 = (unsigned int)si_findcoreidx(a2, 2087LL, 0LL);

else

v11 = 0LL;

v32 = si_corereg_addr(a2, v11, 1536LL);

v33 = si_corereg_addr(a2, v11, 1536LL);

if ( read_bpt_reg(v4, v32, 4LL) & 1 )

if ( read_bpt_reg(v4, v33, 4LL) & 1 )

goto LABEL_66;

v33 = 0;

v34 = 0;

{

IODelay(1000LL);

if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )

{

v35 = v5;

v36 = v5;

v34 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);

v35 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);

}

else

{

v34 = 0LL;

v35 = 0LL;

v35 = v5;

v36 = v5;

}

v36 = si_corereg_addr(v35, v34, 1536LL);

v37 = si_corereg_addr(v36, v35, 1536LL);

++v33;

++v34;

}

while ( !(read_bpt_reg(v10, v36, 4LL) & 1) && v33 < 0x3E8 );

while ( !(read_bpt_reg(v10, v37, 4LL) & 1) && v34 < 0x3E8 );

if ( v33 < 0x3E8 )

if ( v34 < 0x3E8 )

{

LABEL_66:

si_pmu_chipcontrol(v5, 0LL, 0x200000LL, 0LL);

v31 = 2LL;

v32 = 2LL;

}

else

{

osl_wificc_logDebug((unsigned __int64)"Internal LPO is not set\n");

osl_printf("Internal LPO is not set\n", v37);

osl_printf("Internal LPO is not set\n", v38);

v31 = 4LL;

v32 = 4LL;

}

return si_gci_chipcontrol(v5, 6LL, v31, 0LL);

return si_gci_chipcontrol(v5, 6LL, v32, 0LL);

}

return result;

}

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__int64 __usercall si_pmu_set_lpoclk@<rax>(char a1@<al>, __int64 a2@<rdi>, __int64 a3@<rsi>, char a4)
{
  __int64 v4; // rbx
  __int64 v5; // r14
  __int64 result; // rax
  int v7; // er13
  int v8; // er15
  bool v9; // zf
  __int64 v10; // r15
  __int64 v11; // rsi
  int v12; // ecx
  __int64 v13; // r15
  __int64 v14; // rsi
  __int64 v15; // rax
  __int64 v16; // rax
  unsigned int v17; // ebx
  __int64 v18; // rsi
  __int64 v19; // rdi
  __int64 v20; // rax
  __int64 v21; // rax
  int v22; // eax
  __int64 v23; // rsi
  __int64 v24; // rdi
  __int64 v25; // rax
  unsigned int v26; // ebx
  __int64 v27; // rsi
  __int64 v28; // rdi
  __int64 v29; // rax
  int v30; // eax
  signed __int64 v31; // rdx
  __int64 v32; // rax
  unsigned int v33; // ebx
  __int64 v34; // rsi
  __int64 v35; // rdi
  __int64 v36; // rax
  char v37; // [rsp-8h] [rbp-30h]

v37 = a1;
  v4 = a3;
  v5 = a2;
  result = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");
  if ( (_DWORD)result )
  {
    v7 = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");
    v8 = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");
    result = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");
    if ( v7 & 0x8000000 )
    {
      v12 = *(_DWORD *)(a2 + 60);
      if ( v12 != 43602 && v12 != 43462 )
      {
        si_pmu_chipcontrol(a2, 0LL, 0x200000LL, 0x200000LL);
        si_gci_chipcontrol(a2, 6LL, 2LL, 2LL);
      }
      else
      {
        si_pmu_chipcontrol(a2, 2LL, 0x40000000LL, ~(32 * (_DWORD)result) & 0x40000000);
      }
      v13 = a3;
      if ( *(_DWORD *)(a2 + 20) >= 35 && *(_BYTE *)(a2 + 28) & 0x40 )
        v14 = (unsigned int)si_findcoreidx(a2, 2087LL, 0LL);
      else
        v14 = 0LL;
      v15 = si_corereg_addr(a2, v14, 1544LL);
      v16 = read_bpt_reg(v4, v15, 4LL);
      if ( !(v16 & 0x100) )
      {
        v17 = 0;
        do
        {
          IODelay(1000LL);
          if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )
          {
            v19 = v5;
            v18 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);
          }
          else
          {
            v18 = 0LL;
            v19 = v5;
          }
          v20 = si_corereg_addr(v19, v18, 1544LL);
          v21 = read_bpt_reg(v13, v20, 4LL);
          ++v17;
        }
        while ( !(v21 & 0x100) && v17 < 0x3E8 );
        if ( v17 >= 0x3E8 )
        {
          osl_wificc_logDebug((unsigned __int64)"External LPO is not available\n");
          return osl_printf("External LPO is not available\n", a4);
        }
      }
      IODelay(1000LL);
      v22 = *(_DWORD *)(v5 + 60);
      if ( v22 != 43602 && v22 != 43462 )
      {
        si_gci_chipcontrol(v5, 6LL, 8LL, 8LL);
        si_gci_chipcontrol(v5, 6LL, 4LL, 0LL);
        IODelay(1000LL);
        if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )
        {
          v24 = v5;
          v23 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);
        }
        else
        {
          v23 = 0LL;
          v24 = v5;
        }
        v25 = si_corereg_addr(v24, v23, 1536LL);
        if ( read_bpt_reg(v13, v25, 4LL) & 1 )
        {
          v26 = 0;
          do
          {
            IODelay(1000LL);
            if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )
            {
              v28 = v5;
              v27 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);
            }
            else
            {
              v27 = 0LL;
              v28 = v5;
            }
            v29 = si_corereg_addr(v28, v27, 1536LL);
            ++v26;
          }
          while ( read_bpt_reg(v13, v29, 4LL) & 1 && v26 < 0x3E8 );
          if ( v26 >= 0x3E8 )
          {
            osl_wificc_logDebug((unsigned __int64)"External LPO is not set\n");
            osl_printf("External LPO is not set\n", v37);
            v30 = *(_DWORD *)(v5 + 60);
            if ( v30 == 43602 || v30 == 43462 )
              return si_pmu_chipcontrol(v5, 2LL, 0x80000LL, 0LL);
            v31 = 8LL;
            return si_gci_chipcontrol(v5, 6LL, v31, 0LL);
          }
        }
      }
      else
      {
        si_pmu_chipcontrol(v5, 2LL, 0x80000LL, 0x80000LL);
      }
      result = *(unsigned int *)(v5 + 60);
      if ( (_DWORD)result != 43462 && (_DWORD)result != 43602 )
      {
        si_pmu_chipcontrol(v5, 0LL, 0x100000LL, 0LL);
        v31 = 1LL;
        return si_gci_chipcontrol(v5, 6LL, v31, 0LL);
      }
    }
    else
    {
      v9 = (v8 & 0x4000000) == 0;
      v10 = a3;
      if ( !v9 )
      {
        result = *(unsigned int *)(a2 + 60);
        if ( (_DWORD)result != 43462 && (_DWORD)result != 43602 )
        {
          si_pmu_chipcontrol(a2, 0LL, 0x100000LL, 0x100000LL);
          si_gci_chipcontrol(a2, 6LL, 1LL, 1LL);
          IODelay(1000LL);
          si_gci_chipcontrol(a2, 6LL, 4LL, 4LL);
          si_gci_chipcontrol(a2, 6LL, 8LL, 0LL);
          IODelay(1000LL);
          if ( *(_DWORD *)(a2 + 20) >= 35 && *(_BYTE *)(a2 + 28) & 0x40 )
            v11 = (unsigned int)si_findcoreidx(a2, 2087LL, 0LL);
          else
            v11 = 0LL;
          v32 = si_corereg_addr(a2, v11, 1536LL);
          if ( read_bpt_reg(v4, v32, 4LL) & 1 )
            goto LABEL_66;
          v33 = 0;
          do
          {
            IODelay(1000LL);
            if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )
            {
              v35 = v5;
              v34 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);
            }
            else
            {
              v34 = 0LL;
              v35 = v5;
            }
            v36 = si_corereg_addr(v35, v34, 1536LL);
            ++v33;
          }
          while ( !(read_bpt_reg(v10, v36, 4LL) & 1) && v33 < 0x3E8 );
          if ( v33 < 0x3E8 )
          {
LABEL_66:
            si_pmu_chipcontrol(v5, 0LL, 0x200000LL, 0LL);
            v31 = 2LL;
          }
          else
          {
            osl_wificc_logDebug((unsigned __int64)"Internal LPO is not set\n");
            osl_printf("Internal LPO is not set\n", v37);
            v31 = 4LL;
          }
          return si_gci_chipcontrol(v5, 6LL, v31, 0LL);
        }
      }
    }
  }
  return result;
}

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__int64 __usercall si_pmu_set_lpoclk@<rax>(char a1@<al>, __int64 a2@<rdi>, __int64 a3@<rsi>, char a4)
{
  __int64 v4; // rbx
  __int64 v5; // r14
  __int64 result; // rax
  int v7; // er13
  int v8; // er15
  bool v9; // zf
  __int64 v10; // r15
  __int64 v11; // rsi
  int v12; // ecx
  __int64 v13; // r15
  __int64 v14; // rsi
  __int64 v15; // rax
  __int64 v16; // rax
  unsigned int v17; // ebx
  __int64 v18; // rsi
  __int64 v19; // rdi
  __int64 v20; // rax
  __int64 v21; // rax
  int v22; // eax
  __int64 v23; // rsi
  __int64 v24; // rdi
  __int64 v25; // rax
  unsigned int v26; // ebx
  __int64 v27; // rsi
  __int64 v28; // rdi
  __int64 v29; // rax
  char v30; // ST00_1
  int v31; // eax
  signed __int64 v32; // rdx
  __int64 v33; // rax
  unsigned int v34; // ebx
  __int64 v35; // rsi
  __int64 v36; // rdi
  __int64 v37; // rax
  char v38; // [rsp-8h] [rbp-30h]

v38 = a1;
  v4 = a3;
  v5 = a2;
  result = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");
  if ( (_DWORD)result )
  {
    v7 = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");
    v8 = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");
    result = getintvar(*(_QWORD *)(a2 + 184), "boardflags3");
    if ( v7 & 0x8000000 )
    {
      v12 = *(_DWORD *)(a2 + 60);
      if ( v12 != 43602 && v12 != 43462 )
      {
        si_pmu_chipcontrol(a2, 0LL, 0x200000LL, 0x200000LL);
        si_gci_chipcontrol(a2, 6LL, 2LL, 2LL);
      }
      else
      {
        si_pmu_chipcontrol(a2, 2LL, 0x40000000LL, ~(32 * (_DWORD)result) & 0x40000000);
      }
      v13 = a3;
      if ( *(_DWORD *)(a2 + 20) >= 35 && *(_BYTE *)(a2 + 28) & 0x40 )
        v14 = (unsigned int)si_findcoreidx(a2, 2087LL, 0LL);
      else
        v14 = 0LL;
      v15 = si_corereg_addr(a2, v14, 1544LL);
      v16 = read_bpt_reg(v4, v15, 4LL);
      if ( !(v16 & 0x100) )
      {
        v17 = 0;
        do
        {
          IODelay(1000LL);
          if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )
          {
            v19 = v5;
            v18 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);
          }
          else
          {
            v18 = 0LL;
            v19 = v5;
          }
          v20 = si_corereg_addr(v19, v18, 1544LL);
          v21 = read_bpt_reg(v13, v20, 4LL);
          ++v17;
        }
        while ( !(v21 & 0x100) && v17 < 0x3E8 );
        if ( v17 >= 0x3E8 )
        {
          osl_wificc_logDebug((unsigned __int64)"External LPO is not available\n");
          return osl_printf("External LPO is not available\n", a4);
        }
      }
      IODelay(1000LL);
      v22 = *(_DWORD *)(v5 + 60);
      if ( v22 != 43602 && v22 != 43462 )
      {
        si_gci_chipcontrol(v5, 6LL, 8LL, 8LL);
        si_gci_chipcontrol(v5, 6LL, 4LL, 0LL);
        IODelay(1000LL);
        if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )
        {
          v24 = v5;
          v23 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);
        }
        else
        {
          v23 = 0LL;
          v24 = v5;
        }
        v25 = si_corereg_addr(v24, v23, 1536LL);
        if ( read_bpt_reg(v13, v25, 4LL) & 1 )
        {
          v26 = 0;
          do
          {
            IODelay(1000LL);
            if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )
            {
              v28 = v5;
              v27 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);
            }
            else
            {
              v27 = 0LL;
              v28 = v5;
            }
            v29 = si_corereg_addr(v28, v27, 1536LL);
            ++v26;
          }
          while ( read_bpt_reg(v13, v29, 4LL) & 1 && v26 < 0x3E8 );
          if ( v26 >= 0x3E8 )
          {
            osl_wificc_logDebug((unsigned __int64)"External LPO is not set\n");
            osl_printf("External LPO is not set\n", v38);
            osl_panic("32KHz LPO Clock not running", v30);
            v31 = *(_DWORD *)(v5 + 60);
            if ( v31 == 43602 || v31 == 43462 )
              return si_pmu_chipcontrol(v5, 2LL, 0x80000LL, 0LL);
            v32 = 8LL;
            return si_gci_chipcontrol(v5, 6LL, v32, 0LL);
          }
        }
      }
      else
      {
        si_pmu_chipcontrol(v5, 2LL, 0x80000LL, 0x80000LL);
      }
      result = *(unsigned int *)(v5 + 60);
      if ( (_DWORD)result != 43462 && (_DWORD)result != 43602 )
      {
        si_pmu_chipcontrol(v5, 0LL, 0x100000LL, 0LL);
        v32 = 1LL;
        return si_gci_chipcontrol(v5, 6LL, v32, 0LL);
      }
    }
    else
    {
      v9 = (v8 & 0x4000000) == 0;
      v10 = a3;
      if ( !v9 )
      {
        result = *(unsigned int *)(a2 + 60);
        if ( (_DWORD)result != 43462 && (_DWORD)result != 43602 )
        {
          si_pmu_chipcontrol(a2, 0LL, 0x100000LL, 0x100000LL);
          si_gci_chipcontrol(a2, 6LL, 1LL, 1LL);
          IODelay(1000LL);
          si_gci_chipcontrol(a2, 6LL, 4LL, 4LL);
          si_gci_chipcontrol(a2, 6LL, 8LL, 0LL);
          IODelay(1000LL);
          if ( *(_DWORD *)(a2 + 20) >= 35 && *(_BYTE *)(a2 + 28) & 0x40 )
            v11 = (unsigned int)si_findcoreidx(a2, 2087LL, 0LL);
          else
            v11 = 0LL;
          v33 = si_corereg_addr(a2, v11, 1536LL);
          if ( read_bpt_reg(v4, v33, 4LL) & 1 )
            goto LABEL_66;
          v34 = 0;
          do
          {
            IODelay(1000LL);
            if ( *(_DWORD *)(v5 + 20) >= 35 && *(_BYTE *)(v5 + 28) & 0x40 )
            {
              v36 = v5;
              v35 = (unsigned int)si_findcoreidx(v5, 2087LL, 0LL);
            }
            else
            {
              v35 = 0LL;
              v36 = v5;
            }
            v37 = si_corereg_addr(v36, v35, 1536LL);
            ++v34;
          }
          while ( !(read_bpt_reg(v10, v37, 4LL) & 1) && v34 < 0x3E8 );
          if ( v34 < 0x3E8 )
          {
LABEL_66:
            si_pmu_chipcontrol(v5, 0LL, 0x200000LL, 0LL);
            v32 = 2LL;
          }
          else
          {
            osl_wificc_logDebug((unsigned __int64)"Internal LPO is not set\n");
            osl_printf("Internal LPO is not set\n", v38);
            v32 = 4LL;
          }
          return si_gci_chipcontrol(v5, 6LL, v32, 0LL);
        }
      }
    }
  }
  return result;
}