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****** START compiling Program:Test(int,long[]):this (MethodHash=57540ab3)

Generating code for Windows x64

OPTIONS: compCodeOpt = BLENDED_CODE

OPTIONS: compDbgCode = false

OPTIONS: compDbgInfo = true

OPTIONS: compDbgEnC = false

OPTIONS: compProcedureSplitting = false

OPTIONS: compProcedureSplittingEH = false

OPTIONS: optimizer should use profile data

IL to import:

IL_0000 04 ldarg.2

IL_0001 03 ldarg.1

IL_0002 16 ldc.i4.0

IL_0003 6a conv.i8

IL_0004 9f stelem.i8

IL_0005 04 ldarg.2

IL_0006 03 ldarg.1

IL_0007 16 ldc.i4.0

IL_0008 6a conv.i8

IL_0009 9f stelem.i8

IL_000a 2a ret

lvaSetClass: setting class for V00 to (00000000D1FFAB1E) Program

'this' passed in register rcx

Arg #1 passed in register(s) rdx

lvaSetClass: setting class for V02 to (00000000D1FFAB1E) long[]

Arg #2 passed in register(s) r8

lvaGrabTemp returning 3 (V03 tmp0) (a long lifetime temp) called for OutgoingArgSpace.

Local V03 should not be enregistered because: it is address exposed

; Initial local variable assignments

;

; V00 this ref this class-hnd <Program>

; V01 arg1 int

; V02 arg2 ref class-hnd <long[]>

; V03 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"

*************** In compInitDebuggingInfo() for Program:Test(int,long[]):this

getVars() returned cVars = 0, extendOthers = true

info.compVarScopesCount = 3

VarNum LVNum Name Beg End

0: 00h 00h V00 this 000h 00Bh

1: 01h 01h V01 arg1 000h 00Bh

2: 02h 02h V02 arg2 000h 00Bh

info.compStmtOffsetsCount = 0

info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )

*************** In fgFindBasicBlocks() for Program:Test(int,long[]):this

Jump targets:

none

New Basic Block BB01 [0000] created.

BB01 [000..00B)

IL Code Size,Instr 11, 11, Basic Block count 1, Local Variable Num,Ref count 4, 4 for method Program:Test(int,long[]):this

OPTIONS: opts.MinOpts() == false

Basic block list for 'Program:Test(int,long[]):this'

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00B) (return)

-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import

Trees after Pre-import

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00B) (return)

-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Starting PHASE Profile incorporation

BBOPT set, but no profile data available (hr=80004001)

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'Program:Test(int,long[]):this'

[ 0] 0 (0x000) ldarg.2

[ 1] 1 (0x001) ldarg.1

[ 2] 2 (0x002) ldc.i4.0 0

[ 3] 3 (0x003) conv.i8

Folding long operator with constant nodes into a constant:

[000003] ----------- * CAST long <- int

[000002] ----------- \--* CNS_INT int 0

Bashed to long constant:

[000003] ----------- * CNS_INT long 0

[ 3] 4 (0x004) stelem.i8

STMT00000 ( 0x000[E-] ... ??? )

[000005] nA-XG------ * STOREIND long

[000004] ---XG------ +--* INDEX_ADDR byref long[]

[000000] ----------- | +--* LCL_VAR ref V02 arg2

[000001] ----------- | \--* LCL_VAR int V01 arg1

[000003] ----------- \--* CNS_INT long 0

[ 0] 5 (0x005) ldarg.2

[ 1] 6 (0x006) ldarg.1

[ 2] 7 (0x007) ldc.i4.0 0

[ 3] 8 (0x008) conv.i8

Folding long operator with constant nodes into a constant:

[000009] ----------- * CAST long <- int

[000008] ----------- \--* CNS_INT int 0

Bashed to long constant:

[000009] ----------- * CNS_INT long 0

[ 3] 9 (0x009) stelem.i8

STMT00001 ( 0x005[E-] ... ??? )

[000011] nA-XG------ * STOREIND long

[000010] ---XG------ +--* INDEX_ADDR byref long[]

[000006] ----------- | +--* LCL_VAR ref V02 arg2

[000007] ----------- | \--* LCL_VAR int V01 arg1

[000009] ----------- \--* CNS_INT long 0

[ 0] 10 (0x00a) ret

STMT00002 ( 0x00A[E-] ... ??? )

[000012] ----------- * RETURN void

*************** Finishing PHASE Importation

Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00B) (return) i idxlen

-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01

STMT00000 ( 0x000[E-] ... 0x004 )

[000005] nA-XG------ * STOREIND long

[000004] ---XG------ +--* INDEX_ADDR byref long[]

[000000] ----------- | +--* LCL_VAR ref V02 arg2

[000001] ----------- | \--* LCL_VAR int V01 arg1

[000003] ----------- \--* CNS_INT long 0

***** BB01

STMT00001 ( 0x005[E-] ... 0x009 )

[000011] nA-XG------ * STOREIND long

[000010] ---XG------ +--* INDEX_ADDR byref long[]

[000006] ----------- | +--* LCL_VAR ref V02 arg2

[000007] ----------- | \--* LCL_VAR int V01 arg1

[000009] ----------- \--* CNS_INT long 0

***** BB01

STMT00002 ( 0x00A[E-] ... 0x00A )

[000012] ----------- * RETURN void

-------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE Expand patchpoints

-- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Indirect call transform

-- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import [no changes]

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Init [no changes]

*************** Starting PHASE Morph - Inlining

**************** Inline Tree

Inlines into 06000001 [via ExtendedDefaultPolicy] Program:Test(int,long[]):this:

Budget: initialTime=93, finalTime=93, initialBudget=930, currentBudget=930

Budget: initialSize=382, finalSize=382

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00B) (return) i idxlen

-----------------------------------------------------------------------------------------------------------------------------------------

*************** Exception Handling table is empty

=============== No blocks renumbered!

*************** Finishing PHASE Morph - Inlining

Trees after Morph - Inlining

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00B) (return) i idxlen

-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01

STMT00000 ( 0x000[E-] ... 0x004 )

[000005] nA-XG------ * STOREIND long

[000004] ---XG------ +--* INDEX_ADDR byref long[]

[000000] ----------- | +--* LCL_VAR ref V02 arg2

[000001] ----------- | \--* LCL_VAR int V01 arg1

[000003] ----------- \--* CNS_INT long 0

***** BB01

STMT00001 ( 0x005[E-] ... 0x009 )

[000011] nA-XG------ * STOREIND long

[000010] ---XG------ +--* INDEX_ADDR byref long[]

[000006] ----------- | +--* LCL_VAR ref V02 arg2

[000007] ----------- | \--* LCL_VAR int V01 arg1

[000009] ----------- \--* CNS_INT long 0

***** BB01

STMT00002 ( 0x00A[E-] ... 0x00A )

[000012] ----------- * RETURN void

-------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE Allocate Objects

no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00B) (return) i idxlen

-----------------------------------------------------------------------------------------------------------------------------------------

*************** Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks [no changes]

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()

No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally

No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains

No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally

No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Head and tail merge

*************** Finishing PHASE Head and tail merge

Trees after Head and tail merge

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00B) (return) i idxlen

-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01

STMT00000 ( 0x000[E-] ... 0x004 )

[000005] nA-XG------ * STOREIND long

[000004] ---XG------ +--* INDEX_ADDR byref long[]

[000000] ----------- | +--* LCL_VAR ref V02 arg2

[000001] ----------- | \--* LCL_VAR int V01 arg1

[000003] ----------- \--* CNS_INT long 0

***** BB01

STMT00001 ( 0x005[E-] ... 0x009 )

[000011] nA-XG------ * STOREIND long

[000010] ---XG------ +--* INDEX_ADDR byref long[]

[000006] ----------- | +--* LCL_VAR ref V02 arg2

[000007] ----------- | \--* LCL_VAR int V01 arg1

[000009] ----------- \--* CNS_INT long 0

***** BB01

STMT00002 ( 0x00A[E-] ... 0x00A )

[000012] ----------- * RETURN void

-------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE Merge throw blocks

*************** In fgTailMergeThrows

Method does not have multiple noreturn calls.

*************** Finishing PHASE Merge throw blocks [no changes]

*************** Starting PHASE Update flow graph early pass

*************** Finishing PHASE Update flow graph early pass [no changes]

*************** Starting PHASE Morph - Promote Structs

lvaTable before fgPromoteStructs

; Initial local variable assignments

;

; V00 this ref this class-hnd <Program>

; V01 arg1 int

; V02 arg2 ref class-hnd <long[]>

; V03 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"

struct promotion of V03 is disabled because it has already been marked address exposed

*************** Finishing PHASE Morph - Promote Structs [no changes]

*************** Starting PHASE Morph - Structs/AddrExp

LocalAddressVisitor visiting statement:

STMT00000 ( 0x000[E-] ... 0x004 )

[000005] nA-XG------ * STOREIND long

[000004] ---XG------ +--* INDEX_ADDR byref long[]

[000000] ----------- | +--* LCL_VAR ref V02 arg2

[000001] ----------- | \--* LCL_VAR int V01 arg1

[000003] ----------- \--* CNS_INT long 0

LocalAddressVisitor visiting statement:

STMT00001 ( 0x005[E-] ... 0x009 )

[000011] nA-XG------ * STOREIND long

[000010] ---XG------ +--* INDEX_ADDR byref long[]

[000006] ----------- | +--* LCL_VAR ref V02 arg2

[000007] ----------- | \--* LCL_VAR int V01 arg1

[000009] ----------- \--* CNS_INT long 0

LocalAddressVisitor visiting statement:

STMT00002 ( 0x00A[E-] ... 0x00A )

[000012] ----------- * RETURN void

*************** Finishing PHASE Morph - Structs/AddrExp [no changes]

*************** Starting PHASE Early liveness

Local V03 should not be enregistered because: struct size does not match reg size

Tracked variable (2 out of 4) table:

V01 arg1 [ int]: refCnt = 2, refCntWtd = 0

V02 arg2 [ ref]: refCnt = 2, refCntWtd = 0

*************** In fgPerBlockLocalVarLiveness()

BB01 USE(2)={V01 V02}

DEF(0)={ }

** Memory liveness computed, GcHeap states and ByrefExposed states match

*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (2)={V01 V02}

OUT(0)={ }

*************** Finishing PHASE Early liveness

Trees after Early liveness

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00B) (return) i idxlen

-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01

STMT00000 ( 0x000[E-] ... 0x004 )

[000005] nA-XG------ * STOREIND long

[000004] ---XG------ +--* INDEX_ADDR byref long[]

[000000] ----------- | +--* LCL_VAR ref V02 arg2

[000001] ----------- | \--* LCL_VAR int V01 arg1

[000003] ----------- \--* CNS_INT long 0

***** BB01

STMT00001 ( 0x005[E-] ... 0x009 )

[000011] nA-XG------ * STOREIND long

[000010] ---XG------ +--* INDEX_ADDR byref long[]

[000006] ----------- | +--* LCL_VAR ref V02 arg2 (last use)

[000007] ----------- | \--* LCL_VAR int V01 arg1 (last use)

[000009] ----------- \--* CNS_INT long 0

***** BB01

STMT00002 ( 0x00A[E-] ... 0x00A )

[000012] ----------- * RETURN void

-------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE Forward Substitution

===> BB01

*************** Finishing PHASE Forward Substitution [no changes]

*************** Starting PHASE Physical promotion

*************** Finishing PHASE Physical promotion [no changes]

*************** Starting PHASE Identify candidates for implicit byref copy omission

*************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes]

*************** Starting PHASE Morph - ByRefs

*************** Finishing PHASE Morph - ByRefs [no changes]

*************** Starting PHASE Morph - Global

*************** In fgMorphBlocks()

Morphing BB01 of 'Program:Test(int,long[]):this'

fgMorphTree BB01, STMT00000 (before)

[000005] nA-XG------ * STOREIND long

[000004] ---XG------ +--* INDEX_ADDR byref long[]

[000000] ----------- | +--* LCL_VAR ref V02 arg2

[000001] ----------- | \--* LCL_VAR int V01 arg1

[000003] ----------- \--* CNS_INT long 0

fgMorphIndexAddr (before remorph):

[000024] ---X-O----- * COMMA byref

[000016] ---X-O----- +--* BOUNDS_CHECK_Rng void

[000001] ----------- | +--* LCL_VAR int V01 arg1

[000015] ---X------- | \--* ARR_LENGTH int

[000000] ----------- | \--* LCL_VAR ref V02 arg2

[000023] -----O----- \--* ARR_ADDR byref long[]

[000022] ----------- \--* ADD byref

[000013] ----------- +--* LCL_VAR ref V02 arg2

[000021] ----------- \--* ADD long

[000019] ----------- +--* MUL long

[000017] ---------U- | +--* CAST long <- uint

[000014] ----------- | | \--* LCL_VAR int V01 arg1

[000018] -------N--- | \--* CNS_INT long 8

[000020] ----------- \--* CNS_INT long 16

GenTreeNode creates assertion:

[000015] ---X-+----- * ARR_LENGTH int

In BB01 New Local Constant Assertion: V02 != null, index = #01

fgMorphIndexAddr (after remorph):

[000024] ---X-+----- * COMMA byref

[000016] ---X-+----- +--* BOUNDS_CHECK_Rng void

[000001] -----+----- | +--* LCL_VAR int V01 arg1

[000015] ---X-+----- | \--* ARR_LENGTH int

[000000] -----+----- | \--* LCL_VAR ref V02 arg2

[000023] -----+----- \--* ARR_ADDR byref long[]

[000022] -----+----- \--* ADD byref

[000013] -----+----- +--* LCL_VAR ref V02 arg2

[000021] -----+----- \--* ADD long

[000019] -----+----- +--* LSH long

[000017] -----+---U- | +--* CAST long <- uint

[000014] -----+----- | | \--* LCL_VAR int V01 arg1

[000018] -----+-N--- | \--* CNS_INT long 3

[000020] -----+----- \--* CNS_INT long

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****** START compiling Program:Test(int,long[]):this (MethodHash=57540ab3)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC  = false
OPTIONS: compProcedureSplitting   = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: optimizer should use profile data
IL to import:
IL_0000  04                ldarg.2     
IL_0001  03                ldarg.1     
IL_0002  16                ldc.i4.0    
IL_0003  6a                conv.i8     
IL_0004  9f                stelem.i8   
IL_0005  04                ldarg.2     
IL_0006  03                ldarg.1     
IL_0007  16                ldc.i4.0    
IL_0008  6a                conv.i8     
IL_0009  9f                stelem.i8   
IL_000a  2a                ret

lvaSetClass: setting class for V00 to (00000000D1FFAB1E) Program 
'this'    passed in register rcx
Arg #1    passed in register(s) rdx

lvaSetClass: setting class for V02 to (00000000D1FFAB1E) long[] 
Arg #2    passed in register(s) r8

lvaGrabTemp returning 3 (V03 tmp0) (a long lifetime temp) called for OutgoingArgSpace.

Local V03 should not be enregistered because: it is address exposed
; Initial local variable assignments
;
;  V00 this              ref  this class-hnd <Program>
;  V01 arg1              int 
;  V02 arg2              ref  class-hnd <long[]>
;  V03 OutArgs        struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for Program:Test(int,long[]):this
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 3
    	VarNum 	LVNum 	      Name 	Beg 	End
 0: 	00h 	00h 	  V00 this 	000h   	00Bh
 1: 	01h 	01h 	  V01 arg1 	000h   	00Bh
 2: 	02h 	02h 	  V02 arg2 	000h   	00Bh
info.compStmtOffsetsCount    = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:Test(int,long[]):this
Jump targets:
  none
New Basic Block BB01 [0000] created.
BB01 [000..00B)
IL Code Size,Instr   11,  11, Basic Block count   1, Local Variable Num,Ref count   4,  4 for method Program:Test(int,long[]):this
OPTIONS: opts.MinOpts() == false
Basic block list for 'Program:Test(int,long[]):this'

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import
Trees after Pre-import

------------ BB01 [000..00B) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'Program:Test(int,long[]):this'
    [ 0]   0 (0x000) ldarg.2
    [ 1]   1 (0x001) ldarg.1
    [ 2]   2 (0x002) ldc.i4.0 0
    [ 3]   3 (0x003) conv.i8
Folding long operator with constant nodes into a constant:
               [000003] -----------                         *  CAST      long <- int
               [000002] -----------                         \--*  CNS_INT   int    0
Bashed to long constant:
               [000003] -----------                         *  CNS_INT   long   0

[ 3]   4 (0x004) stelem.i8

STMT00000 ( 0x000[E-] ... ??? )
               [000005] nA-XG------                         *  STOREIND  long  
               [000004] ---XG------                         +--*  INDEX_ADDR byref long[]
               [000000] -----------                         |  +--*  LCL_VAR   ref    V02 arg2         
               [000001] -----------                         |  \--*  LCL_VAR   int    V01 arg1         
               [000003] -----------                         \--*  CNS_INT   long   0

[ 0]   5 (0x005) ldarg.2
    [ 1]   6 (0x006) ldarg.1
    [ 2]   7 (0x007) ldc.i4.0 0
    [ 3]   8 (0x008) conv.i8
Folding long operator with constant nodes into a constant:
               [000009] -----------                         *  CAST      long <- int
               [000008] -----------                         \--*  CNS_INT   int    0
Bashed to long constant:
               [000009] -----------                         *  CNS_INT   long   0

[ 3]   9 (0x009) stelem.i8

STMT00001 ( 0x005[E-] ... ??? )
               [000011] nA-XG------                         *  STOREIND  long  
               [000010] ---XG------                         +--*  INDEX_ADDR byref long[]
               [000006] -----------                         |  +--*  LCL_VAR   ref    V02 arg2         
               [000007] -----------                         |  \--*  LCL_VAR   int    V01 arg1         
               [000009] -----------                         \--*  CNS_INT   long   0

[ 0]  10 (0x00a) ret

STMT00002 ( 0x00A[E-] ... ??? )
               [000012] -----------                         *  RETURN    void

*************** Finishing PHASE Importation
Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x004 )
               [000005] nA-XG------                         *  STOREIND  long  
               [000004] ---XG------                         +--*  INDEX_ADDR byref long[]
               [000000] -----------                         |  +--*  LCL_VAR   ref    V02 arg2         
               [000001] -----------                         |  \--*  LCL_VAR   int    V01 arg1         
               [000003] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
               [000011] nA-XG------                         *  STOREIND  long  
               [000010] ---XG------                         +--*  INDEX_ADDR byref long[]
               [000006] -----------                         |  +--*  LCL_VAR   ref    V02 arg2         
               [000007] -----------                         |  \--*  LCL_VAR   int    V01 arg1         
               [000009] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----------                         *  RETURN    void

*************** Starting PHASE Expand patchpoints

-- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Indirect call transform

-- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import [no changes]

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Init [no changes]

*************** Starting PHASE Morph - Inlining
**************** Inline Tree

Inlines into 06000001 [via ExtendedDefaultPolicy] Program:Test(int,long[]):this:
Budget: initialTime=93, finalTime=93, initialBudget=930, currentBudget=930
Budget: initialSize=382, finalSize=382

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
=============== No blocks renumbered!

*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----------                         *  RETURN    void

*************** Starting PHASE Allocate Objects
no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks [no changes]

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally
No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Head and tail merge

*************** Finishing PHASE Head and tail merge
Trees after Head and tail merge

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----------                         *  RETURN    void

*************** Starting PHASE Merge throw blocks

*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.

*************** Finishing PHASE Merge throw blocks [no changes]

*************** Starting PHASE Update flow graph early pass

*************** Finishing PHASE Update flow graph early pass [no changes]

*************** Starting PHASE Morph - Promote Structs

lvaTable before fgPromoteStructs
; Initial local variable assignments
;
;  V00 this              ref  this class-hnd <Program>
;  V01 arg1              int 
;  V02 arg2              ref  class-hnd <long[]>
;  V03 OutArgs        struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
  struct promotion of V03 is disabled because it has already been marked address exposed

*************** Finishing PHASE Morph - Promote Structs [no changes]

*************** Starting PHASE Morph - Structs/AddrExp
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x004 )
               [000005] nA-XG------                         *  STOREIND  long  
               [000004] ---XG------                         +--*  INDEX_ADDR byref long[]
               [000000] -----------                         |  +--*  LCL_VAR   ref    V02 arg2         
               [000001] -----------                         |  \--*  LCL_VAR   int    V01 arg1         
               [000003] -----------                         \--*  CNS_INT   long   0

LocalAddressVisitor visiting statement:
STMT00001 ( 0x005[E-] ... 0x009 )
               [000011] nA-XG------                         *  STOREIND  long  
               [000010] ---XG------                         +--*  INDEX_ADDR byref long[]
               [000006] -----------                         |  +--*  LCL_VAR   ref    V02 arg2         
               [000007] -----------                         |  \--*  LCL_VAR   int    V01 arg1         
               [000009] -----------                         \--*  CNS_INT   long   0

LocalAddressVisitor visiting statement:
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----------                         *  RETURN    void

*************** Finishing PHASE Morph - Structs/AddrExp [no changes]

*************** Starting PHASE Early liveness

Local V03 should not be enregistered because: struct size does not match reg size
Tracked variable (2 out of 4) table:
V01 arg1          [   int]: refCnt =    2, refCntWtd =   0   
V02 arg2          [   ref]: refCnt =    2, refCntWtd =   0

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V01 V02}
     DEF(0)={       }

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (2)={V01 V02}
     OUT(0)={       }

*************** Finishing PHASE Early liveness
Trees after Early liveness

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
               [000011] nA-XG------                         *  STOREIND  long  
               [000010] ---XG------                         +--*  INDEX_ADDR byref long[]
               [000006] -----------                         |  +--*  LCL_VAR   ref    V02 arg2          (last use)
               [000007] -----------                         |  \--*  LCL_VAR   int    V01 arg1          (last use)
               [000009] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----------                         *  RETURN    void

*************** Starting PHASE Forward Substitution

===> BB01

*************** Finishing PHASE Forward Substitution [no changes]

*************** Starting PHASE Physical promotion

*************** Finishing PHASE Physical promotion [no changes]

*************** Starting PHASE Identify candidates for implicit byref copy omission

*************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes]

*************** Starting PHASE Morph - ByRefs

*************** Finishing PHASE Morph - ByRefs [no changes]

*************** Starting PHASE Morph - Global

*************** In fgMorphBlocks()

Morphing BB01 of 'Program:Test(int,long[]):this'

fgMorphTree BB01, STMT00000 (before)
               [000005] nA-XG------                         *  STOREIND  long  
               [000004] ---XG------                         +--*  INDEX_ADDR byref long[]
               [000000] -----------                         |  +--*  LCL_VAR   ref    V02 arg2         
               [000001] -----------                         |  \--*  LCL_VAR   int    V01 arg1         
               [000003] -----------                         \--*  CNS_INT   long   0
fgMorphIndexAddr (before remorph):
               [000024] ---X-O-----                         *  COMMA     byref 
               [000016] ---X-O-----                         +--*  BOUNDS_CHECK_Rng void  
               [000001] -----------                         |  +--*  LCL_VAR   int    V01 arg1         
               [000015] ---X-------                         |  \--*  ARR_LENGTH int   
               [000000] -----------                         |     \--*  LCL_VAR   ref    V02 arg2         
               [000023] -----O-----                         \--*  ARR_ADDR  byref long[]
               [000022] -----------                            \--*  ADD       byref 
               [000013] -----------                               +--*  LCL_VAR   ref    V02 arg2         
               [000021] -----------                               \--*  ADD       long  
               [000019] -----------                                  +--*  MUL       long  
               [000017] ---------U-                                  |  +--*  CAST      long <- uint
               [000014] -----------                                  |  |  \--*  LCL_VAR   int    V01 arg1         
               [000018] -------N---                                  |  \--*  CNS_INT   long   8
               [000020] -----------                                  \--*  CNS_INT   long   16
GenTreeNode creates assertion:
               [000015] ---X-+-----                         *  ARR_LENGTH int   
In BB01 New Local Constant Assertion: V02 != null, index = #01
fgMorphIndexAddr (after remorph):
               [000024] ---X-+-----                         *  COMMA     byref 
               [000016] ---X-+-----                         +--*  BOUNDS_CHECK_Rng void  
               [000001] -----+-----                         |  +--*  LCL_VAR   int    V01 arg1         
               [000015] ---X-+-----                         |  \--*  ARR_LENGTH int   
               [000000] -----+-----                         |     \--*  LCL_VAR   ref    V02 arg2         
               [000023] -----+-----                         \--*  ARR_ADDR  byref long[]
               [000022] -----+-----                            \--*  ADD       byref 
               [000013] -----+-----                               +--*  LCL_VAR   ref    V02 arg2         
               [000021] -----+-----                               \--*  ADD       long  
               [000019] -----+-----                                  +--*  LSH       long  
               [000017] -----+---U-                                  |  +--*  CAST      long <- uint
               [000014] -----+-----                                  |  |  \--*  LCL_VAR   int    V01 arg1         
               [000018] -----+-N---                                  |  \--*  CNS_INT   long   3
               [000020] -----+-----                                  \--*  CNS_INT   long   16

fgMorphTree BB01, STMT00000 (after)
               [000005] nA-XG+-----                         *  STOREIND  long  
               [000024] ---X-+-----                         +--*  COMMA     byref 
               [000016] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000001] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1         
               [000015] ---X-+-----                         |  |  \--*  ARR_LENGTH int   
               [000000] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2         
               [000023] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000022] -----+-----                         |     \--*  ADD       byref 
               [000013] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2         
               [000021] -----+-----                         |        \--*  ADD       long  
               [000019] -----+-----                         |           +--*  LSH       long  
               [000017] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000014] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
               [000018] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000020] -----+-----                         |           \--*  CNS_INT   long   16
               [000003] -----+-----                         \--*  CNS_INT   long   0

fgMorphTree BB01, STMT00001 (before)
               [000011] nA-XG------                         *  STOREIND  long  
               [000010] ---XG------                         +--*  INDEX_ADDR byref long[]
               [000006] -----------                         |  +--*  LCL_VAR   ref    V02 arg2          (last use)
               [000007] -----------                         |  \--*  LCL_VAR   int    V01 arg1          (last use)
               [000009] -----------                         \--*  CNS_INT   long   0
fgMorphIndexAddr (before remorph):
               [000036] ---X-O-----                         *  COMMA     byref 
               [000028] ---X-O-----                         +--*  BOUNDS_CHECK_Rng void  
               [000007] -----------                         |  +--*  LCL_VAR   int    V01 arg1          (last use)
               [000027] ---X-------                         |  \--*  ARR_LENGTH int   
               [000006] -----------                         |     \--*  LCL_VAR   ref    V02 arg2          (last use)
               [000035] -----O-----                         \--*  ARR_ADDR  byref long[]
               [000034] -----------                            \--*  ADD       byref 
               [000025] -----------                               +--*  LCL_VAR   ref    V02 arg2          (last use)
               [000033] -----------                               \--*  ADD       long  
               [000031] -----------                                  +--*  MUL       long  
               [000029] ---------U-                                  |  +--*  CAST      long <- uint
               [000026] -----------                                  |  |  \--*  LCL_VAR   int    V01 arg1          (last use)
               [000030] -------N---                                  |  \--*  CNS_INT   long   8
               [000032] -----------                                  \--*  CNS_INT   long   16
fgMorphIndexAddr (after remorph):
               [000036] ---X-+-----                         *  COMMA     byref 
               [000028] ---X-+-----                         +--*  BOUNDS_CHECK_Rng void  
               [000007] -----+-----                         |  +--*  LCL_VAR   int    V01 arg1          (last use)
               [000027] ---X-+-----                         |  \--*  ARR_LENGTH int   
               [000006] -----+-----                         |     \--*  LCL_VAR   ref    V02 arg2          (last use)
               [000035] -----+-----                         \--*  ARR_ADDR  byref long[]
               [000034] -----+-----                            \--*  ADD       byref 
               [000025] -----+-----                               +--*  LCL_VAR   ref    V02 arg2          (last use)
               [000033] -----+-----                               \--*  ADD       long  
               [000031] -----+-----                                  +--*  LSH       long  
               [000029] -----+---U-                                  |  +--*  CAST      long <- uint
               [000026] -----+-----                                  |  |  \--*  LCL_VAR   int    V01 arg1          (last use)
               [000030] -----+-N---                                  |  \--*  CNS_INT   long   3
               [000032] -----+-----                                  \--*  CNS_INT   long   16

fgMorphTree BB01, STMT00001 (after)
               [000011] nA-XG+-----                         *  STOREIND  long  
               [000036] ---X-+-----                         +--*  COMMA     byref 
               [000028] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000007] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1          (last use)
               [000027] ---X-+-----                         |  |  \--*  ARR_LENGTH int   
               [000006] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2          (last use)
               [000035] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000034] -----+-----                         |     \--*  ADD       byref 
               [000025] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2          (last use)
               [000033] -----+-----                         |        \--*  ADD       long  
               [000031] -----+-----                         |           +--*  LSH       long  
               [000029] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000026] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1          (last use)
               [000030] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000032] -----+-----                         |           \--*  CNS_INT   long   16
               [000009] -----+-----                         \--*  CNS_INT   long   0

fgMorphTree BB01, STMT00002 (before)
               [000012] -----------                         *  RETURN    void

*************** In fgMarkDemotedImplicitByRefArgs()

*************** Finishing PHASE Morph - Global
Trees after Morph - Global

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x004 )
               [000005] nA-XG+-----                         *  STOREIND  long  
               [000024] ---X-+-----                         +--*  COMMA     byref 
               [000016] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000001] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1         
               [000015] ---X-+-----                         |  |  \--*  ARR_LENGTH int   
               [000000] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2         
               [000023] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000022] -----+-----                         |     \--*  ADD       byref 
               [000013] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2         
               [000021] -----+-----                         |        \--*  ADD       long  
               [000019] -----+-----                         |           +--*  LSH       long  
               [000017] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000014] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
               [000018] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000020] -----+-----                         |           \--*  CNS_INT   long   16
               [000003] -----+-----                         \--*  CNS_INT   long   0

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
               [000011] nA-XG+-----                         *  STOREIND  long  
               [000036] ---X-+-----                         +--*  COMMA     byref 
               [000028] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000007] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1         
               [000027] ---X-+-----                         |  |  \--*  ARR_LENGTH int   
               [000006] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2         
               [000035] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000034] -----+-----                         |     \--*  ADD       byref 
               [000025] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2         
               [000033] -----+-----                         |        \--*  ADD       long  
               [000031] -----+-----                         |           +--*  LSH       long  
               [000029] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000026] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
               [000030] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000032] -----+-----                         |           \--*  CNS_INT   long   16
               [000009] -----+-----                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----+-----                         *  RETURN    void

*************** Starting PHASE GS Cookie
No GS security needed

*************** Finishing PHASE GS Cookie [no changes]

*************** Starting PHASE Compute edge weights (1, false)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

-- no profile data, so using default called count
 -- not optimizing or no profile data, so not computing edge weights

*************** Finishing PHASE Compute edge weights (1, false) [no changes]

*************** Starting PHASE Create EH funclets

*************** Finishing PHASE Create EH funclets [no changes]

*************** Starting PHASE Invert loops

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
=============== No blocks renumbered!

*************** Finishing PHASE Invert loops [no changes]

*************** Starting PHASE Optimize control flow

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize control flow
Trees after Optimize control flow

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----+-----                         *  RETURN    void

*************** Starting PHASE Post-morph head and tail merge

*************** Finishing PHASE Post-morph head and tail merge
Trees after Post-morph head and tail merge

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----+-----                         *  RETURN    void

*************** Starting PHASE Compute blocks reachability
Return blocks: BB01

Renumbering the basic blocks for fgComputeReachability pass #1

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
=============== No blocks renumbered!
Enter blocks: BB01

Dominator computation start blocks (those blocks with no incoming edges):
BB01

After computing reachability sets:
------------------------------------------------
BBnum  Reachable by 
------------------------------------------------
BB01 : BB01 
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
------------------------------------------------
BBnum  Dominated by
------------------------------------------------
BB01:  BB01

Inside fgBuildDomTree

After computing the Dominance Tree:

After numbering the dominator tree:
BB01: pre=01, post=01

*************** Finishing PHASE Compute blocks reachability [no changes]

*************** Starting PHASE Set block weights

*************** Finishing PHASE Set block weights [no changes]

*************** Starting PHASE Find loops
*************** In optFindLoops()
*************** In optMarkLoopHeads()
0 loop heads marked

*************** Finishing PHASE Find loops
Trees after Find loops

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----+-----                         *  RETURN    void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Clone loops

*************** In optCloneLoops()
  No loops to clone

*************** Finishing PHASE Clone loops [no changes]

*************** Starting PHASE Unroll loops

*************** Finishing PHASE Unroll loops [no changes]

*************** Starting PHASE Clear loop info

*************** Finishing PHASE Clear loop info [no changes]

*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function

*************** Finishing PHASE Morph array ops [no changes]

*************** Starting PHASE Mark local vars

*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** marking local variables in block BB01 (weight=1)
STMT00000 ( 0x000[E-] ... 0x004 )
               [000005] nA-XG+-----                         *  STOREIND  long  
               [000024] ---X-+-----                         +--*  COMMA     byref 
               [000016] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000001] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1         
               [000015] ---X-+-----                         |  |  \--*  ARR_LENGTH int   
               [000000] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2         
               [000023] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000022] -----+-----                         |     \--*  ADD       byref 
               [000013] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2         
               [000021] -----+-----                         |        \--*  ADD       long  
               [000019] -----+-----                         |           +--*  LSH       long  
               [000017] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000014] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
               [000018] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000020] -----+-----                         |           \--*  CNS_INT   long   16
               [000003] -----+-----                         \--*  CNS_INT   long   0
New refCnts for V01: refCnt =  1, refCntWtd = 1
New refCnts for V02: refCnt =  1, refCntWtd = 1
New refCnts for V02: refCnt =  2, refCntWtd = 2
New refCnts for V01: refCnt =  2, refCntWtd = 2
STMT00001 ( 0x005[E-] ... 0x009 )
               [000011] nA-XG+-----                         *  STOREIND  long  
               [000036] ---X-+-----                         +--*  COMMA     byref 
               [000028] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000007] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1         
               [000027] ---X-+-----                         |  |  \--*  ARR_LENGTH int   
               [000006] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2         
               [000035] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000034] -----+-----                         |     \--*  ADD       byref 
               [000025] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2         
               [000033] -----+-----                         |        \--*  ADD       long  
               [000031] -----+-----                         |           +--*  LSH       long  
               [000029] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000026] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
               [000030] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000032] -----+-----                         |           \--*  CNS_INT   long   16
               [000009] -----+-----                         \--*  CNS_INT   long   0
New refCnts for V01: refCnt =  3, refCntWtd = 3
New refCnts for V02: refCnt =  3, refCntWtd = 3
New refCnts for V02: refCnt =  4, refCntWtd = 4
New refCnts for V01: refCnt =  4, refCntWtd = 4
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----+-----                         *  RETURN    void

*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V01: refCnt =  5, refCntWtd = 5
New refCnts for V01: refCnt =  6, refCntWtd = 6
New refCnts for V02: refCnt =  5, refCntWtd = 5
New refCnts for V02: refCnt =  6, refCntWtd = 6

*************** Finishing PHASE Mark local vars [no changes]

*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()

*************** Finishing PHASE Find oper order
Trees after Find oper order

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x004 )
     ( 16, 20) [000005] nA-XGO-----                         *  STOREIND  long  
     ( 11, 16) [000024] ---X-O-----                         +--*  COMMA     byref 
     (  8, 11) [000016] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
     (  1,  1) [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         
     (  3,  3) [000015] ---X-------                         |  |  \--*  ARR_LENGTH int   
     (  1,  1) [000000] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         
     (  3,  5) [000023] -----O-----                         |  \--*  ARR_ADDR  byref long[]
     (  3,  5) [000022] -------N---                         |     \--*  ADD       byref 
     (  1,  1) [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         
     (  4,  5) [000021] -------N---                         |        \--*  ADD       long  
     (  3,  4) [000019] -------N---                         |           +--*  LSH       long  
     (  2,  3) [000017] ---------U-                         |           |  +--*  CAST      long <- uint
     (  1,  1) [000014] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
     (  1,  1) [000018] -------N---                         |           |  \--*  CNS_INT   long   3
     (  1,  1) [000020] -----------                         |           \--*  CNS_INT   long   16
     (  1,  1) [000003] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
     ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long  
     ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref 
     (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
     (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         
     (  3,  3) [000027] ---X-------                         |  |  \--*  ARR_LENGTH int   
     (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         
     (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[]
     (  3,  5) [000034] -------N---                         |     \--*  ADD       byref 
     (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         
     (  4,  5) [000033] -------N---                         |        \--*  ADD       long  
     (  3,  4) [000031] -------N---                         |           +--*  LSH       long  
     (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint
     (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
     (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3
     (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16
     (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
     (  0,  0) [000012] -----------                         *  RETURN    void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has   16 tree nodes

*************** Finishing PHASE Set block order
Trees after Set block order

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x004 )
N016 ( 16, 20) [000005] nA-XGO-----                         *  STOREIND  long  
N014 ( 11, 16) [000024] ---X-O-----                         +--*  COMMA     byref 
N004 (  8, 11) [000016] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
N001 (  1,  1) [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         
N003 (  3,  3) [000015] ---X-------                         |  |  \--*  ARR_LENGTH int   
N002 (  1,  1) [000000] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         
N013 (  3,  5) [000023] -----O-----                         |  \--*  ARR_ADDR  byref long[]
N012 (  3,  5) [000022] -------N---                         |     \--*  ADD       byref 
N005 (  1,  1) [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         
N011 (  4,  5) [000021] -------N---                         |        \--*  ADD       long  
N009 (  3,  4) [000019] -------N---                         |           +--*  LSH       long  
N007 (  2,  3) [000017] ---------U-                         |           |  +--*  CAST      long <- uint
N006 (  1,  1) [000014] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
N008 (  1,  1) [000018] -------N---                         |           |  \--*  CNS_INT   long   3
N010 (  1,  1) [000020] -----------                         |           \--*  CNS_INT   long   16
N015 (  1,  1) [000003] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
N016 ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long  
N014 ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref 
N004 (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
N001 (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         
N003 (  3,  3) [000027] ---X-------                         |  |  \--*  ARR_LENGTH int   
N002 (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         
N013 (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[]
N012 (  3,  5) [000034] -------N---                         |     \--*  ADD       byref 
N005 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         
N011 (  4,  5) [000033] -------N---                         |        \--*  ADD       long  
N009 (  3,  4) [000031] -------N---                         |           +--*  LSH       long  
N007 (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint
N006 (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
N008 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3
N010 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16
N015 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0) [000012] -----------                         *  RETURN    void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 2.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]

Inside fgBuildDomTree

After computing the Dominance Tree:

*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit

Local V03 should not be enregistered because: struct size does not match reg size
Tracked variable (2 out of 4) table:
V02 arg2          [   ref]: refCnt =    6, refCntWtd =   6   
V01 arg1          [   int]: refCnt =    6, refCntWtd =   6

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V02 V01}
     DEF(0)={       } + ByrefExposed + GcHeap

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (2)={V02 V01}
     OUT(0)={       }

*************** In optRemoveRedundantZeroInits()
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
V01.1: defined in BB00 4 uses (global)
V02.1: defined in BB00 4 uses (global)

*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x004 )
N016 ( 16, 20) [000005] nA-XGO-----                         *  STOREIND  long  
N014 ( 11, 16) [000024] ---X-O-----                         +--*  COMMA     byref 
N004 (  8, 11) [000016] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
N001 (  1,  1) [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1
N003 (  3,  3) [000015] ---X-------                         |  |  \--*  ARR_LENGTH int   
N002 (  1,  1) [000000] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1
N013 (  3,  5) [000023] -----O-----                         |  \--*  ARR_ADDR  byref long[]
N012 (  3,  5) [000022] -------N---                         |     \--*  ADD       byref 
N005 (  1,  1) [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1
N011 (  4,  5) [000021] -------N---                         |        \--*  ADD       long  
N009 (  3,  4) [000019] -------N---                         |           +--*  LSH       long  
N007 (  2,  3) [000017] ---------U-                         |           |  +--*  CAST      long <- uint
N006 (  1,  1) [000014] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1
N008 (  1,  1) [000018] -------N---                         |           |  \--*  CNS_INT   long   3
N010 (  1,  1) [000020] -----------                         |           \--*  CNS_INT   long   16
N015 (  1,  1) [000003] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
N016 ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long  
N014 ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref 
N004 (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
N001 (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1
N003 (  3,  3) [000027] ---X-------                         |  |  \--*  ARR_LENGTH int   
N002 (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1
N013 (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[]
N012 (  3,  5) [000034] -------N---                         |     \--*  ADD       byref 
N005 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use)
N011 (  4,  5) [000033] -------N---                         |        \--*  ADD       long  
N009 (  3,  4) [000031] -------N---                         |           +--*  LSH       long  
N007 (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint
N006 (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use)
N008 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3
N010 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16
N015 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0) [000012] -----------                         *  RETURN    void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V01.1
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method

*************** Finishing PHASE Early Value Propagation [no changes]

*************** Starting PHASE Do value numbering

*************** In fgValueNumber()
Memory Initial Value in BB01 is: $100
The SSA definition for ByrefExposed (#1) at start of BB01 is $100 {InitVal($42)}
The SSA definition for GcHeap (#1) at start of BB01 is $100 {InitVal($42)}

***** BB01, STMT00000(before)
N016 ( 16, 20) [000005] nA-XGO-----                         *  STOREIND  long  
N014 ( 11, 16) [000024] ---X-O-----                         +--*  COMMA     byref 
N004 (  8, 11) [000016] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
N001 (  1,  1) [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1
N003 (  3,  3) [000015] ---X-------                         |  |  \--*  ARR_LENGTH int   
N002 (  1,  1) [000000] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1
N013 (  3,  5) [000023] -----O-----                         |  \--*  ARR_ADDR  byref long[]
N012 (  3,  5) [000022] -------N---                         |     \--*  ADD       byref 
N005 (  1,  1) [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1
N011 (  4,  5) [000021] -------N---                         |        \--*  ADD       long  
N009 (  3,  4) [000019] -------N---                         |           +--*  LSH       long  
N007 (  2,  3) [000017] ---------U-                         |           |  +--*  CAST      long <- uint
N006 (  1,  1) [000014] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1
N008 (  1,  1) [000018] -------N---                         |           |  \--*  CNS_INT   long   3
N010 (  1,  1) [000020] -----------                         |           \--*  CNS_INT   long   16
N015 (  1,  1) [000003] -----------                         \--*  CNS_INT   long   0

N001 [000001]   LCL_VAR   V01 arg1         u:1 => $80 {InitVal($40)}
N002 [000000]   LCL_VAR   V02 arg2         u:1 => $c0 {InitVal($41)}
N003 [000015]   ARR_LENGTH => $180 {norm=$81 {ARR_LENGTH($c0)}, exc=$140 {NullPtrExc($c0)}}
N004 [000016]   BOUNDS_CHECK_Rng => $145 {norm=$VN.Void, exc=$144( {NullPtrExc($c0)},  {IndexOutOfRangeExc($80, $81)})}
N005 [000013]   LCL_VAR   V02 arg2         u:1 => $c0 {InitVal($41)}
N006 [000014]   LCL_VAR   V01 arg1         u:1 => $80 {InitVal($40)}
N007 [000017]   CAST      => $1c0 {$80, long <- uint}
N008 [000018]   CNS_INT   3 => $200 {LngCns:  3}
N009 [000019]   LSH       => $1c1 {LSH($1c0, $200)}
N010 [000020]   CNS_INT   16 => $202 {LngCns:  16}
N011 [000021]   ADD       => $1c2 {ADD($1c1, $202)}
N012 [000022]   ADD       => $240 {ADD($c0, $1c2)}
    VNForHandle(arrElemType: long) is $280
N013 [000023]   ARR_ADDR  => $2c0 {PtrToArrElem($280, $c0, $1c0, $201)}
N014 [000024]   COMMA     => $241 {norm=$2c0 {PtrToArrElem($280, $c0, $1c0, $201)}, exc=$144( {NullPtrExc($c0)},  {IndexOutOfRangeExc($80, $81)})}
N015 [000003]   CNS_INT   0 => $201 {LngCns:  0}
  Array element store: elemTypeEq is $280 for long[]
    VNForMapSelect($100, $280):mem returns $300 {$100[$280]}
  GcHeap[elemTypeEq: $280] is $300
    VNForMapSelect($300, $c0):mem returns $301 {$300[$c0]}
  GcHeap[elemTypeEq][array: $c0] is $301
  GcHeap[elemTypeEq][array][index: $1c0] = $201:
    VNForMapStore($301, $1c0, $201):mem in BB01 returns $340 {$301[$1c0 := $201]}
  GcHeap[elemTypeEq][array: $c0] = $340:
    VNForMapStore($300, $c0, $340):mem in BB01 returns $341 {$300[$c0 := $340]}
  GcHeap[elemTypeEq: $280] = $341:
    VNForMapStore($100, $280, $341):heap in BB01 returns $380 {$100[$280 := $341]}
  fgCurMemoryVN[GcHeap] assigned for array element store at [000005] to VN: $380.
N016 [000005]   STOREIND  => $145 {norm=$VN.Void, exc=$144( {NullPtrExc($c0)},  {IndexOutOfRangeExc($80, $81)})}

***** BB01, STMT00000(after)
N016 ( 16, 20) [000005] nA-XGO-----                         *  STOREIND  long   $145
N014 ( 11, 16) [000024] ---X-O-----                         +--*  COMMA     byref  $241
N004 (  8, 11) [000016] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1) [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) [000015] ---X-------                         |  |  \--*  ARR_LENGTH int    $180
N002 (  1,  1) [000000] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5) [000023] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5) [000022] -------N---                         |     \--*  ADD       byref  $240
N005 (  1,  1) [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N011 (  4,  5) [000021] -------N---                         |        \--*  ADD       long   $1c2
N009 (  3,  4) [000019] -------N---                         |           +--*  LSH       long   $1c1
N007 (  2,  3) [000017] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N006 (  1,  1) [000014] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 $80
N008 (  1,  1) [000018] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N010 (  1,  1) [000020] -----------                         |           \--*  CNS_INT   long   16 $202
N015 (  1,  1) [000003] -----------                         \--*  CNS_INT   long   0 $201

---------

***** BB01, STMT00001(before)
N016 ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long  
N014 ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref 
N004 (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
N001 (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1
N003 (  3,  3) [000027] ---X-------                         |  |  \--*  ARR_LENGTH int   
N002 (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1
N013 (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[]
N012 (  3,  5) [000034] -------N---                         |     \--*  ADD       byref 
N005 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use)
N011 (  4,  5) [000033] -------N---                         |        \--*  ADD       long  
N009 (  3,  4) [000031] -------N---                         |           +--*  LSH       long  
N007 (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint
N006 (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use)
N008 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3
N010 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16
N015 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0

N001 [000007]   LCL_VAR   V01 arg1         u:1 => $80 {InitVal($40)}
N002 [000006]   LCL_VAR   V02 arg2         u:1 => $c0 {InitVal($41)}
N003 [000027]   ARR_LENGTH => $180 {norm=$81 {ARR_LENGTH($c0)}, exc=$140 {NullPtrExc($c0)}}
N004 [000028]   BOUNDS_CHECK_Rng => $145 {norm=$VN.Void, exc=$144( {NullPtrExc($c0)},  {IndexOutOfRangeExc($80, $81)})}
N005 [000025]   LCL_VAR   V02 arg2         u:1 (last use) => $c0 {InitVal($41)}
N006 [000026]   LCL_VAR   V01 arg1         u:1 (last use) => $80 {InitVal($40)}
N007 [000029]   CAST      => $1c0 {$80, long <- uint}
N008 [000030]   CNS_INT   3 => $200 {LngCns:  3}
N009 [000031]   LSH       => $1c1 {LSH($1c0, $200)}
N010 [000032]   CNS_INT   16 => $202 {LngCns:  16}
N011 [000033]   ADD       => $1c2 {ADD($1c1, $202)}
N012 [000034]   ADD       => $240 {ADD($c0, $1c2)}
    VNForHandle(arrElemType: long) is $280
N013 [000035]   ARR_ADDR  => $2c0 {PtrToArrElem($280, $c0, $1c0, $201)}
N014 [000036]   COMMA     => $241 {norm=$2c0 {PtrToArrElem($280, $c0, $1c0, $201)}, exc=$144( {NullPtrExc($c0)},  {IndexOutOfRangeExc($80, $81)})}
N015 [000009]   CNS_INT   0 => $201 {LngCns:  0}
  Array element store: elemTypeEq is $280 for long[]
      AX1: select([$100]store($380, $280, $341), $280) ==> $341.
    VNForMapSelect($380, $280):mem returns $341 {$300[$c0 := $340]}
  GcHeap[elemTypeEq: $280] is $341
      AX1: select([$300]store($341, $c0, $340), $c0) ==> $340.
    VNForMapSelect($341, $c0):mem returns $340 {$301[$1c0 := $201]}
  GcHeap[elemTypeEq][array: $c0] is $340
  GcHeap[elemTypeEq][array][index: $1c0] = $201:
    VNForMapStore($340, $1c0, $201):mem in BB01 returns $342 {$340[$1c0 := $201]}
  GcHeap[elemTypeEq][array: $c0] = $342:
    VNForMapStore($341, $c0, $342):mem in BB01 returns $343 {$341[$c0 := $342]}
  GcHeap[elemTypeEq: $280] = $343:
    VNForMapStore($380, $280, $343):heap in BB01 returns $381 {$380[$280 := $343]}
  fgCurMemoryVN[GcHeap] assigned for array element store at [000011] to VN: $381.
N016 [000011]   STOREIND  => $145 {norm=$VN.Void, exc=$144( {NullPtrExc($c0)},  {IndexOutOfRangeExc($80, $81)})}

***** BB01, STMT00001(after)
N016 ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long   $145
N014 ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref  $241
N004 (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) [000027] ---X-------                         |  |  \--*  ARR_LENGTH int    $180
N002 (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5) [000034] -------N---                         |     \--*  ADD       byref  $240
N005 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N011 (  4,  5) [000033] -------N---                         |        \--*  ADD       long   $1c2
N009 (  3,  4) [000031] -------N---                         |           +--*  LSH       long   $1c1
N007 (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N006 (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use) $80
N008 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N010 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16 $202
N015 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0 $201

---------

***** BB01, STMT00002(before)
N001 (  0,  0) [000012] -----------                         *  RETURN    void

N001 [000012]   RETURN    => $VN.Void

***** BB01, STMT00002(after)
N001 (  0,  0) [000012] -----------                         *  RETURN    void   $VN.Void

finish(BB01).

*************** Finishing PHASE Do value numbering
Trees after Do value numbering

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x004 )
N016 ( 16, 20) [000005] nA-XGO-----                         *  STOREIND  long   $145
N014 ( 11, 16) [000024] ---X-O-----                         +--*  COMMA     byref  $241
N004 (  8, 11) [000016] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1) [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) [000015] ---X-------                         |  |  \--*  ARR_LENGTH int    $180
N002 (  1,  1) [000000] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5) [000023] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5) [000022] -------N---                         |     \--*  ADD       byref  $240
N005 (  1,  1) [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N011 (  4,  5) [000021] -------N---                         |        \--*  ADD       long   $1c2
N009 (  3,  4) [000019] -------N---                         |           +--*  LSH       long   $1c1
N007 (  2,  3) [000017] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N006 (  1,  1) [000014] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 $80
N008 (  1,  1) [000018] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N010 (  1,  1) [000020] -----------                         |           \--*  CNS_INT   long   16 $202
N015 (  1,  1) [000003] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
N016 ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long   $145
N014 ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref  $241
N004 (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) [000027] ---X-------                         |  |  \--*  ARR_LENGTH int    $180
N002 (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5) [000034] -------N---                         |     \--*  ADD       byref  $240
N005 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N011 (  4,  5) [000033] -------N---                         |        \--*  ADD       long   $1c2
N009 (  3,  4) [000031] -------N---                         |           +--*  LSH       long   $1c1
N007 (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N006 (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use) $80
N008 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N010 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16 $202
N015 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0) [000012] -----------                         *  RETURN    void   $VN.Void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V01.1
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Hoist loop code

No loops; no hoisting

*************** Finishing PHASE Hoist loop code [no changes]

*************** Starting PHASE VN based copy prop
Copy Assertion for BB01
  curSsaName stack: { }

Live vars after [000025]: {V01 V02} -{V02} => {V01}
							Live vars after [000026]: {V01} -{V01} => {}

*************** Finishing PHASE VN based copy prop [no changes]

*************** Starting PHASE Redundant branch opts

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Redundant branch opts [no changes]

*************** Starting PHASE Optimize Valnum CSEs

Candidate CSE #01, key=$81 in BB01, [cost= 3, size= 3]: 
N003 (  3,  3) CSE #01 (use)[000027] ---X-------                         *  ARR_LENGTH int    $180
N002 (  1,  1)              [000006] -----------                         \--*  LCL_VAR   ref    V02 arg2         u:1 $c0

Candidate CSE #02, key=$1c0 in BB01, [cost= 2, size= 3]: 
N007 (  2,  3) CSE #02 (use)[000029] ---------U-                         *  CAST      long <- uint $1c0
N006 (  1,  1)              [000026] -----------                         \--*  LCL_VAR   int    V01 arg1         u:1 (last use) $80

Candidate CSE #03, key=$241 in BB01, [cost=11, size=16]: 
N014 ( 11, 16) CSE #03 (use)[000036] ---X-O-----                         *  COMMA     byref  $241
N004 (  8, 11)              [000028] ---X-O-----                         +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1)              [000007] -----------                         |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) CSE #01 (use)[000027] ---X-------                         |  \--*  ARR_LENGTH int    $180
N002 (  1,  1)              [000006] -----------                         |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5)              [000035] -----O-----                         \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5)              [000034] -------N---                            \--*  ADD       byref  $240
N005 (  1,  1)              [000025] -----------                               +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N011 (  4,  5)              [000033] -------N---                               \--*  ADD       long   $1c2
N009 (  3,  4)              [000031] -------N---                                  +--*  LSH       long   $1c1
N007 (  2,  3) CSE #02 (use)[000029] ---------U-                                  |  +--*  CAST      long <- uint $1c0
N006 (  1,  1)              [000026] -----------                                  |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use) $80
N008 (  1,  1)              [000030] -------N---                                  |  \--*  CNS_INT   long   3 $200
N010 (  1,  1)              [000032] -----------                                  \--*  CNS_INT   long   16 $202

Blocks that generate CSE def/uses
BB01 cseGen = 000000000000003F CSE #01.c, CSE #02.c, CSE #03.c
[info] HasGlobalUse overestimated for V01.1
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully

Performing DataFlow for ValnumCSE's

After performing DataFlow for ValnumCSE's
BB01
 in: 0000000000000000 
gen: 000000000000003F CSE #01.c, CSE #02.c, CSE #03.c
out: 000000000000003F CSE #01.c, CSE #02.c, CSE #03.c

Labeling the CSEs with Use/Def information
BB01 [000015] Def of CSE #01 [weight=1]
BB01 [000017] Def of CSE #02 [weight=1]
BB01 [000024] Def of CSE #03 [weight=1]
BB01 [000027] Use of CSE #01 [weight=1]
BB01 [000029] Use of CSE #02 [weight=1]
BB01 [000036] Use of CSE #03 [weight=1]

************ Trees at start of optValnumCSE_Heuristic()

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x004 )
N016 ( 16, 20)              [000005] nA-XGO-----                         *  STOREIND  long   $145
N014 ( 11, 16) CSE #03 (def)[000024] ---X-O-----                         +--*  COMMA     byref  $241
N004 (  8, 11)              [000016] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1)              [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) CSE #01 (def)[000015] ---X-------                         |  |  \--*  ARR_LENGTH int    $180
N002 (  1,  1)              [000000] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5)              [000023] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5)              [000022] -------N---                         |     \--*  ADD       byref  $240
N005 (  1,  1)              [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N011 (  4,  5)              [000021] -------N---                         |        \--*  ADD       long   $1c2
N009 (  3,  4)              [000019] -------N---                         |           +--*  LSH       long   $1c1
N007 (  2,  3) CSE #02 (def)[000017] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N006 (  1,  1)              [000014] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 $80
N008 (  1,  1)              [000018] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N010 (  1,  1)              [000020] -----------                         |           \--*  CNS_INT   long   16 $202
N015 (  1,  1)              [000003] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
N016 ( 16, 20)              [000011] nA-XGO-----                         *  STOREIND  long   $145
N014 ( 11, 16) CSE #03 (use)[000036] ---X-O-----                         +--*  COMMA     byref  $241
N004 (  8, 11)              [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1)              [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) CSE #01 (use)[000027] ---X-------                         |  |  \--*  ARR_LENGTH int    $180
N002 (  1,  1)              [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5)              [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5)              [000034] -------N---                         |     \--*  ADD       byref  $240
N005 (  1,  1)              [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N011 (  4,  5)              [000033] -------N---                         |        \--*  ADD       long   $1c2
N009 (  3,  4)              [000031] -------N---                         |           +--*  LSH       long   $1c1
N007 (  2,  3) CSE #02 (use)[000029] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N006 (  1,  1)              [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use) $80
N008 (  1,  1)              [000030] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N010 (  1,  1)              [000032] -----------                         |           \--*  CNS_INT   long   16 $202
N015 (  1,  1)              [000009] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0)              [000012] -----------                         *  RETURN    void   $VN.Void

-------------------------------------------------------------------------------------------------------------------

Aggressive CSE Promotion cutoff is 200.000000
Moderate CSE Promotion cutoff is 100.000000
enregCount is 2
Framesize estimate is 0x0000
We have a small frame

Sorted CSE candidates:
CSE #03, {$241, $144} useCnt=1: [def=100.000000, use=100.000000, cost= 11      ]
        :: N014 ( 11, 16) CSE #03 (def)[000024] ---X-O-----                         *  COMMA     byref  $241
CSE #01, {$81 , $140} useCnt=1: [def=100.000000, use=100.000000, cost=  3      ]
        :: N003 (  3,  3) CSE #01 (def)[000015] ---X-------                         *  ARR_LENGTH int    $180
CSE #02, {$1c0, $2  } useCnt=1: [def=100.000000, use=100.000000, cost=  2      ]
        :: N007 (  2,  3) CSE #02 (def)[000017] ---------U-                         *  CAST      long <- uint $1c0

Considering CSE #03 {$241, $144} [def=100.000000, use=100.000000, cost= 11      ]
CSE Expression : 
N014 ( 11, 16) CSE #03 (def)[000024] ---X-O-----                         *  COMMA     byref  $241
N004 (  8, 11)              [000016] ---X-O-----                         +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1)              [000001] -----------                         |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) CSE #01 (def)[000015] ---X-------                         |  \--*  ARR_LENGTH int    $180
N002 (  1,  1)              [000000] -----------                         |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5)              [000023] -----O-----                         \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5)              [000022] -------N---                            \--*  ADD       byref  $240
N005 (  1,  1)              [000013] -----------                               +--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N011 (  4,  5)              [000021] -------N---                               \--*  ADD       long   $1c2
N009 (  3,  4)              [000019] -------N---                                  +--*  LSH       long   $1c1
N007 (  2,  3) CSE #02 (def)[000017] ---------U-                                  |  +--*  CAST      long <- uint $1c0
N006 (  1,  1)              [000014] -----------                                  |  |  \--*  LCL_VAR   int    V01 arg1         u:1 $80
N008 (  1,  1)              [000018] -------N---                                  |  \--*  CNS_INT   long   3 $200
N010 (  1,  1)              [000020] -----------                                  \--*  CNS_INT   long   16 $202

Aggressive CSE Promotion (300.000000 >= 200.000000)
cseRefCnt=300.000000, aggressiveRefCnt=200.000000, moderateRefCnt=100.000000
defCnt=100.000000, useCnt=100.000000, cost=11, size=16
def_cost=1, use_cost=1, extra_no_cost=30, extra_yes_cost=0
CSE cost savings check (1130.000000 >= 200.000000) passes

Promoting CSE:

lvaGrabTemp returning 4 (V04 rat0) (a long lifetime temp) called for CSE - aggressive.
CSE #03 is single-def, so associated CSE temp V04 will be in SSA
New refCnts for V04: refCnt =  2, refCntWtd = 2
New refCnts for V04: refCnt =  3, refCntWtd = 3

CSE #03 def at [000024] replaced in BB01 with def of V04
optValnumCSE morphed tree:
N019 ( 17, 21)              [000005] nA-XGO-----                         *  STOREIND  long   $145
N017 ( 12, 17)              [000039] -A-X-O-----                         +--*  COMMA     byref  $241
N015 ( 11, 16) CSE #03 (def)[000037] DA-X-O-----                         |  +--*  STORE_LCL_VAR byref  V04 cse0         d:1 $VN.Void
N014 ( 11, 16)              [000024] ---X-O-----                         |  |  \--*  COMMA     byref  $241
N004 (  8, 11)              [000016] ---X-O-----                         |  |     +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1)              [000001] -----------                         |  |     |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) CSE #01 (def)[000015] ---X-------                         |  |     |  \--*  ARR_LENGTH int    $180
N002 (  1,  1)              [000000] -----------                         |  |     |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5)              [000023] -----O-----                         |  |     \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5)              [000022] -------N---                         |  |        \--*  ADD       byref  $240
N005 (  1,  1)              [000013] -----------                         |  |           +--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N011 (  4,  5)              [000021] -------N---                         |  |           \--*  ADD       long   $1c2
N009 (  3,  4)              [000019] -------N---                         |  |              +--*  LSH       long   $1c1
N007 (  2,  3) CSE #02 (def)[000017] ---------U-                         |  |              |  +--*  CAST      long <- uint $1c0
N006 (  1,  1)              [000014] -----------                         |  |              |  |  \--*  LCL_VAR   int    V01 arg1         u:1 $80
N008 (  1,  1)              [000018] -------N---                         |  |              |  \--*  CNS_INT   long   3 $200
N010 (  1,  1)              [000020] -----------                         |  |              \--*  CNS_INT   long   16 $202
N016 (  1,  1)              [000038] -----------                         |  \--*  LCL_VAR   byref  V04 cse0         u:1 $241
N018 (  1,  1)              [000003] -----------                         \--*  CNS_INT   long   0 $201

Working on the replacement of the CSE #03 use at [000036] in BB01
Unmark CSE use #01 at [000027]:   1 ->   0
Unmark CSE use #02 at [000029]:   1 ->   0
optValnumCSE morphed tree:
N003 (  5,  4)              [000011] nA--GO-----                         *  STOREIND  long   $145
N001 (  1,  1)              [000040] -----------                         +--*  LCL_VAR   byref  V04 cse0         u:1 $2c0
N002 (  1,  1)              [000009] -----------                         \--*  CNS_INT   long   0 $201

Skipped CSE #01 because use count is 0
Skipped CSE #02 because use count is 0

*************** Finishing PHASE Optimize Valnum CSEs
Trees after Optimize Valnum CSEs

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x004 )
N019 ( 17, 21) [000005] nA-XGO-----                         *  STOREIND  long   $145
N017 ( 12, 17) [000039] -A-X-O-----                         +--*  COMMA     byref  $241
N015 ( 11, 16) [000037] DA-X-O-----                         |  +--*  STORE_LCL_VAR byref  V04 cse0         d:1 $VN.Void
N014 ( 11, 16) [000024] ---X-O-----                         |  |  \--*  COMMA     byref  $241
N004 (  8, 11) [000016] ---X-O-----                         |  |     +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1) [000001] -----------                         |  |     |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) [000015] ---X-------                         |  |     |  \--*  ARR_LENGTH int    $180
N002 (  1,  1) [000000] -----------                         |  |     |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5) [000023] -----O-----                         |  |     \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5) [000022] -------N---                         |  |        \--*  ADD       byref  $240
N005 (  1,  1) [000013] -----------                         |  |           +--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N011 (  4,  5) [000021] -------N---                         |  |           \--*  ADD       long   $1c2
N009 (  3,  4) [000019] -------N---                         |  |              +--*  LSH       long   $1c1
N007 (  2,  3) [000017] ---------U-                         |  |              |  +--*  CAST      long <- uint $1c0
N006 (  1,  1) [000014] -----------                         |  |              |  |  \--*  LCL_VAR   int    V01 arg1         u:1 $80
N008 (  1,  1) [000018] -------N---                         |  |              |  \--*  CNS_INT   long   3 $200
N010 (  1,  1) [000020] -----------                         |  |              \--*  CNS_INT   long   16 $202
N016 (  1,  1) [000038] -----------                         |  \--*  LCL_VAR   byref  V04 cse0         u:1 $241
N018 (  1,  1) [000003] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
N003 (  5,  4) [000011] nA--GO-----                         *  STOREIND  long   $145
N001 (  1,  1) [000040] -----------                         +--*  LCL_VAR   byref  V04 cse0         u:1 $2c0
N002 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0) [000012] -----------                         *  RETURN    void   $VN.Void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] NumUses overestimated for V01.1: IR 2 SSA 4
[info] HasGlobalUse overestimated for V01.1
[info] NumUses overestimated for V02.1: IR 2 SSA 4
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully
*************** In fgDebugCheckLoopTable
Disabling SSA checking before assertion prop

*************** Starting PHASE Assertion prop
GenTreeNode creates assertion:
N003 (  3,  3) [000015] ---X-------                         *  ARR_LENGTH int    $180
In BB01 New Global Constant Assertion: ($c0,$0) V02.01 != null, index = #01
GenTreeNode creates assertion:
N004 (  8, 11) [000016] ---X-O-----                         *  BOUNDS_CHECK_Rng void   $145
In BB01 New Global ArrBnds  Assertion: ($0,$0) [idx: {InitVal($40)};len: {ARR_LENGTH($c0)}] in range , index = #02
GenTreeNode creates assertion:
N019 ( 17, 21) [000005] nA-XGO-----                         *  STOREIND  long   $145
In BB01 New Global Constant Assertion: ($2c0,$0) Value_Number {PtrToArrElem($280, $c0, $1c0, $201)} is not 0, index = #03

BB01 valueGen = #01 #02 #03

BB01:
 in   = #NA
 out  = #01 #02 #03

Propagating #NA for BB01, stmt STMT00000, tree [000001], tree -> #NA
Propagating #NA for BB01, stmt STMT00000, tree [000000], tree -> #NA
Propagating #NA for BB01, stmt STMT00000, tree [000015], tree -> #01
Propagating #01 for BB01, stmt STMT00000, tree [000016], tree -> #02
Propagating #01 #02 for BB01, stmt STMT00000, tree [000013], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000014], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000017], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000018], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000019], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000020], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000021], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000022], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000023], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000024], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000037], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000038], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000039], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000003], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000005], tree -> #03
Propagating #01 #02 #03 for BB01, stmt STMT00001, tree [000040], tree -> #NA
Propagating #01 #02 #03 for BB01, stmt STMT00001, tree [000009], tree -> #NA
Propagating #01 #02 #03 for BB01, stmt STMT00001, tree [000011], tree -> #03
Propagating #01 #02 #03 for BB01, stmt STMT00002, tree [000012], tree -> #NA

*************** Finishing PHASE Assertion prop [no changes]

*************** Starting PHASE VN based intrinsic expansion

*************** Finishing PHASE VN based intrinsic expansion [no changes]

*************** Starting PHASE Optimize index checks
Looking for array size assertions for: $81
ArrSize for lengthVN:081 = 0
[RangeCheck::GetRange] BB01 N001 (  1,  1) [000001] -----------                         *  LCL_VAR   int    V01 arg1         u:1 $80
{
Merging assertions from pred edges of BB01 for op [000001] $80
   Computed Range [000001] => <Unknown, Unknown>
}

*************** Finishing PHASE Optimize index checks [no changes]

*************** Starting PHASE VN-based dead store removal

*************** Finishing PHASE VN-based dead store removal [no changes]

*************** Starting PHASE Stress gtSplitTree

*************** Finishing PHASE Stress gtSplitTree [no changes]

*************** Starting PHASE Expand runtime lookups

*************** Finishing PHASE Expand runtime lookups [no changes]

*************** Starting PHASE Expand static init
Nothing to expand.

*************** Finishing PHASE Expand static init [no changes]

*************** Starting PHASE Expand TLS access
Nothing to expand.

*************** Finishing PHASE Expand TLS access [no changes]

*************** Starting PHASE Insert GC Polls

*************** Finishing PHASE Insert GC Polls [no changes]

*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()

optimized 0 BBJ_COND cases, 0 BBJ_RETURN cases in 1 passes

*************** Finishing PHASE Optimize bools [no changes]

*************** Starting PHASE If conversion

*************** Finishing PHASE If conversion [no changes]

*************** Starting PHASE Optimize layout

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize layout
Trees after Optimize layout

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0) [000012] -----------                         *  RETURN    void   $VN.Void

*************** Starting PHASE Recognize Switch

*************** Finishing PHASE Recognize Switch [no changes]

*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method

*************** Finishing PHASE Determine first cold block [no changes]

*************** Starting PHASE Rationalize IR

*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}
               [000041] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   int    V01 arg1         u:1 $80
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
                                                            /--*  t0     ref    
N003 (  3,  3) [000015] ---X-------                   t15 = *  ARR_LENGTH int    $180
                                                            /--*  t1     int    
                                                            +--*  t15    int    
N004 (  8, 11) [000016] ---X-O-----                         *  BOUNDS_CHECK_Rng void   $145
N005 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 $c0
N006 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 $80
                                                            /--*  t14    int    
N007 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint $1c0
N008 (  1,  1) [000018] -------N---                   t18 =    CNS_INT   long   3 $200
                                                            /--*  t17    long   
                                                            +--*  t18    long   
N009 (  3,  4) [000019] -------N---                   t19 = *  LSH       long   $1c1
N010 (  1,  1) [000020] -----------                   t20 =    CNS_INT   long   16 $202
                                                            /--*  t19    long   
                                                            +--*  t20    long   
N011 (  4,  5) [000021] -------N---                   t21 = *  ADD       long   $1c2
                                                            /--*  t13    ref    
                                                            +--*  t21    long   
N012 (  3,  5) [000022] -------N---                   t22 = *  ADD       byref  $240
                                                            /--*  t22    byref  
N015 ( 11, 16) [000037] DA-X-O-----                         *  STORE_LCL_VAR byref  V04 cse0         d:1 $VN.Void
N016 (  1,  1) [000038] -----------                   t38 =    LCL_VAR   byref  V04 cse0         u:1 $241
N018 (  1,  1) [000003] -----------                    t3 =    CNS_INT   long   0 $201
                                                            /--*  t38    byref  
                                                            +--*  t3     long   
N019 ( 17, 21) [000005] nA-XGO-----                         *  STOREIND  long   $145
               [000042] -----------                            IL_OFFSET void   INLRT @ 0x005[E-]
N001 (  1,  1) [000040] -----------                   t40 =    LCL_VAR   byref  V04 cse0         u:1 $2c0
N002 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 $201
                                                            /--*  t40    byref  
                                                            +--*  t9     long   
N003 (  5,  4) [000011] nA--GO-----                         *  STOREIND  long   $145
               [000043] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-]
N001 (  0,  0) [000012] -----------                            RETURN    void   $VN.Void

*************** Starting PHASE Do 'simple' lowering
Lower ARR_LENGTH:
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
                                                            /--*  t0     ref    
N003 (  3,  3) [000015] ---X-------                   t15 = *  ARR_LENGTH int    $180
After Lower IND:
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
               [000044] -----------                   t44 =    CNS_INT   long   8
                                                            /--*  t0     ref    
                                                            +--*  t44    long   
               [000045] -----------                   t45 = *  ADD       byref 
                                                            /--*  t45    byref  
N003 (  3,  3) [000015] ---X-------                   t15 = *  IND       int   
*** Computing fgRngChkTarget for block BB01
fgNewBBinRegion(jumpKind=BBJ_THROW, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=true, insertAtEnd=true): inserting after BB01
New Basic Block BB02 [0001] created.

fgAddCodeRef - Add BB in non-EH region for RNGCHK_FAIL, new block BB02 [0001]
Initializing arg info for 46.CALL:
Args for call [000046] CALL after AddFinalArgsAndDetermineABIInfo:

Morphing args for 46.CALL:
Args for [000046].CALL after fgMorphArgs:
OutgoingArgsStackSize is 32

*************** Finishing PHASE Do 'simple' lowering
Trees after Do 'simple' lowering

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}
               [000041] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   int    V01 arg1         u:1 $80
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
               [000044] -----------                   t44 =    CNS_INT   long   8
                                                            /--*  t0     ref    
                                                            +--*  t44    long   
               [000045] -----------                   t45 = *  ADD       byref 
                                                            /--*  t45    byref  
N003 (  3,  3) [000015] ---X-------                   t15 = *  IND       int   
                                                            /--*  t1     int    
                                                            +--*  t15    int    
N004 (  8, 11) [000016] ---X-O-----                         *  BOUNDS_CHECK_Rng -> BB02 void   $145
N005 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 $c0
N006 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 $80
                                                            /--*  t14    int    
N007 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint $1c0
N008 (  1,  1) [000018] -------N---                   t18 =    CNS_INT   long   3 $200
                                                            /--*  t17    long   
                                                            +--*  t18    long   
N009 (  3,  4) [000019] -------N---                   t19 = *  LSH       long   $1c1
N010 (  1,  1) [000020] -----------                   t20 =    CNS_INT   long   16 $202
                                                            /--*  t19    long   
                                                            +--*  t20    long   
N011 (  4,  5) [000021] -------N---                   t21 = *  ADD       long   $1c2
                                                            /--*  t13    ref    
                                                            +--*  t21    long   
N012 (  3,  5) [000022] -------N---                   t22 = *  ADD       byref  $240
                                                            /--*  t22    byref  
N015 ( 11, 16) [000037] DA-X-O-----                         *  STORE_LCL_VAR byref  V04 cse0         d:1 $VN.Void
N016 (  1,  1) [000038] -----------                   t38 =    LCL_VAR   byref  V04 cse0         u:1 $241
N018 (  1,  1) [000003] -----------                    t3 =    CNS_INT   long   0 $201
                                                            /--*  t38    byref  
                                                            +--*  t3     long   
N019 ( 17, 21) [000005] nA-XGO-----                         *  STOREIND  long   $145
               [000042] -----------                            IL_OFFSET void   INLRT @ 0x005[E-]
N001 (  1,  1) [000040] -----------                   t40 =    LCL_VAR   byref  V04 cse0         u:1 $2c0
N002 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 $201
                                                            /--*  t40    byref  
                                                            +--*  t9     long   
N003 (  5,  4) [000011] nA--GO-----                         *  STOREIND  long   $145
               [000043] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-]
N001 (  0,  0) [000012] -----------                            RETURN    void   $VN.Void

------------ BB02 [???..???) (throw), preds={} succs={}
N001 ( 14,  5) [000046] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL

*************** Starting PHASE Lowering nodeinfo
Addressing mode:
  Base
    N002 (  1,  1) [000000] -----------                         *  LCL_VAR   ref    V02 arg2         u:1 $c0
  + 8
Removing unused node:
                 [000044] -c---------                         *  CNS_INT   long   8
New addressing mode node:
                 [000045] -----------                         *  LEA(b+8)  byref

Addressing mode:
  Base
    N005 (  1,  1) [000013] -----------                         *  LCL_VAR   ref    V02 arg2         u:1 $c0
  + Index * 8 + 16
    N007 (  2,  3) [000017] ---------U-                         *  CAST      long <- uint $1c0
Removing unused node:
  N011 (  4,  5) [000021] -------N---                         *  ADD       long   $1c2
Removing unused node:
  N010 (  1,  1) [000020] -c---------                         *  CNS_INT   long   16 $202
Removing unused node:
  N009 (  3,  4) [000019] -------N---                         *  LSH       long   $1c1
Removing unused node:
  N008 (  1,  1) [000018] -c-----N---                         *  CNS_INT   long   3 $200
New addressing mode node:
  N012 (  3,  5) [000022] -----------                         *  LEA(b+(i*8)+16) byref

lowering store lcl var/field (before):
N005 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 $c0
N006 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 $80
                                                            /--*  t14    int    
N007 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint $1c0
                                                            /--*  t13    ref    
                                                            +--*  t17    long   
N012 (  3,  5) [000022] -----------                   t22 = *  LEA(b+(i*8)+16) byref 
                                                            /--*  t22    byref  
N015 ( 11, 16) [000037] DA-X-O-----                         *  STORE_LCL_VAR byref  V04 cse0         d:1 $VN.Void

lowering store lcl var/field (after):
N005 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 $c0
N006 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 $80
                                                            /--*  t14    int    
N007 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint $1c0
                                                            /--*  t13    ref    
                                                            +--*  t17    long   
N012 (  3,  5) [000022] -----------                   t22 = *  LEA(b+(i*8)+16) byref 
                                                            /--*  t22    byref  
N015 ( 11, 16) [000037] DA-X-O-----                         *  STORE_LCL_VAR byref  V04 cse0         d:1 $VN.Void

Lower of StoreInd didn't mark the node as self contained for reason: oper is not supported
N016 (  1,  1) [000038] -----------                   t38 =    LCL_VAR   byref  V04 cse0         u:1 $241
N018 (  1,  1) [000003] -----------                    t3 =    CNS_INT   long   0 $201
                                                            /--*  t38    byref  
                                                            +--*  t3     long   
N019 ( 17, 21) [000005] nA-XGO-----                         *  STOREIND  long   $145
Lower of StoreInd didn't mark the node as self contained for reason: oper is not supported
N001 (  1,  1) [000040] -----------                   t40 =    LCL_VAR   byref  V04 cse0         u:1 $2c0
N002 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 $201
                                                            /--*  t40    byref  
                                                            +--*  t9     long   
N003 (  5,  4) [000011] nA--GO-----                         *  STOREIND  long   $145
lowering GT_RETURN
N001 (  0,  0) [000012] -----------                         *  RETURN    void   $VN.Void
============lowering call (before):
N001 ( 14,  5) [000046] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL

args:
======

late:
======
Bumping outgoing arg space size from 0 to 32 for [000046]
lowering call (after):
N001 ( 14,  5) [000046] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL

Lower has completed modifying nodes.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB02 [???..???) (throw), preds={} succs={}
N001 ( 14,  5) [000046] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL

-------------------------------------------------------------------------------------------------------------------

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V01: refCnt =  1, refCntWtd = 1
New refCnts for V02: refCnt =  1, refCntWtd = 1
New refCnts for V02: refCnt =  2, refCntWtd = 2
New refCnts for V01: refCnt =  2, refCntWtd = 2
New refCnts for V04: refCnt =  1, refCntWtd = 1
New refCnts for V04: refCnt =  2, refCntWtd = 2

*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V01: refCnt =  3, refCntWtd = 3
New refCnts for V01: refCnt =  4, refCntWtd = 4
New refCnts for V02: refCnt =  3, refCntWtd = 3
New refCnts for V02: refCnt =  4, refCntWtd = 4
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
;  V00 this              ref  this class-hnd single-def <Program>
;  V01 arg1              int  single-def
;  V02 arg2              ref  class-hnd single-def <long[]>
;  V03 OutArgs        struct <32> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V04 cse0            byref  "CSE - aggressive"
In fgLocalVarLivenessInit

Local V03 should not be enregistered because: struct size does not match reg size
Tracked variable (3 out of 5) table:
V02 arg2          [   ref]: refCnt =    4, refCntWtd =   4   
V01 arg1          [   int]: refCnt =    4, refCntWtd =   4   
V04 cse0          [ byref]: refCnt =    2, refCntWtd =   2

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V02 V01    } + ByrefExposed + GcHeap
     DEF(1)={        V04} + ByrefExposed + GcHeap

BB02 USE(0)={}
     DEF(0)={}

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (2)={V02 V01} + ByrefExposed + GcHeap
     OUT(0)={       }

BB02 IN (0)={}
     OUT(0)={}

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgRemoveDeadBlocks()
New BlockSet epoch 2, # of blocks (including unused BB00): 3, bitset array size: 1 (short)

Removing unreachable blocks for fgRemoveDeadBlocks iteration #1
*************** In fgDebugCheckBBlist

*** lvaComputeRefCounts ***

*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB02 [???..???) (throw), preds={} succs={}
N001 ( 14,  5) [000046] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL

*************** Starting PHASE Calculate stack level slots

*************** Finishing PHASE Calculate stack level slots [no changes]

*************** Starting PHASE Linear scan register alloc
Clearing modified regs.

buildIntervals ========

-----------------
LIVENESS:
-----------------
BB01
use: {V01 V02}
def: {V04}
 in: {V01 V02}
out: {}
BB02
use: {}
def: {}
 in: {}
out: {}
Interval  0: int RefPositions {} physReg:NA Preferences=[allInt]
  Interval  0: (V01) int RefPositions {} physReg:NA Preferences=[allInt]
Interval  1: ref RefPositions {} physReg:NA Preferences=[allInt]
  Interval  1: (V02) ref RefPositions {} physReg:NA Preferences=[allInt]
Interval  2: byref RefPositions {} physReg:NA Preferences=[allInt]
  Interval  2: (V04) byref RefPositions {} physReg:NA Preferences=[allInt]

FP callee save candidate vars: None

floatVarCount = 0; hasLoops = false, singleExit = true
TUPLE STYLE DUMP BEFORE LSRA
Start LSRA Block Sequence: 
Current block: BB01
	Unvisited block: BB02, Criteria: weight, Worklist: [BB02 ]
Current block: BB02
Final LSRA Block Sequence:
BB01 (  1   )
BB02 (  0   )

BB01 [000..00B) (return), preds={} succs={}
=====
  N000.                    IL_OFFSET INLRT @ 0x000[E-]
  N001.                    V01(t1)
  N002.                    V02(t0)
  N000. t45             =  LEA(b+8) ; t0
  N003. t15             =  IND      ; t45
  N004.                    BOUNDS_CHECK_Rng -> BB02; t1,t15
  N005.                    V02(t13*)
  N006.                    V01(t14*)
  N007. t17             =  CAST     ; t14*
  N012. t22             =  LEA(b+(i*8)+16); t13*,t17
  N015.                    V04(t37); t22
  N000.                    IL_OFFSET INLRT @ 0x005[E-]
  N001.                    V04(t40*)
  N002. t9              =  CNS_INT   0
  N003.                    STOREIND ; t40*,t9
  N000.                    IL_OFFSET INLRT @ 0x00A[E-]
  N001.                    RETURN

BB02 [???..???) (throw), preds={} succs={}
=====
  N001.                    CALL help

buildIntervals second part ========
Int arg V02 in reg r8
<RefPosition #0   @0   RefTypeParamDef <Ivl:1 V02> BB00 regmask=[r8] minReg=1 fixed wt=100.00>
Int arg V01 in reg rdx
<RefPosition #1   @0   RefTypeParamDef <Ivl:0 V01> BB00 regmask=[rdx] minReg=1 fixed wt=100.00>
Int arg V00 in reg rcx

NEW BLOCK BB01
<RefPosition #2   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N003 (???,???) [000041] -----------                         *  IL_OFFSET void   INLRT @ 0x000[E-] REG NA

DefList: {  }
N005 (  1,  1) [000001] -----------                         *  LCL_VAR   int    V01 arg1         u:1 NA REG NA $80

DefList: {  }
N007 (  1,  1) [000000] -----------                         *  LCL_VAR   ref    V02 arg2         u:1 NA REG NA $c0

DefList: {  }
N009 (???,???) [000045] -c---------                         *  LEA(b+8)  byref  REG NA
Contained
DefList: {  }
N011 (  3,  3) [000015] -c-X-------                         *  IND       int    REG NA
Contained
DefList: {  }
N013 (  8, 11) [000016] ---X-O-----                         *  BOUNDS_CHECK_Rng -> BB02 void   REG NA $145
<RefPosition #3   @13  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
<RefPosition #4   @13  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>

DefList: {  }
N015 (  1,  1) [000013] -----------                         *  LCL_VAR   ref    V02 arg2         u:1 NA (last use) REG NA $c0

DefList: {  }
N017 (  1,  1) [000014] -----------                         *  LCL_VAR   int    V01 arg1         u:1 NA (last use) REG NA $80

DefList: {  }
N019 (  2,  3) [000017] ---------U-                         *  CAST      long <- uint REG NA $1c0
<RefPosition #5   @19  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
Interval  3: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #6   @20  RefTypeDef <Ivl:3> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N019.t17. CAST }
N021 (  3,  5) [000022] -----------                         *  LEA(b+(i*8)+16) byref  REG NA
<RefPosition #7   @21  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
<RefPosition #8   @21  RefTypeUse <Ivl:3> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval  4: byref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #9   @22  RefTypeDef <Ivl:4> LEA BB01 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N021.t22. LEA }
N023 ( 11, 16) [000037] DA-X-O-----                         *  STORE_LCL_VAR byref  V04 cse0         d:1 NA REG NA $VN.Void
<RefPosition #10  @23  RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V04/L2> to <I4>
<RefPosition #11  @24  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=200.00>

DefList: {  }
N025 (???,???) [000042] -----------                         *  IL_OFFSET void   INLRT @ 0x005[E-] REG NA

DefList: {  }
N027 (  1,  1) [000040] -----------                         *  LCL_VAR   byref  V04 cse0         u:1 NA (last use) REG NA $2c0

DefList: {  }
N029 (  1,  1) [000009] -----------                         *  CNS_INT   long   0 REG NA $201
Interval  5: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #12  @30  RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N029.t9. CNS_INT }
N031 (  5,  4) [000011] nA--GO-----                         *  STOREIND  long   REG NA $145
<RefPosition #13  @31  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=200.00>
<RefPosition #14  @31  RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>

DefList: {  }
N033 (???,???) [000043] -----------                         *  IL_OFFSET void   INLRT @ 0x00A[E-] REG NA

DefList: {  }
N035 (  0,  0) [000012] -----------                         *  RETURN    void   REG NA $VN.Void

CHECKING LAST USES for BB01, liveout={}
==============================
use: {V01 V02}
def: {V04}

NEW BLOCK BB02

No predecessor;  - throw block; <RefPosition #15  @37  RefTypeBB BB02 regmask=[] minReg=1 wt=0.00>

firstColdLoc = 39
DefList: {  }
N039 ( 14,  5) [000046] --CXG------                         *  CALL help void   CORINFO_HELP_RNGCHKFAIL REG NA
<RefPosition #16  @40  RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 wt=0.00>
<RefPosition #17  @40  RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #18  @40  RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #19  @40  RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 wt=0.00>
<RefPosition #20  @40  RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 wt=0.00>
<RefPosition #21  @40  RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 wt=0.00>
<RefPosition #22  @40  RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 wt=0.00>

CHECKING LAST USES for BB02, liveout={}
==============================
use: {}
def: {}

Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval  0: (V01) int RefPositions {#1@0 #3@13 #5@19} physReg:rdx Preferences=[rdx]
Interval  1: (V02) ref RefPositions {#0@0 #4@13 #7@21} physReg:r8 Preferences=[r8]
Interval  2: (V04) byref RefPositions {#11@24 #13@31} physReg:NA Preferences=[allInt]
Interval  3: long RefPositions {#6@20 #8@21} physReg:NA Preferences=[allInt]
Interval  4: byref RefPositions {#9@22 #10@23} physReg:NA Preferences=[allInt] RelatedInterval <V04/L2>
Interval  5: long (constant) RefPositions {#12@30 #14@31} physReg:NA Preferences=[allInt]

------------
REFPOSITIONS BEFORE VALIDATING INTERVALS: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:1 V02> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @0   RefTypeParamDef <Ivl:0 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3   @13  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #4   @13  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #5   @19  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=400.00>
<RefPosition #6   @20  RefTypeDef <Ivl:3> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #7   @21  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
<RefPosition #8   @21  RefTypeUse <Ivl:3> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #9   @22  RefTypeDef <Ivl:4> LEA BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #10  @23  RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #11  @24  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=200.00>
<RefPosition #12  @30  RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #13  @31  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=200.00>
<RefPosition #14  @31  RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #15  @37  RefTypeBB BB02 regmask=[] minReg=1 wt=0.00>
<RefPosition #16  @40  RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last wt=0.00>
<RefPosition #17  @40  RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last wt=0.00>
<RefPosition #18  @40  RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last wt=0.00>
<RefPosition #19  @40  RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last wt=0.00>
<RefPosition #20  @40  RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last wt=0.00>
<RefPosition #21  @40  RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last wt=0.00>
<RefPosition #22  @40  RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last wt=0.00>

------------
REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval)
------------

-----------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:1 V02> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00>
<RefPosition #4   @13  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #7   @21  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
-----------------
<RefPosition #1   @0   RefTypeParamDef <Ivl:0 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3   @13  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #5   @19  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=400.00>
-----------------
<RefPosition #11  @24  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=200.00>
<RefPosition #13  @31  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=200.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:  V02 V01
BB01 [000..00B) (return), preds={} succs={}
=====
  N003.                    IL_OFFSET INLRT @ 0x000[E-]
  N005.                    V01(L0)
  N007.                    V02(L1)
  N009.                    LEA(b+8) 
  N011.                    IND      
  N013.                    BOUNDS_CHECK_Rng -> BB02
                               Use:<V01/L0>(#3)
                               Use:<V02/L1>(#4)
  N015.                    V02(L1)
  N017.                    V01(L0)
  N019.                    CAST     
                               Use:<V01/L0>(#5) *
        Def:<I3>(#6)
  N021.                    LEA(b+(i*8)+16)
                               Use:<V02/L1>(#7) *
                               Use:<I3>(#8) *
        Def:<I4>(#9) Pref:<V04/L2>
  N023.                    V04(L2)
                               Use:<I4>(#10) *
        Def:<V04/L2>(#11)
  N025.                    IL_OFFSET INLRT @ 0x005[E-]
  N027.                    V04(L2)
  N029.                    CNS_INT   0
        Def:<I5>(#12)
  N031.                    STOREIND 
                               Use:<V04/L2>(#13) *
                               Use:<I5>(#14) *
  N033.                    IL_OFFSET INLRT @ 0x00A[E-]
  N035.                    RETURN

BB02 [???..???) (throw), preds={} succs={}
=====
  N039.                    CALL help
        Kill: rax rcx rdx r8 r9 r10 r11

Linear scan intervals after buildIntervals:
Interval  0: (V01) int RefPositions {#1@0 #3@13 #5@19} physReg:rdx Preferences=[rdx]
Interval  1: (V02) ref RefPositions {#0@0 #4@13 #7@21} physReg:r8 Preferences=[r8]
Interval  2: (V04) byref RefPositions {#11@24 #13@31} physReg:NA Preferences=[allInt]
Interval  3: long RefPositions {#6@20 #8@21} physReg:NA Preferences=[allInt]
Interval  4: byref RefPositions {#9@22 #10@23} physReg:NA Preferences=[allInt] RelatedInterval <V04/L2>
Interval  5: long (constant) RefPositions {#12@30 #14@31} physReg:NA Preferences=[allInt]

*************** In LinearScan::allocateRegisters()

Linear scan intervals before allocateRegisters:
Interval  0: (V01) int RefPositions {#1@0 #3@13 #5@19} physReg:rdx Preferences=[rdx]
Interval  1: (V02) ref RefPositions {#0@0 #4@13 #7@21} physReg:r8 Preferences=[r8]
Interval  2: (V04) byref RefPositions {#11@24 #13@31} physReg:NA Preferences=[allInt]
Interval  3: long RefPositions {#6@20 #8@21} physReg:NA Preferences=[allInt]
Interval  4: byref RefPositions {#9@22 #10@23} physReg:NA Preferences=[allInt] RelatedInterval <V04/L2>
Interval  5: long (constant) RefPositions {#12@30 #14@31} physReg:NA Preferences=[allInt]

------------
REFPOSITIONS BEFORE ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:1 V02> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @0   RefTypeParamDef <Ivl:0 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3   @13  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #4   @13  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #5   @19  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=400.00>
<RefPosition #6   @20  RefTypeDef <Ivl:3> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #7   @21  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
<RefPosition #8   @21  RefTypeUse <Ivl:3> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #9   @22  RefTypeDef <Ivl:4> LEA BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #10  @23  RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #11  @24  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=200.00>
<RefPosition #12  @30  RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #13  @31  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=200.00>
<RefPosition #14  @31  RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #15  @37  RefTypeBB BB02 regmask=[] minReg=1 wt=0.00>
<RefPosition #16  @40  RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last wt=0.00>
<RefPosition #17  @40  RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last wt=0.00>
<RefPosition #18  @40  RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last wt=0.00>
<RefPosition #19  @40  RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last wt=0.00>
<RefPosition #20  @40  RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last wt=0.00>
<RefPosition #21  @40  RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last wt=0.00>
<RefPosition #22  @40  RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last wt=0.00>

Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.

------------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------------------+----+----+----+----+----+----+----+----+----+
                                          |    |    |V01a|    |    |    |    |V02a|    |
          0.#0  V02  Parm   Keep     r8   |    |    |V01a|    |    |    |    |V02a|    |
          0.#1  V01  Parm   Keep     rdx  |    |    |V01a|    |    |    |    |V02a|    |
          1.#2  BB1 PredBB0               |    |    |V01a|    |    |    |    |V02a|    |
[000016] 13.#3  V01  Use    Keep     rdx  |    |    |V01a|    |    |    |    |V02a|    |
         13.#4  V02  Use    Keep     r8   |    |    |V01a|    |    |    |    |V02a|    |
[000017] 19.#5  V01  Use *  Keep     rdx  |    |    |V01a|    |    |    |    |V02a|    |
         20.#6  I3   Def    ORDER(A) rax  |I3 a|    |    |    |    |    |    |V02a|    |
[000022] 21.#7  V02  Use *  Keep     r8   |I3 a|    |    |    |    |    |    |V02a|    |
         21.#8  I3   Use *  Keep     rax  |I3 a|    |    |    |    |    |    |V02a|    |
         22.#9  I4   Def    ORDER(A) rax  |I4 a|    |    |    |    |    |    |    |    |
[000037] 23.#10 I4   Use *  Keep     rax  |I4 a|    |    |    |    |    |    |    |    |
         24.#11 V04  Def    COVRS(A) rax  |V04a|    |    |    |    |    |    |    |    |
[000009] 30.#12 C5   Def    ORDER(A) rcx  |V04a|C5 a|    |    |    |    |    |    |    |
[000011] 31.#13 V04  Use *  Keep     rax  |V04a|C5 a|    |    |    |    |    |    |    |
         31.#14 C5   Use *  Keep     rcx  |V04a|C5 a|    |    |    |    |    |    |    |
------------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------------------+----+----+----+----+----+----+----+----+----+
         37.#15 BB2 PredBB0               |    |    |    |    |    |    |    |    |    |
[000046] 40.#16 rax  Kill   Keep     rax  |    |    |    |    |    |    |    |    |    |
         40.#17 rcx  Kill   Keep     rcx  |    |    |    |    |    |    |    |    |    |
         40.#18 rdx  Kill   Keep     rdx  |    |    |    |    |    |    |    |    |    |
         40.#19 r8   Kill   Keep     r8   |    |    |    |    |    |    |    |    |    |
         40.#20 r9   Kill   Keep     r9   |    |    |    |    |    |    |    |    |    |
         40.#21 r10  Kill   Keep     r10  |    |    |    |    |    |    |    |    |    |
         40.#22 r11  Kill   Keep     r11  |    |    |    |    |    |    |    |    |    |

------------
REFPOSITIONS AFTER ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:1 V02> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @0   RefTypeParamDef <Ivl:0 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3   @13  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #4   @13  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[r8] minReg=1 wt=400.00>
<RefPosition #5   @19  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 last regOptional wt=400.00>
<RefPosition #6   @20  RefTypeDef <Ivl:3> CAST BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #7   @21  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[r8] minReg=1 last wt=400.00>
<RefPosition #8   @21  RefTypeUse <Ivl:3> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #9   @22  RefTypeDef <Ivl:4> LEA BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #10  @23  RefTypeUse <Ivl:4> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #11  @24  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 wt=200.00>
<RefPosition #12  @30  RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #13  @31  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[rax] minReg=1 last wt=200.00>
<RefPosition #14  @31  RefTypeUse <Ivl:5> BB01 regmask=[rcx] minReg=1 last wt=100.00>
<RefPosition #15  @37  RefTypeBB BB02 regmask=[] minReg=1 wt=0.00>
<RefPosition #16  @40  RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last wt=0.00>
<RefPosition #17  @40  RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last wt=0.00>
<RefPosition #18  @40  RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last wt=0.00>
<RefPosition #19  @40  RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last wt=0.00>
<RefPosition #20  @40  RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last wt=0.00>
<RefPosition #21  @40  RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last wt=0.00>
<RefPosition #22  @40  RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last wt=0.00>

Active intervals at end of allocation:

-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V01 V02}
Has No Critical Edges

Prior to Resolution

BB01
use: {V01 V02}
def: {V04}
 in: {V01 V02}
out: {}
Var=Reg beg of BB01: V02=r8 V01=rdx 
Var=Reg end of BB01: none

BB02
use: {}
def: {}
 in: {}
out: {}
Var=Reg beg of BB02: none
Var=Reg end of BB02: none

RESOLVING EDGES
  Set V01 argument initial register to rdx
  Set V02 argument initial register to r8
Trees after linear scan register allocator (LSRA)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}
N003 (???,???) [000041] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
N005 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   int    V01 arg1         u:1 rdx REG rdx $80
N007 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 r8 REG r8 $c0
                                                            /--*  t0     ref    
N009 (???,???) [000045] -c---------                   t45 = *  LEA(b+8)  byref  REG NA
                                                            /--*  t45    byref  
N011 (  3,  3) [000015] -c-X-------                   t15 = *  IND       int    REG NA
                                                            /--*  t1     int    
                                                            +--*  t15    int    
N013 (  8, 11) [000016] ---X-O-----                         *  BOUNDS_CHECK_Rng -> BB02 void   REG NA $145
N015 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 r8 (last use) REG r8 $c0
N017 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 rdx (last use) REG rdx $80
                                                            /--*  t14    int    
N019 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint REG rax $1c0
                                                            /--*  t13    ref    
                                                            +--*  t17    long   
N021 (  3,  5) [000022] -----------                   t22 = *  LEA(b+(i*8)+16) byref  REG rax
                                                            /--*  t22    byref  
N023 ( 11, 16) [000037] DA-X-O-----                         *  STORE_LCL_VAR byref  V04 cse0         d:1 rax REG rax $VN.Void
N025 (???,???) [000042] -----------                            IL_OFFSET void   INLRT @ 0x005[E-] REG NA
N027 (  1,  1) [000040] -----------                   t40 =    LCL_VAR   byref  V04 cse0         u:1 rax (last use) REG rax $2c0
N029 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 REG rcx $201
                                                            /--*  t40    byref  
                                                            +--*  t9     long   
N031 (  5,  4) [000011] nA--GO-----                         *  STOREIND  long   REG NA $145
N033 (???,???) [000043] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-] REG NA
N035 (  0,  0) [000012] -----------                            RETURN    void   REG NA $VN.Void

------------ BB02 [???..???) (throw), preds={} succs={}
N039 ( 14,  5) [000046] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL REG NA

-------------------------------------------------------------------------------------------------------------------

Final allocation
------------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------------------+----+----+----+----+----+----+----+----+----+
          0.#0  V02  Parm   Alloc    r8   |    |    |    |    |    |    |    |V02a|    |
          0.#1  V01  Parm   Alloc    rdx  |    |    |V01a|    |    |    |    |V02a|    |
          1.#2  BB1 PredBB0               |    |    |V01a|    |    |    |    |V02a|    |
[000016] 13.#3  V01  Use    Keep     rdx  |    |    |V01a|    |    |    |    |V02a|    |
         13.#4  V02  Use    Keep     r8   |    |    |V01a|    |    |    |    |V02a|    |
[000017] 19.#5  V01  Use *  Keep     rdx  |    |    |V01i|    |    |    |    |V02a|    |
         20.#6  I3   Def    Alloc    rax  |I3 a|    |    |    |    |    |    |V02a|    |
[000022] 21.#7  V02  Use *  Keep     r8   |I3 a|    |    |    |    |    |    |V02i|    |
         21.#8  I3   Use *  Keep     rax  |I3 i|    |    |    |    |    |    |    |    |
         22.#9  I4   Def    Alloc    rax  |I4 a|    |    |    |    |    |    |    |    |
[000037] 23.#10 I4   Use *  Keep     rax  |I4 i|    |    |    |    |    |    |    |    |
         24.#11 V04  Def    Alloc    rax  |V04a|    |    |    |    |    |    |    |    |
[000009] 30.#12 C5   Def    Alloc    rcx  |V04a|C5 a|    |    |    |    |    |    |    |
[000011] 31.#13 V04  Use *  Keep     rax  |V04i|C5 a|    |    |    |    |    |    |    |
         31.#14 C5   Use *  Keep     rcx  |    |C5 i|    |    |    |    |    |    |    |
------------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------------------+----+----+----+----+----+----+----+----+----+
         37.#15 BB2 PredBB0               |    |    |    |    |    |    |    |    |    |
[000046] 40.#16 rax  Kill   Keep     rax  |    |    |    |    |    |    |    |    |    |
         40.#17 rcx  Kill   Keep     rcx  |    |    |    |    |    |    |    |    |    |
         40.#18 rdx  Kill   Keep     rdx  |    |    |    |    |    |    |    |    |    |
         40.#19 r8   Kill   Keep     r8   |    |    |    |    |    |    |    |    |    |
         40.#20 r9   Kill   Keep     r9   |    |    |    |    |    |    |    |    |    |
         40.#21 r10  Kill   Keep     r10  |    |    |    |    |    |    |    |    |    |
         40.#22 r11  Kill   Keep     r11  |    |    |    |    |    |    |    |    |    |

Recording the maximum number of concurrent spills:

----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars:  3
Total Reg Cand Vars: 3
Total number of Intervals: 5
Total number of RefPositions: 22
Total Number of spill temps created: 0
..........
BB01 [  100.00]: COVERS = 1, REG_ORDER = 3
..........
Total SpillCount : 0   Weighted: 0.000000
Total CopyReg : 0   Weighted: 0.000000
Total ResolutionMovs : 0   Weighted: 0.000000
Total SplitEdges : 0   Weighted: 0.000000
..........
Total COVERS [# 4] : 1   Weighted: 100.000000
Total REG_ORDER [#13] : 3   Weighted: 300.000000

TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:  V02(r8) V01(rdx)
BB01 [000..00B) (return), preds={} succs={}
=====
  N003.                    IL_OFFSET INLRT @ 0x000[E-]
  N005.                    V01(rdx)
  N007.                    V02(r8)
  N009. STK             =  LEA(b+8) ; r8
  N011. STK             =  IND      ; STK
  N013.                    BOUNDS_CHECK_Rng -> BB02; rdx,STK
  N015.                    V02(r8*)
  N017.                    V01(rdx*)
  N019. rax             =  CAST     ; rdx*
  N021. rax             =  LEA(b+(i*8)+16); r8*,rax
* N023.                    V04(rax); rax
  N025.                    IL_OFFSET INLRT @ 0x005[E-]
  N027.                    V04(rax*)
  N029. rcx             =  CNS_INT   0
  N031.                    STOREIND ; rax*,rcx
  N033.                    IL_OFFSET INLRT @ 0x00A[E-]
  N035.                    RETURN   
Var=Reg end of BB01: none

BB02 [???..???) (throw), preds={} succs={}
=====
Predecessor for variable locations: BB00
Var=Reg beg of BB02: none
  N039.                    CALL help
Var=Reg end of BB02: none

*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB02 [???..???) (throw), preds={} succs={}
N039 ( 14,  5) [000046] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL REG NA

*************** Starting PHASE Place 'align' instructions

*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
  V02(r8)  V01(rdx)
Modified regs: [rax rcx rdx r8-r11]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V03 OutArgs, size=32, stkOffs=-0x28
--- delta bump 8 for RA
--- delta bump 40 for RSP frame
--- virtual stack offset to actual stack offset delta is 48
-- V00 was 0, now 48
-- V01 was 8, now 56
-- V02 was 16, now 64
-- V03 was -40, now 8
; Final local variable assignments
;
;* V00 this         [V00    ] (  0,  0   )     ref  ->  zero-ref    this class-hnd single-def <Program>
;  V01 arg1         [V01,T01] (  4,  4   )     int  ->  rdx         single-def
;  V02 arg2         [V02,T00] (  4,  4   )     ref  ->   r8         class-hnd single-def <long[]>
;  V03 OutArgs      [V03    ] (  1,  1   )  struct (32) [rsp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V04 cse0         [V04,T02] (  2,  2   )   byref  ->  rax         "CSE - aggressive"
;
; Lcl frame size = 40
Created:
      G_M62796_IG02:        ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
  BB01 : first block
  BB02 : throw helper block
*************** After genMarkLabelsForCodegen()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i label idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare label LIR 
-----------------------------------------------------------------------------------------------------------------------------------------
Setting stack level from -572662307 to 0

=============== Generating BB01 [000..00B) (return), preds={} succs={} flags=0x00000000.00420011: i label idxlen LIR 
BB01 IN (2)={V02 V01} + ByrefExposed + GcHeap
     OUT(0)={       }

Recording Var Locations at start of BB01
  V02(r8)  V01(rdx)
Change life 0000000000000000 {} -> 0000000000000003 {V01 V02}
							V02 in reg r8 is becoming live  [------]
							Live regs: 0000000000000000 {} + {r8} => 0000000000000100 {r8}
Debug: New V02 debug range: first
							V01 in reg rdx is becoming live  [------]
							Live regs: 0000000000000100 {r8} + {rdx} => 0000000000000104 {rdx r8}
Debug: New V01 debug range: first
							Live regs: (unchanged) 0000000000000104 {rdx r8}
							GC regs: (unchanged) 0100 {r8}
							Byref regs: (unchanged) 0000 {}

L_M62796_BB01:
Label: G_M62796_IG02, GCvars=0000000000000000 {}, gcrefRegs=0100 {r8}, byrefRegs=0000 {}

Scope info: begin block BB01, IL range [000..00B)
Added IP mapping: 0x0000 STACK_EMPTY (G_M62796_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000041] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
Generating: N005 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   int    V01 arg1         u:1 rdx REG rdx $80
Generating: N007 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 r8 REG r8 $c0
                                                                        /--*  t0     ref    
Generating: N009 (???,???) [000045] -c---------                   t45 = *  LEA(b+8)  byref  REG NA
                                                                        /--*  t45    byref  
Generating: N011 (  3,  3) [000015] -c-X-------                   t15 = *  IND       int    REG NA
                                                                        /--*  t1     int    
                                                                        +--*  t15    int    
Generating: N013 (  8, 11) [000016] ---X-O-----                         *  BOUNDS_CHECK_Rng -> BB02 void   REG NA $145
Mapped BB01 to G_M62796_IG02
IN0001:        cmp      edx, dword ptr [r8+0x08]
IN0002:        jae      L_M62796_BB02
Generating: N015 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 r8 (last use) REG r8 $c0
Generating: N017 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 rdx (last use) REG rdx $80
                                                                        /--*  t14    int    
Generating: N019 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint REG rax $1c0
							V01 in reg rdx is becoming dead  [000014]
							Live regs: 0000000000000104 {rdx r8} - {rdx} => 0000000000000100 {r8}
Debug: Closing V01 debug range.
							Live vars after [000014]: {V01 V02} -{V01} => {V02}
IN0003:        mov      eax, edx
                                                                        /--*  t13    ref    
                                                                        +--*  t17    long   
Generating: N021 (  3,  5) [000022] -----------                   t22 = *  LEA(b+(i*8)+16) byref  REG rax
							V02 in reg r8 is becoming dead  [000013]
							Live regs: 0000000000000100 {r8} - {r8} => 0000000000000000 {}
Debug: Closing V02 debug range.
							Live vars after [000013]: {V02} -{V02} => {}
							GC regs: 0100 {r8} => 0000 {}
IN0004:        lea      rax, bword ptr [r8+8*rax+0x10]
							Byref regs: 0000 {} => 0001 {rax}
                                                                        /--*  t22    byref  
Generating: N023 ( 11, 16) [000037] DA-X-O-----                         *  STORE_LCL_VAR byref  V04 cse0         d:1 rax REG rax $VN.Void
							Byref regs: 0001 {rax} => 0000 {}
							V04 in reg rax is becoming live  [000037]
							Live regs: 0000000000000000 {} + {rax} => 0000000000000001 {rax}
							Live vars after [000037]: {} +{V04} => {V04}
							Byref regs: 0000 {} => 0001 {rax}
Added IP mapping: 0x0005 STACK_EMPTY (G_M62796_IG02,ins#4,ofs#17)
Generating: N025 (???,???) [000042] -----------                            IL_OFFSET void   INLRT @ 0x005[E-] REG NA
Generating: N027 (  1,  1) [000040] -----------                   t40 =    LCL_VAR   byref  V04 cse0         u:1 rax (last use) REG rax $2c0
Generating: N029 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 REG rcx $201
IN0005:        xor      rcx, rcx
                                                                        /--*  t40    byref  
                                                                        +--*  t9     long   
Generating: N031 (  5,  4) [000011] nA--GO-----                         *  STOREIND  long   REG NA $145
							V04 in reg rax is becoming dead  [000040]
							Live regs: 0000000000000001 {rax} - {rax} => 0000000000000000 {}
							Live vars after [000040]: {V04} -{V04} => {}
							Byref regs: 0001 {rax} => 0000 {}
IN0006:        mov      qword ptr [rax], rcx
Added IP mapping: 0x000A STACK_EMPTY (G_M62796_IG02,ins#6,ofs#22)
Generating: N033 (???,???) [000043] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-] REG NA
Generating: N035 (  0,  0) [000012] -----------                            RETURN    void   REG NA $VN.Void
Added IP mapping: EPILOG (G_M62796_IG02,ins#6,ofs#22) label
Reserving epilog IG for block BB01
Saved:
      G_M62796_IG02:        ; offs=0x000000, size=0x0016, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
Created:
      G_M62796_IG03:        ; offs=0x000016, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Created:
      G_M62796_IG04:        ; offs=0x000116, size=0x0000, bbWeight=1, gcrefRegs=0000 {}, epilog
*************** After placeholder IG creation
G_M62796_IG01:        ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M62796_IG02:        ; offs=0x000000, size=0x0016, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
G_M62796_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0100 {r8}, InitByrefRegs=0000 {}
G_M62796_IG04:        ; offs=0x000116, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Current IG

Variable Live Range History Dump for BB01
V01 arg1: rdx [(G_M62796_IG02,ins#0,ofs#0), (G_M62796_IG02,ins#2,ofs#10)]
V02 arg2: r8 [(G_M62796_IG02,ins#0,ofs#0), (G_M62796_IG02,ins#3,ofs#12)]

=============== Generating BB02 [???..???) (throw), preds={} succs={} flags=0x00000000.00022039: keep i internal rare label LIR 
BB02 IN (0)={}
     OUT(0)={}

Recording Var Locations at start of BB02
  <none>

Liveness not changing: 0000000000000000 {}
							Live regs: (unchanged) 0000000000000000 {}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 0000 {}

L_M62796_BB02:
Label: G_M62796_IG04, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}

Scope info: begin block BB02, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP (G_M62796_IG04,ins#0,ofs#0) label
Generating: N039 ( 14,  5) [000046] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL REG NA
							Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Mapped BB02 to G_M62796_IG04
IN0007:        call     CORINFO_HELP_RNGCHKFAIL
Scope info: ignoring block end
IN0008:        int3

Variable Live Range History Dump for BB02
..None..
Liveness not changing: 0000000000000000 {}

# compCycleEstimate =     22, compSizeEstimate =    25 Program:Test(int,long[]):this
; Final local variable assignments
;
;* V00 this         [V00    ] (  0,  0   )     ref  ->  zero-ref    this class-hnd single-def <Program>
;  V01 arg1         [V01,T01] (  4,  4   )     int  ->  rdx         single-def
;  V02 arg2         [V02,T00] (  4,  4   )     ref  ->   r8         class-hnd single-def <long[]>
;  V03 OutArgs      [V03    ] (  1,  1   )  struct (32) [rsp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V04 cse0         [V04,T02] (  2,  2   )   byref  ->  rax         "CSE - aggressive"
;
; Lcl frame size = 40
*************** Before prolog / epilog generation
G_M62796_IG01:        ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M62796_IG02:        ; offs=0x000000, size=0x0016, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
G_M62796_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0100 {r8}, InitByrefRegs=0000 {}
G_M62796_IG04:        ; offs=0x000116, size=0x0000, bbWeight=0, gcrefRegs=0000 {}, BB02 [0001] <-- Current IG
Recording Var Locations at start of BB01
  V02(r8)  V01(rdx)
Saved:
      G_M62796_IG04:        ; offs=0x000116, size=0x0006, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], gcvars, byref
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M62796_IG01,ins#0,ofs#0) label

__prolog:
Debug: New V00 debug range: first
Debug: New V01 debug range: first
Debug: New V02 debug range: first
IN0009:        sub      rsp, 40
*************** In genFnPrologCalleeRegArgs() for int regs
*************** In genEnregisterIncomingStackArgs()
Debug: Closing V00 debug range.
Debug: Closing V01 debug range.
Debug: Closing V02 debug range.

Saved:
      G_M62796_IG01:        ; offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc
*************** In genFnEpilog()

__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0100 {r8}, gcRegByrefSetCur=0000 {}
IN000a:        add      rsp, 40
IN000b:        ret      
Saved:
      G_M62796_IG03:        ; offs=0x000016, size=0x0005, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M62796_IG01:        ; func=00, offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M62796_IG02:        ; offs=0x000004, size=0x0016, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
G_M62796_IG03:        ; offs=0x00001A, size=0x0005, bbWeight=1, epilog, nogc, extend
G_M62796_IG04:        ; offs=0x00001F, size=0x0006, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], gcvars, byref
*************** In emitJumpDistBind()
Emitter Jump List:
IG02 IN0002 jae[6] -> IG04
  total jump count: 1
Binding: IN0002: 000000 jae      L_M62796_BB02
Binding L_M62796_BB02 to G_M62796_IG04
Estimate of fwd jump [D1FFAB1E/002]: 0008 -> 001F = 0015
Shrinking jump [D1FFAB1E/002]
Adjusted offset of BB03 from 001A to 0016
Adjusted offset of BB04 from 001F to 001B
Total shrinkage =   4, min extra jump size = 4294967295

*************** Finishing PHASE Generate code

*************** Starting PHASE Emit code

Hot  code size = 0x21 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x6)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)

***************************************************************************
Instructions as they come out of the scheduler

G_M62796_IG01:        ; offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0009: 000000 sub      rsp, 40
						;; size=4 bbWeight=1 PerfScore 0.25
G_M62796_IG02:        ; offs=0x000004, size=0x0012, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref, isz
       ; gcrRegs +[r8]
IN0001: 000004 cmp      edx, dword ptr [r8+0x08]
IN0002: 000008 jae      SHORT G_M62796_IG04
IN0003: 00000A mov      eax, edx
IN0004: 00000C lea      rax, bword ptr [r8+8*rax+0x10]
       ; byrRegs +[rax]
IN0005: 000011 xor      ecx, ecx
IN0006: 000013 mov      qword ptr [rax], rcx
						;; size=18 bbWeight=1 PerfScore 6.50
G_M62796_IG03:        ; offs=0x000016, size=0x0005, bbWeight=1, epilog, nogc, extend
IN000a: 000016 add      rsp, 40
IN000b: 00001A ret      
						;; size=5 bbWeight=1 PerfScore 1.25
G_M62796_IG04:        ; offs=0x00001B, size=0x0006, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], gcvars, byref
       ; gcrRegs -[r8]
       ; byrRegs -[rax]
recordRelocation: 00000000D1FFAB1E (rw: 00000000D1FFAB1E) => 00000000D1FFAB1E, type 16 (IMAGE_REL_BASED_REL32), delta 0
IN0007: 00001B call     CORINFO_HELP_RNGCHKFAIL
       ; gcr arg pop 0
IN0008: 000020 int3     
						;; size=6 bbWeight=0 PerfScore 0.00

Allocated method code size =   33 , actual size =   33, unused size =    0

; Total bytes of code 33, prolog size 4, PerfScore 11.30, instruction count 11, allocated bytes for code 33 (MethodHash=57540ab3) for method Program:Test(int,long[]):this (FullOpts)
; ============================================================

*************** After end code gen, before unwindEmit()
G_M62796_IG01:        ; func=00, offs=0x000000, size=0x0004, bbWeight=1, PerfScore 0.25, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG

IN0009: 000000 sub      rsp, 40

G_M62796_IG02:        ; offs=0x000004, size=0x0012, bbWeight=1, PerfScore 6.50, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref, isz

IN0001: 000004 cmp      edx, dword ptr [r8+0x08]
IN0002: 000008 jae      SHORT G_M62796_IG04
IN0003: 00000A mov      eax, edx
IN0004: 00000C lea      rax, bword ptr [r8+8*rax+0x10]
IN0005: 000011 xor      ecx, ecx
IN0006: 000013 mov      qword ptr [rax], rcx

G_M62796_IG03:        ; offs=0x000016, size=0x0005, bbWeight=1, PerfScore 1.25, epilog, nogc, extend

IN000a: 000016 add      rsp, 40
IN000b: 00001A ret

G_M62796_IG04:        ; offs=0x00001B, size=0x0006, bbWeight=0, PerfScore 0.00, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], gcvars, byref

IN0007: 00001B call     CORINFO_HELP_RNGCHKFAIL
IN0008: 000020 int3

*************** Finishing PHASE Emit code

*************** Starting PHASE Emit GC+EH tables
Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0xd1ffab1e (not in unwind data)
  Version           : 1
  Flags             : 0x00
  SizeOfProlog      : 0x04
  CountOfUnwindCodes: 1
  FrameRegister     : none (0)
  FrameOffset       : N/A (no FrameRegister) (Value=0)
  UnwindCodes       :
    CodeOffset: 0x04 UnwindOp: UWOP_ALLOC_SMALL (2)     OpInfo: 4 * 8 + 8 = 40 = 0x28
allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x21, unwindSize=0x6, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 6
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000004 ( STACK_EMPTY )
IL offs 0x0005 : 0x00000011 ( STACK_EMPTY )
IL offs 0x000A : 0x00000016 ( STACK_EMPTY )
IL offs EPILOG : 0x00000016 ( STACK_EMPTY )
IL offs NO_MAP : 0x0000001B ( STACK_EMPTY )

*************** In genSetScopeInfo()
VarLocInfo count is 5
; Variable debug info: 3 live ranges, 3 vars for method Program:Test(int,long[]):this
(V00 this) : From 00000000h to 00000004h, in rcx
(V01 arg1) : From 00000000h to 0000000Ah, in rdx
(V02 arg2) : From 00000000h to 0000000Ch, in r8
*************** In gcInfoBlockHdrSave()
Set code length to 33.
Set ReturnKind to Scalar.
Set Outgoing stack arg area size to 32.
Defining 1 call sites:
    Offset 0x1b, size 5.

*************** Finishing PHASE Emit GC+EH tables
Method code size: 33

Allocations for Program:Test(int,long[]):this (MethodHash=57540ab3)
count:        631, size:      71539, max =       5488
allocateMemory:     131072, nraUsed:      74504

Alloc'd bytes by kind:
                  kind |       size |     pct
  ---------------------+------------+--------
         AssertionProp |       6676 |   9.33%
               ASTNode |       6448 |   9.01%
              InstDesc |       2916 |   4.08%
              ImpStack |        384 |   0.54%
            BasicBlock |       1152 |   1.61%
              CallArgs |          0 |   0.00%
              FlowEdge |          0 |   0.00%
     TreeStatementList |        192 |   0.27%
               SiScope |          0 |   0.00%
       DominatorMemory |         96 |   0.13%
                  LSRA |       7172 |  10.03%
         LSRA_Interval |        480 |   0.67%
      LSRA_RefPosition |       1840 |   2.57%
          Reachability |         40 |   0.06%
                   SSA |        336 |   0.47%
           ValueNumber |      15466 |  21.62%
              LvaTable |       1572 |   2.20%
            UnwindInfo |          0 |   0.00%
                hashBv |         40 |   0.06%
                bitset |         32 |   0.04%
          FixedBitVect |         16 |   0.02%
               Generic |        998 |   1.40%
   LocalAddressVisitor |          0 |   0.00%
         FieldSeqStore |          0 |   0.00%
          MemorySsaMap |         40 |   0.06%
          MemoryPhiArg |          0 |   0.00%
                   CSE |       1440 |   2.01%
                    GC |       1429 |   2.00%
       CorTailCallInfo |          0 |   0.00%
              Inlining |        440 |   0.62%
            ArrayStack |        128 |   0.18%
             DebugInfo |        408 |   0.57%
             DebugOnly |      18579 |  25.97%
               Codegen |       1240 |   1.73%
               LoopOpt |          0 |   0.00%
             LoopClone |          0 |   0.00%
             LoopHoist |          0 |   0.00%
               Unknown |        107 |   0.15%
            RangeCheck |        336 |   0.47%
              CopyProp |        424 |   0.59%
             Promotion |          0 |   0.00%
           SideEffects |          0 |   0.00%
       ObjectAllocator |          0 |   0.00%
    VariableLiveRanges |        880 |   1.23%
           ClassLayout |        128 |   0.18%
       TailMergeThrows |          0 |   0.00%
             EarlyProp |          0 |   0.00%
              ZeroInit |        104 |   0.15%
                   Pgo |          0 |   0.00%

****** DONE compiling Program:Test(int,long[]):this

Texto alterado

Abrir arquivo

lvaSetClass: setting class for V00 to (00000000D1FFAB1E) Program 
'this'    passed in register rcx
Arg #1    passed in register(s) rdx

lvaSetClass: setting class for V02 to (00000000D1FFAB1E) long[] 
Arg #2    passed in register(s) r8

lvaGrabTemp returning 3 (V03 tmp0) (a long lifetime temp) called for OutgoingArgSpace.

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import
Trees after Pre-import

------------ BB01 [000..00B) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation

impImportBlockPending for BB01

[ 3]   4 (0x004) stelem.i8

[ 3]   9 (0x009) stelem.i8

[ 0]  10 (0x00a) ret

STMT00002 ( 0x00A[E-] ... ??? )
               [000012] -----------                         *  RETURN    void

*************** Finishing PHASE Importation
Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----------                         *  RETURN    void

*************** Starting PHASE Expand patchpoints

-- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Indirect call transform

-- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import [no changes]

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Init [no changes]

*************** Starting PHASE Morph - Inlining
**************** Inline Tree

Inlines into 06000001 [via ExtendedDefaultPolicy] Program:Test(int,long[]):this:
Budget: initialTime=93, finalTime=93, initialBudget=930, currentBudget=930
Budget: initialSize=382, finalSize=382

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
=============== No blocks renumbered!

*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----------                         *  RETURN    void

*************** Starting PHASE Allocate Objects
no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks [no changes]

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally
No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Head and tail merge

*************** Finishing PHASE Head and tail merge
Trees after Head and tail merge

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----------                         *  RETURN    void

*************** Starting PHASE Merge throw blocks

*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.

*************** Finishing PHASE Merge throw blocks [no changes]

*************** Starting PHASE Update flow graph early pass

*************** Finishing PHASE Update flow graph early pass [no changes]

*************** Starting PHASE Morph - Promote Structs

*************** Finishing PHASE Morph - Promote Structs [no changes]

LocalAddressVisitor visiting statement:
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----------                         *  RETURN    void

*************** Finishing PHASE Morph - Structs/AddrExp [no changes]

*************** Starting PHASE Early liveness

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V01 V02}
     DEF(0)={       }

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (2)={V01 V02}
     OUT(0)={       }

*************** Finishing PHASE Early liveness
Trees after Early liveness

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
               [000011] nA-XG------                         *  STOREIND  long  
               [000010] ---XG------                         +--*  INDEX_ADDR byref long[]
               [000006] -----------                         |  +--*  LCL_VAR   ref    V02 arg2          (last use)
               [000007] -----------                         |  \--*  LCL_VAR   int    V01 arg1          (last use)
               [000009] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----------                         *  RETURN    void

*************** Starting PHASE Forward Substitution

===> BB01

*************** Finishing PHASE Forward Substitution [no changes]

*************** Starting PHASE Physical promotion

*************** Finishing PHASE Physical promotion [no changes]

*************** Starting PHASE Identify candidates for implicit byref copy omission

*************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes]

*************** Starting PHASE Morph - ByRefs

*************** Finishing PHASE Morph - ByRefs [no changes]

*************** Starting PHASE Morph - Global

*************** In fgMorphBlocks()

Morphing BB01 of 'Program:Test(int,long[]):this'

Non-null prop for index #01 in BB01:
               [000027] ---X-------                         *  ARR_LENGTH int   
fgMorphIndexAddr (after remorph):
               [000036] ---X-+-----                         *  COMMA     byref 
               [000028] ---X-+-----                         +--*  BOUNDS_CHECK_Rng void  
               [000007] -----+-----                         |  +--*  LCL_VAR   int    V01 arg1          (last use)
               [000027] -----+-----                         |  \--*  ARR_LENGTH int   
               [000006] -----+-----                         |     \--*  LCL_VAR   ref    V02 arg2          (last use)
               [000035] -----+-----                         \--*  ARR_ADDR  byref long[]
               [000034] -----+-----                            \--*  ADD       byref 
               [000025] -----+-----                               +--*  LCL_VAR   ref    V02 arg2          (last use)
               [000033] -----+-----                               \--*  ADD       long  
               [000031] -----+-----                                  +--*  LSH       long  
               [000029] -----+---U-                                  |  +--*  CAST      long <- uint
               [000026] -----+-----                                  |  |  \--*  LCL_VAR   int    V01 arg1          (last use)
               [000030] -----+-N---                                  |  \--*  CNS_INT   long   3
               [000032] -----+-----                                  \--*  CNS_INT   long   16

fgMorphTree BB01, STMT00001 (after)
               [000011] nA-XG+-----                         *  STOREIND  long  
               [000036] ---X-+-----                         +--*  COMMA     byref 
               [000028] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000007] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1          (last use)
               [000027] -----+-----                         |  |  \--*  ARR_LENGTH int   
               [000006] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2          (last use)
               [000035] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000034] -----+-----                         |     \--*  ADD       byref 
               [000025] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2          (last use)
               [000033] -----+-----                         |        \--*  ADD       long  
               [000031] -----+-----                         |           +--*  LSH       long  
               [000029] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000026] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1          (last use)
               [000030] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000032] -----+-----                         |           \--*  CNS_INT   long   16
               [000009] -----+-----                         \--*  CNS_INT   long   0

fgMorphTree BB01, STMT00002 (before)
               [000012] -----------                         *  RETURN    void

*************** In fgMarkDemotedImplicitByRefArgs()

*************** Finishing PHASE Morph - Global
Trees after Morph - Global

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
               [000011] nA-XG+-----                         *  STOREIND  long  
               [000036] ---X-+-----                         +--*  COMMA     byref 
               [000028] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000007] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1         
               [000027] -----+-----                         |  |  \--*  ARR_LENGTH int   
               [000006] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2         
               [000035] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000034] -----+-----                         |     \--*  ADD       byref 
               [000025] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2         
               [000033] -----+-----                         |        \--*  ADD       long  
               [000031] -----+-----                         |           +--*  LSH       long  
               [000029] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000026] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
               [000030] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000032] -----+-----                         |           \--*  CNS_INT   long   16
               [000009] -----+-----                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----+-----                         *  RETURN    void

*************** Starting PHASE GS Cookie
No GS security needed

*************** Finishing PHASE GS Cookie [no changes]

*************** Starting PHASE Compute edge weights (1, false)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

-- no profile data, so using default called count
 -- not optimizing or no profile data, so not computing edge weights

*************** Finishing PHASE Compute edge weights (1, false) [no changes]

*************** Starting PHASE Create EH funclets

*************** Finishing PHASE Create EH funclets [no changes]

*************** Starting PHASE Invert loops

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
=============== No blocks renumbered!

*************** Finishing PHASE Invert loops [no changes]

*************** Starting PHASE Optimize control flow

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize control flow
Trees after Optimize control flow

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
               [000011] nA-XG+-----                         *  STOREIND  long  
               [000036] ---X-+-----                         +--*  COMMA     byref 
               [000028] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000007] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1         
               [000027] -----+-----                         |  |  \--*  ARR_LENGTH int   
               [000006] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2         
               [000035] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000034] -----+-----                         |     \--*  ADD       byref 
               [000025] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2         
               [000033] -----+-----                         |        \--*  ADD       long  
               [000031] -----+-----                         |           +--*  LSH       long  
               [000029] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000026] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
               [000030] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000032] -----+-----                         |           \--*  CNS_INT   long   16
               [000009] -----+-----                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----+-----                         *  RETURN    void

*************** Starting PHASE Post-morph head and tail merge

*************** Finishing PHASE Post-morph head and tail merge
Trees after Post-morph head and tail merge

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
               [000011] nA-XG+-----                         *  STOREIND  long  
               [000036] ---X-+-----                         +--*  COMMA     byref 
               [000028] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000007] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1         
               [000027] -----+-----                         |  |  \--*  ARR_LENGTH int   
               [000006] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2         
               [000035] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000034] -----+-----                         |     \--*  ADD       byref 
               [000025] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2         
               [000033] -----+-----                         |        \--*  ADD       long  
               [000031] -----+-----                         |           +--*  LSH       long  
               [000029] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000026] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
               [000030] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000032] -----+-----                         |           \--*  CNS_INT   long   16
               [000009] -----+-----                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----+-----                         *  RETURN    void

*************** Starting PHASE Compute blocks reachability
Return blocks: BB01

Renumbering the basic blocks for fgComputeReachability pass #1

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
=============== No blocks renumbered!
Enter blocks: BB01

Dominator computation start blocks (those blocks with no incoming edges):
BB01

Inside fgBuildDomTree

After computing the Dominance Tree:

After numbering the dominator tree:
BB01: pre=01, post=01

*************** Finishing PHASE Compute blocks reachability [no changes]

*************** Starting PHASE Set block weights

*************** Finishing PHASE Set block weights [no changes]

*************** Starting PHASE Find loops
*************** In optFindLoops()
*************** In optMarkLoopHeads()
0 loop heads marked

*************** Finishing PHASE Find loops
Trees after Find loops

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
               [000011] nA-XG+-----                         *  STOREIND  long  
               [000036] ---X-+-----                         +--*  COMMA     byref 
               [000028] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000007] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1         
               [000027] -----+-----                         |  |  \--*  ARR_LENGTH int   
               [000006] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2         
               [000035] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000034] -----+-----                         |     \--*  ADD       byref 
               [000025] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2         
               [000033] -----+-----                         |        \--*  ADD       long  
               [000031] -----+-----                         |           +--*  LSH       long  
               [000029] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000026] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
               [000030] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000032] -----+-----                         |           \--*  CNS_INT   long   16
               [000009] -----+-----                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----+-----                         *  RETURN    void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Clone loops

*************** In optCloneLoops()
  No loops to clone

*************** Finishing PHASE Clone loops [no changes]

*************** Starting PHASE Unroll loops

*************** Finishing PHASE Unroll loops [no changes]

*************** Starting PHASE Clear loop info

*************** Finishing PHASE Clear loop info [no changes]

*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function

*************** Finishing PHASE Morph array ops [no changes]

*************** Starting PHASE Mark local vars

*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** marking local variables in block BB01 (weight=1)
STMT00000 ( 0x000[E-] ... 0x004 )
               [000005] nA-XG+-----                         *  STOREIND  long  
               [000024] ---X-+-----                         +--*  COMMA     byref 
               [000016] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000001] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1         
               [000015] ---X-+-----                         |  |  \--*  ARR_LENGTH int   
               [000000] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2         
               [000023] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000022] -----+-----                         |     \--*  ADD       byref 
               [000013] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2         
               [000021] -----+-----                         |        \--*  ADD       long  
               [000019] -----+-----                         |           +--*  LSH       long  
               [000017] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000014] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
               [000018] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000020] -----+-----                         |           \--*  CNS_INT   long   16
               [000003] -----+-----                         \--*  CNS_INT   long   0
New refCnts for V01: refCnt =  1, refCntWtd = 1
New refCnts for V02: refCnt =  1, refCntWtd = 1
New refCnts for V02: refCnt =  2, refCntWtd = 2
New refCnts for V01: refCnt =  2, refCntWtd = 2
STMT00001 ( 0x005[E-] ... 0x009 )
               [000011] nA-XG+-----                         *  STOREIND  long  
               [000036] ---X-+-----                         +--*  COMMA     byref 
               [000028] ---X-+-----                         |  +--*  BOUNDS_CHECK_Rng void  
               [000007] -----+-----                         |  |  +--*  LCL_VAR   int    V01 arg1         
               [000027] -----+-----                         |  |  \--*  ARR_LENGTH int   
               [000006] -----+-----                         |  |     \--*  LCL_VAR   ref    V02 arg2         
               [000035] -----+-----                         |  \--*  ARR_ADDR  byref long[]
               [000034] -----+-----                         |     \--*  ADD       byref 
               [000025] -----+-----                         |        +--*  LCL_VAR   ref    V02 arg2         
               [000033] -----+-----                         |        \--*  ADD       long  
               [000031] -----+-----                         |           +--*  LSH       long  
               [000029] -----+---U-                         |           |  +--*  CAST      long <- uint
               [000026] -----+-----                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
               [000030] -----+-N---                         |           |  \--*  CNS_INT   long   3
               [000032] -----+-----                         |           \--*  CNS_INT   long   16
               [000009] -----+-----                         \--*  CNS_INT   long   0
New refCnts for V01: refCnt =  3, refCntWtd = 3
New refCnts for V02: refCnt =  3, refCntWtd = 3
New refCnts for V02: refCnt =  4, refCntWtd = 4
New refCnts for V01: refCnt =  4, refCntWtd = 4
STMT00002 ( 0x00A[E-] ... 0x00A )
               [000012] -----+-----                         *  RETURN    void

*************** Finishing PHASE Mark local vars [no changes]

*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()

*************** Finishing PHASE Find oper order
Trees after Find oper order

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
     ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long  
     ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref 
     (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
     (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         
     (  3,  3) [000027] -----O-----                         |  |  \--*  ARR_LENGTH int   
     (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         
     (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[]
     (  3,  5) [000034] -------N---                         |     \--*  ADD       byref 
     (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         
     (  4,  5) [000033] -------N---                         |        \--*  ADD       long  
     (  3,  4) [000031] -------N---                         |           +--*  LSH       long  
     (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint
     (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
     (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3
     (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16
     (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
     (  0,  0) [000012] -----------                         *  RETURN    void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has   16 tree nodes

*************** Finishing PHASE Set block order
Trees after Set block order

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
N016 ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long  
N014 ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref 
N004 (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
N001 (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         
N003 (  3,  3) [000027] -----O-----                         |  |  \--*  ARR_LENGTH int   
N002 (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         
N013 (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[]
N012 (  3,  5) [000034] -------N---                         |     \--*  ADD       byref 
N005 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         
N011 (  4,  5) [000033] -------N---                         |        \--*  ADD       long  
N009 (  3,  4) [000031] -------N---                         |           +--*  LSH       long  
N007 (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint
N006 (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         
N008 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3
N010 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16
N015 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0) [000012] -----------                         *  RETURN    void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 2.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]

Inside fgBuildDomTree

After computing the Dominance Tree:

*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V02 V01}
     DEF(0)={       } + ByrefExposed + GcHeap

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (2)={V02 V01}
     OUT(0)={       }

*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x004 )
N016 ( 16, 20) [000005] nA-XGO-----                         *  STOREIND  long  
N014 ( 11, 16) [000024] ---X-O-----                         +--*  COMMA     byref 
N004 (  8, 11) [000016] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
N001 (  1,  1) [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1
N003 (  3,  3) [000015] ---X-------                         |  |  \--*  ARR_LENGTH int   
N002 (  1,  1) [000000] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1
N013 (  3,  5) [000023] -----O-----                         |  \--*  ARR_ADDR  byref long[]
N012 (  3,  5) [000022] -------N---                         |     \--*  ADD       byref 
N005 (  1,  1) [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1
N011 (  4,  5) [000021] -------N---                         |        \--*  ADD       long  
N009 (  3,  4) [000019] -------N---                         |           +--*  LSH       long  
N007 (  2,  3) [000017] ---------U-                         |           |  +--*  CAST      long <- uint
N006 (  1,  1) [000014] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1
N008 (  1,  1) [000018] -------N---                         |           |  \--*  CNS_INT   long   3
N010 (  1,  1) [000020] -----------                         |           \--*  CNS_INT   long   16
N015 (  1,  1) [000003] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
N016 ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long  
N014 ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref 
N004 (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
N001 (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1
N003 (  3,  3) [000027] -----O-----                         |  |  \--*  ARR_LENGTH int   
N002 (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1
N013 (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[]
N012 (  3,  5) [000034] -------N---                         |     \--*  ADD       byref 
N005 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use)
N011 (  4,  5) [000033] -------N---                         |        \--*  ADD       long  
N009 (  3,  4) [000031] -------N---                         |           +--*  LSH       long  
N007 (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint
N006 (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use)
N008 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3
N010 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16
N015 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0) [000012] -----------                         *  RETURN    void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V01.1
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method

*************** Finishing PHASE Early Value Propagation [no changes]

*************** Starting PHASE Do value numbering

---------

***** BB01, STMT00001(before)
N016 ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long  
N014 ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref 
N004 (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void  
N001 (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1
N003 (  3,  3) [000027] -----O-----                         |  |  \--*  ARR_LENGTH int   
N002 (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1
N013 (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[]
N012 (  3,  5) [000034] -------N---                         |     \--*  ADD       byref 
N005 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use)
N011 (  4,  5) [000033] -------N---                         |        \--*  ADD       long  
N009 (  3,  4) [000031] -------N---                         |           +--*  LSH       long  
N007 (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint
N006 (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use)
N008 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3
N010 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16
N015 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0

N001 [000007]   LCL_VAR   V01 arg1         u:1 => $80 {InitVal($40)}
N002 [000006]   LCL_VAR   V02 arg2         u:1 => $c0 {InitVal($41)}
N003 [000027]   ARR_LENGTH => $81 {ARR_LENGTH($c0)}
N004 [000028]   BOUNDS_CHECK_Rng => $146 {norm=$VN.Void, exc=$143 {IndexOutOfRangeExc($80, $81)}}
N005 [000025]   LCL_VAR   V02 arg2         u:1 (last use) => $c0 {InitVal($41)}
N006 [000026]   LCL_VAR   V01 arg1         u:1 (last use) => $80 {InitVal($40)}
N007 [000029]   CAST      => $1c0 {$80, long <- uint}
N008 [000030]   CNS_INT   3 => $200 {LngCns:  3}
N009 [000031]   LSH       => $1c1 {LSH($1c0, $200)}
N010 [000032]   CNS_INT   16 => $202 {LngCns:  16}
N011 [000033]   ADD       => $1c2 {ADD($1c1, $202)}
N012 [000034]   ADD       => $240 {ADD($c0, $1c2)}
    VNForHandle(arrElemType: long) is $280
N013 [000035]   ARR_ADDR  => $2c0 {PtrToArrElem($280, $c0, $1c0, $201)}
N014 [000036]   COMMA     => $242 {norm=$2c0 {PtrToArrElem($280, $c0, $1c0, $201)}, exc=$143 {IndexOutOfRangeExc($80, $81)}}
N015 [000009]   CNS_INT   0 => $201 {LngCns:  0}
  Array element store: elemTypeEq is $280 for long[]
      AX1: select([$100]store($380, $280, $341), $280) ==> $341.
    VNForMapSelect($380, $280):mem returns $341 {$300[$c0 := $340]}
  GcHeap[elemTypeEq: $280] is $341
      AX1: select([$300]store($341, $c0, $340), $c0) ==> $340.
    VNForMapSelect($341, $c0):mem returns $340 {$301[$1c0 := $201]}
  GcHeap[elemTypeEq][array: $c0] is $340
  GcHeap[elemTypeEq][array][index: $1c0] = $201:
    VNForMapStore($340, $1c0, $201):mem in BB01 returns $342 {$340[$1c0 := $201]}
  GcHeap[elemTypeEq][array: $c0] = $342:
    VNForMapStore($341, $c0, $342):mem in BB01 returns $343 {$341[$c0 := $342]}
  GcHeap[elemTypeEq: $280] = $343:
    VNForMapStore($380, $280, $343):heap in BB01 returns $381 {$380[$280 := $343]}
  fgCurMemoryVN[GcHeap] assigned for array element store at [000011] to VN: $381.
N016 [000011]   STOREIND  => $146 {norm=$VN.Void, exc=$143 {IndexOutOfRangeExc($80, $81)}}

***** BB01, STMT00001(after)
N016 ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long   $146
N014 ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref  $242
N004 (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $146
N001 (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) [000027] -----O-----                         |  |  \--*  ARR_LENGTH int    $81
N002 (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5) [000034] -------N---                         |     \--*  ADD       byref  $240
N005 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N011 (  4,  5) [000033] -------N---                         |        \--*  ADD       long   $1c2
N009 (  3,  4) [000031] -------N---                         |           +--*  LSH       long   $1c1
N007 (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N006 (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use) $80
N008 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N010 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16 $202
N015 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0 $201

---------

***** BB01, STMT00002(before)
N001 (  0,  0) [000012] -----------                         *  RETURN    void

N001 [000012]   RETURN    => $VN.Void

***** BB01, STMT00002(after)
N001 (  0,  0) [000012] -----------                         *  RETURN    void   $VN.Void

finish(BB01).

*************** Finishing PHASE Do value numbering
Trees after Do value numbering

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
N016 ( 16, 20) [000011] nA-XGO-----                         *  STOREIND  long   $146
N014 ( 11, 16) [000036] ---X-O-----                         +--*  COMMA     byref  $242
N004 (  8, 11) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $146
N001 (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) [000027] -----O-----                         |  |  \--*  ARR_LENGTH int    $81
N002 (  1,  1) [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5) [000034] -------N---                         |     \--*  ADD       byref  $240
N005 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N011 (  4,  5) [000033] -------N---                         |        \--*  ADD       long   $1c2
N009 (  3,  4) [000031] -------N---                         |           +--*  LSH       long   $1c1
N007 (  2,  3) [000029] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N006 (  1,  1) [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use) $80
N008 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N010 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16 $202
N015 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0) [000012] -----------                         *  RETURN    void   $VN.Void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V01.1
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Hoist loop code

No loops; no hoisting

*************** Finishing PHASE Hoist loop code [no changes]

*************** Starting PHASE VN based copy prop
Copy Assertion for BB01
  curSsaName stack: { }

Live vars after [000025]: {V01 V02} -{V02} => {V01}
							Live vars after [000026]: {V01} -{V01} => {}

*************** Finishing PHASE VN based copy prop [no changes]

*************** Starting PHASE Redundant branch opts

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Redundant branch opts [no changes]

*************** Starting PHASE Optimize Valnum CSEs

Candidate CSE #01, key=$81 in BB01, [cost= 3, size= 3]: 
N003 (  3,  3) CSE #01 (use)[000027] -----O-----                         *  ARR_LENGTH int    $81
N002 (  1,  1)              [000006] -----------                         \--*  LCL_VAR   ref    V02 arg2         u:1 $c0

Blocks that generate CSE def/uses
BB01 cseGen = 000000000000000F CSE #01.c, CSE #02.c
[info] HasGlobalUse overestimated for V01.1
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully

Performing DataFlow for ValnumCSE's

After performing DataFlow for ValnumCSE's
BB01
 in: 0000000000000000 
gen: 000000000000000F CSE #01.c, CSE #02.c
out: 000000000000000F CSE #01.c, CSE #02.c

Labeling the CSEs with Use/Def information
BB01 [000015] Def of CSE #01 [weight=1]
BB01 [000017] Def of CSE #02 [weight=1]
BB01 [000027] Use of CSE #01 [weight=1]
BB01 [000029] Use of CSE #02 [weight=1]

************ Trees at start of optValnumCSE_Heuristic()

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x004 )
N016 ( 16, 20)              [000005] nA-XGO-----                         *  STOREIND  long   $145
N014 ( 11, 16)              [000024] ---X-O-----                         +--*  COMMA     byref  $241
N004 (  8, 11)              [000016] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1)              [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) CSE #01 (def)[000015] ---X-------                         |  |  \--*  ARR_LENGTH int    $180
N002 (  1,  1)              [000000] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5)              [000023] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5)              [000022] -------N---                         |     \--*  ADD       byref  $240
N005 (  1,  1)              [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N011 (  4,  5)              [000021] -------N---                         |        \--*  ADD       long   $1c2
N009 (  3,  4)              [000019] -------N---                         |           +--*  LSH       long   $1c1
N007 (  2,  3) CSE #02 (def)[000017] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N006 (  1,  1)              [000014] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 $80
N008 (  1,  1)              [000018] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N010 (  1,  1)              [000020] -----------                         |           \--*  CNS_INT   long   16 $202
N015 (  1,  1)              [000003] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
N016 ( 16, 20)              [000011] nA-XGO-----                         *  STOREIND  long   $146
N014 ( 11, 16)              [000036] ---X-O-----                         +--*  COMMA     byref  $242
N004 (  8, 11)              [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $146
N001 (  1,  1)              [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N003 (  3,  3) CSE #01 (use)[000027] -----O-----                         |  |  \--*  ARR_LENGTH int    $81
N002 (  1,  1)              [000006] -----------                         |  |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N013 (  3,  5)              [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N012 (  3,  5)              [000034] -------N---                         |     \--*  ADD       byref  $240
N005 (  1,  1)              [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N011 (  4,  5)              [000033] -------N---                         |        \--*  ADD       long   $1c2
N009 (  3,  4)              [000031] -------N---                         |           +--*  LSH       long   $1c1
N007 (  2,  3) CSE #02 (use)[000029] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N006 (  1,  1)              [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use) $80
N008 (  1,  1)              [000030] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N010 (  1,  1)              [000032] -----------                         |           \--*  CNS_INT   long   16 $202
N015 (  1,  1)              [000009] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0)              [000012] -----------                         *  RETURN    void   $VN.Void

-------------------------------------------------------------------------------------------------------------------

Aggressive CSE Promotion cutoff is 200.000000
Moderate CSE Promotion cutoff is 100.000000
enregCount is 2
Framesize estimate is 0x0000
We have a small frame

Sorted CSE candidates:
CSE #01, {$81 , $2  } useCnt=1: [def=100.000000, use=100.000000, cost=  3      ]
        :: N003 (  3,  3) CSE #01 (def)[000015] ---X-------                         *  ARR_LENGTH int    $180
CSE #02, {$1c0, $2  } useCnt=1: [def=100.000000, use=100.000000, cost=  2      ]
        :: N007 (  2,  3) CSE #02 (def)[000017] ---------U-                         *  CAST      long <- uint $1c0

Considering CSE #01 {$81 , $2  } [def=100.000000, use=100.000000, cost=  3      ]
CSE Expression : 
N003 (  3,  3) CSE #01 (def)[000015] ---X-------                         *  ARR_LENGTH int    $180
N002 (  1,  1)              [000000] -----------                         \--*  LCL_VAR   ref    V02 arg2         u:1 $c0

Aggressive CSE Promotion (300.000000 >= 200.000000)
cseRefCnt=300.000000, aggressiveRefCnt=200.000000, moderateRefCnt=100.000000
defCnt=100.000000, useCnt=100.000000, cost=3, size=3
def_cost=1, use_cost=1, extra_no_cost=4, extra_yes_cost=0
CSE cost savings check (304.000000 >= 200.000000) passes

Promoting CSE:

lvaGrabTemp returning 4 (V04 rat0) (a long lifetime temp) called for CSE - aggressive.
CSE #01 is single-def, so associated CSE temp V04 will be in SSA
New refCnts for V04: refCnt =  2, refCntWtd = 2
New refCnts for V04: refCnt =  3, refCntWtd = 3

CSE #01 def at [000015] replaced in BB01 with def of V04
optValnumCSE morphed tree:
N019 ( 17, 21)              [000005] nA-XGO-----                         *  STOREIND  long   $145
N017 ( 12, 17)              [000024] -A-X-O-----                         +--*  COMMA     byref  $241
N007 (  9, 12)              [000016] -A-X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1)              [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N006 (  4,  4)              [000039] -A-X-------                         |  |  \--*  COMMA     int    $180
N004 (  3,  3) CSE #01 (def)[000037] DA-X-------                         |  |     +--*  STORE_LCL_VAR int    V04 cse0         d:1 $VN.Void
N003 (  3,  3)              [000015] ---X-------                         |  |     |  \--*  ARR_LENGTH int    $180
N002 (  1,  1)              [000000] -----------                         |  |     |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N005 (  1,  1)              [000038] -----------                         |  |     \--*  LCL_VAR   int    V04 cse0         u:1 $180
N016 (  3,  5)              [000023] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N015 (  3,  5)              [000022] -------N---                         |     \--*  ADD       byref  $240
N008 (  1,  1)              [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N014 (  4,  5)              [000021] -------N---                         |        \--*  ADD       long   $1c2
N012 (  3,  4)              [000019] -------N---                         |           +--*  LSH       long   $1c1
N010 (  2,  3) CSE #02 (def)[000017] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N009 (  1,  1)              [000014] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 $80
N011 (  1,  1)              [000018] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N013 (  1,  1)              [000020] -----------                         |           \--*  CNS_INT   long   16 $202
N018 (  1,  1)              [000003] -----------                         \--*  CNS_INT   long   0 $201

Working on the replacement of the CSE #01 use at [000027] in BB01
optValnumCSE morphed tree:
N015 ( 14, 18)              [000011] nA-XGO-----                         *  STOREIND  long   $146
N013 (  9, 14)              [000036] ---X-O-----                         +--*  COMMA     byref  $242
N003 (  6,  9)              [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $146
N001 (  1,  1)              [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N002 (  1,  1)              [000040] -----------                         |  |  \--*  LCL_VAR   int    V04 cse0         u:1 $81
N012 (  3,  5)              [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N011 (  3,  5)              [000034] -------N---                         |     \--*  ADD       byref  $240
N004 (  1,  1)              [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N010 (  4,  5)              [000033] -------N---                         |        \--*  ADD       long   $1c2
N008 (  3,  4)              [000031] -------N---                         |           +--*  LSH       long   $1c1
N006 (  2,  3) CSE #02 (use)[000029] ---------U-                         |           |  +--*  CAST      long <- uint $1c0
N005 (  1,  1)              [000026] -----------                         |           |  |  \--*  LCL_VAR   int    V01 arg1         u:1 (last use) $80
N007 (  1,  1)              [000030] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N009 (  1,  1)              [000032] -----------                         |           \--*  CNS_INT   long   16 $202
N014 (  1,  1)              [000009] -----------                         \--*  CNS_INT   long   0 $201

Considering CSE #02 {$1c0, $2  } [def=100.000000, use=100.000000, cost=  2      ]
CSE Expression : 
N010 (  2,  3) CSE #02 (def)[000017] ---------U-                         *  CAST      long <- uint $1c0
N009 (  1,  1)              [000014] -----------                         \--*  LCL_VAR   int    V01 arg1         u:1 $80

Aggressive CSE Promotion (300.000000 >= 200.000000)
cseRefCnt=300.000000, aggressiveRefCnt=200.000000, moderateRefCnt=100.000000
defCnt=100.000000, useCnt=100.000000, cost=2, size=3
def_cost=1, use_cost=1, extra_no_cost=4, extra_yes_cost=0
CSE cost savings check (204.000000 >= 200.000000) passes

Promoting CSE:

lvaGrabTemp returning 5 (V05 rat0) (a long lifetime temp) called for CSE - aggressive.
CSE #02 is single-def, so associated CSE temp V05 will be in SSA
New refCnts for V05: refCnt =  2, refCntWtd = 2
New refCnts for V05: refCnt =  3, refCntWtd = 3

CSE #02 def at [000017] replaced in BB01 with def of V05
optValnumCSE morphed tree:
N022 ( 18, 22)              [000005] nA-XGO-----                         *  STOREIND  long   $145
N020 ( 13, 18)              [000024] -A-X-O-----                         +--*  COMMA     byref  $241
N007 (  9, 12)              [000016] -A-X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1)              [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N006 (  4,  4)              [000039] -A-X-------                         |  |  \--*  COMMA     int    $180
N004 (  3,  3) CSE #01 (def)[000037] DA-X-------                         |  |     +--*  STORE_LCL_VAR int    V04 cse0         d:1 $VN.Void
N003 (  3,  3)              [000015] ---X-------                         |  |     |  \--*  ARR_LENGTH int    $180
N002 (  1,  1)              [000000] -----------                         |  |     |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N005 (  1,  1)              [000038] -----------                         |  |     \--*  LCL_VAR   int    V04 cse0         u:1 $180
N019 (  4,  6)              [000023] -A---O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N018 (  4,  6)              [000022] -A-----N---                         |     \--*  ADD       byref  $240
N008 (  1,  1)              [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N017 (  5,  6)              [000021] -A-----N---                         |        \--*  ADD       long   $1c2
N015 (  4,  5)              [000019] -A-----N---                         |           +--*  LSH       long   $1c1
N013 (  3,  4)              [000043] -A---------                         |           |  +--*  COMMA     long   $1c0
N011 (  2,  3) CSE #02 (def)[000041] DA---------                         |           |  |  +--*  STORE_LCL_VAR long   V05 cse1         d:1 $VN.Void
N010 (  2,  3)              [000017] ---------U-                         |           |  |  |  \--*  CAST      long <- uint $1c0
N009 (  1,  1)              [000014] -----------                         |           |  |  |     \--*  LCL_VAR   int    V01 arg1         u:1 $80
N012 (  1,  1)              [000042] -----------                         |           |  |  \--*  LCL_VAR   long   V05 cse1         u:1 $1c0
N014 (  1,  1)              [000018] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N016 (  1,  1)              [000020] -----------                         |           \--*  CNS_INT   long   16 $202
N021 (  1,  1)              [000003] -----------                         \--*  CNS_INT   long   0 $201

Working on the replacement of the CSE #02 use at [000029] in BB01
optValnumCSE morphed tree:
N014 ( 13, 16)              [000011] nA-XGO-----                         *  STOREIND  long   $146
N012 (  8, 12)              [000036] ---X-O-----                         +--*  COMMA     byref  $242
N003 (  6,  9)              [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $146
N001 (  1,  1)              [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N002 (  1,  1)              [000040] -----------                         |  |  \--*  LCL_VAR   int    V04 cse0         u:1 $81
N011 (  2,  3)              [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N010 (  2,  3)              [000034] -------N---                         |     \--*  ADD       byref  $240
N004 (  1,  1)              [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N009 (  3,  3)              [000033] -------N---                         |        \--*  ADD       long   $1c2
N007 (  2,  2)              [000031] -------N---                         |           +--*  LSH       long   $1c1
N005 (  1,  1)              [000044] -----------                         |           |  +--*  LCL_VAR   long   V05 cse1         u:1 $1c0
N006 (  1,  1)              [000030] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N008 (  1,  1)              [000032] -----------                         |           \--*  CNS_INT   long   16 $202
N013 (  1,  1)              [000009] -----------                         \--*  CNS_INT   long   0 $201

*************** Finishing PHASE Optimize Valnum CSEs
Trees after Optimize Valnum CSEs

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x004 )
N022 ( 18, 22) [000005] nA-XGO-----                         *  STOREIND  long   $145
N020 ( 13, 18) [000024] -A-X-O-----                         +--*  COMMA     byref  $241
N007 (  9, 12) [000016] -A-X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $145
N001 (  1,  1) [000001] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N006 (  4,  4) [000039] -A-X-------                         |  |  \--*  COMMA     int    $180
N004 (  3,  3) [000037] DA-X-------                         |  |     +--*  STORE_LCL_VAR int    V04 cse0         d:1 $VN.Void
N003 (  3,  3) [000015] ---X-------                         |  |     |  \--*  ARR_LENGTH int    $180
N002 (  1,  1) [000000] -----------                         |  |     |     \--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N005 (  1,  1) [000038] -----------                         |  |     \--*  LCL_VAR   int    V04 cse0         u:1 $180
N019 (  4,  6) [000023] -A---O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N018 (  4,  6) [000022] -A-----N---                         |     \--*  ADD       byref  $240
N008 (  1,  1) [000013] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 $c0
N017 (  5,  6) [000021] -A-----N---                         |        \--*  ADD       long   $1c2
N015 (  4,  5) [000019] -A-----N---                         |           +--*  LSH       long   $1c1
N013 (  3,  4) [000043] -A---------                         |           |  +--*  COMMA     long   $1c0
N011 (  2,  3) [000041] DA---------                         |           |  |  +--*  STORE_LCL_VAR long   V05 cse1         d:1 $VN.Void
N010 (  2,  3) [000017] ---------U-                         |           |  |  |  \--*  CAST      long <- uint $1c0
N009 (  1,  1) [000014] -----------                         |           |  |  |     \--*  LCL_VAR   int    V01 arg1         u:1 $80
N012 (  1,  1) [000042] -----------                         |           |  |  \--*  LCL_VAR   long   V05 cse1         u:1 $1c0
N014 (  1,  1) [000018] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N016 (  1,  1) [000020] -----------                         |           \--*  CNS_INT   long   16 $202
N021 (  1,  1) [000003] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
N014 ( 13, 16) [000011] nA-XGO-----                         *  STOREIND  long   $146
N012 (  8, 12) [000036] ---X-O-----                         +--*  COMMA     byref  $242
N003 (  6,  9) [000028] ---X-O-----                         |  +--*  BOUNDS_CHECK_Rng void   $146
N001 (  1,  1) [000007] -----------                         |  |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N002 (  1,  1) [000040] -----------                         |  |  \--*  LCL_VAR   int    V04 cse0         u:1 $81
N011 (  2,  3) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N010 (  2,  3) [000034] -------N---                         |     \--*  ADD       byref  $240
N004 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N009 (  3,  3) [000033] -------N---                         |        \--*  ADD       long   $1c2
N007 (  2,  2) [000031] -------N---                         |           +--*  LSH       long   $1c1
N005 (  1,  1) [000044] -----------                         |           |  +--*  LCL_VAR   long   V05 cse1         u:1 $1c0
N006 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N008 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16 $202
N013 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0) [000012] -----------                         *  RETURN    void   $VN.Void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] NumUses overestimated for V01.1: IR 3 SSA 4
[info] HasGlobalUse overestimated for V01.1
[info] NumUses overestimated for V02.1: IR 3 SSA 4
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully
*************** In fgDebugCheckLoopTable
Disabling SSA checking before assertion prop

BB01 valueGen = #01 #02

BB01:
 in   = #NA
 out  = #01 #02

Propagating #NA for BB01, stmt STMT00000, tree [000001], tree -> #NA
Propagating #NA for BB01, stmt STMT00000, tree [000000], tree -> #NA
Propagating #NA for BB01, stmt STMT00000, tree [000015], tree -> #01
Propagating #01 for BB01, stmt STMT00000, tree [000037], tree -> #NA
Propagating #01 for BB01, stmt STMT00000, tree [000038], tree -> #NA
Propagating #01 for BB01, stmt STMT00000, tree [000039], tree -> #NA
Propagating #01 for BB01, stmt STMT00000, tree [000016], tree -> #02
Propagating #01 #02 for BB01, stmt STMT00000, tree [000013], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000014], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000017], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000041], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000042], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000043], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000018], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000019], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000020], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000021], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000022], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000023], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000024], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000003], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00000, tree [000005], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000007], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000040], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000028], tree -> #02

VN based redundant (a[i] followed by a[i]) bounds check assertion prop for index #02 in BB01:
N003 (  6,  9) [000028] ---X-O-----                         *  BOUNDS_CHECK_Rng void   $146
Propagating #01 #02 for BB01, stmt STMT00001, tree [000025], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000044], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000030], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000031], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000032], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000033], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000034], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000035], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000036], tree -> #NA
Before optRemoveRangeCheck:
N012 (  8, 12) [000036] ---X-O-----                         *  COMMA     byref  $242
N003 (  6,  9) [000028] ---X-O-----                         +--*  BOUNDS_CHECK_Rng void   $146
N001 (  1,  1) [000007] -----------                         |  +--*  LCL_VAR   int    V01 arg1         u:1 $80
N002 (  1,  1) [000040] -----------                         |  \--*  LCL_VAR   int    V04 cse0         u:1 $81
N011 (  2,  3) [000035] -----O-----                         \--*  ARR_ADDR  byref long[] $2c0
N010 (  2,  3) [000034] -------N---                            \--*  ADD       byref  $240
N004 (  1,  1) [000025] -----------                               +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N009 (  3,  3) [000033] -------N---                               \--*  ADD       long   $1c2
N007 (  2,  2) [000031] -------N---                                  +--*  LSH       long   $1c1
N005 (  1,  1) [000044] -----------                                  |  +--*  LCL_VAR   long   V05 cse1         u:1 $1c0
N006 (  1,  1) [000030] -------N---                                  |  \--*  CNS_INT   long   3 $200
N008 (  1,  1) [000032] -----------                                  \--*  CNS_INT   long   16 $202
After optRemoveRangeCheck for [000036]:
N014 ( 13, 16) [000011] nA--GO-----                         *  STOREIND  long   $146
N012 (  8, 12) [000036] -----O-N---                         +--*  COMMA     byref  $242
N003 (  6,  9) [000028] -----------                         |  +--*  NOP       void  
N011 (  2,  3) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N010 (  2,  3) [000034] -------N---                         |     \--*  ADD       byref  $240
N004 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N009 (  3,  3) [000033] -------N---                         |        \--*  ADD       long   $1c2
N007 (  2,  2) [000031] -------N---                         |           +--*  LSH       long   $1c1
N005 (  1,  1) [000044] -----------                         |           |  +--*  LCL_VAR   long   V05 cse1         u:1 $1c0
N006 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N008 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16 $202
N013 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0 $201
Propagating #01 #02 for BB01, stmt STMT00001, tree [000009], tree -> #NA
Propagating #01 #02 for BB01, stmt STMT00001, tree [000011], tree -> #NA
Re-morphing this stmt:
STMT00001 ( 0x005[E-] ... 0x009 )
N014 ( 13, 16) [000011] nA--GO-----                         *  STOREIND  long   $146
N012 (  8, 12) [000036] -----O-N---                         +--*  COMMA     byref  $242
N003 (  6,  9) [000028] -----------                         |  +--*  NOP       void  
N011 (  2,  3) [000035] -----O-----                         |  \--*  ARR_ADDR  byref long[] $2c0
N010 (  2,  3) [000034] -------N---                         |     \--*  ADD       byref  $240
N004 (  1,  1) [000025] -----------                         |        +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N009 (  3,  3) [000033] -------N---                         |        \--*  ADD       long   $1c2
N007 (  2,  2) [000031] -------N---                         |           +--*  LSH       long   $1c1
N005 (  1,  1) [000044] -----------                         |           |  +--*  LCL_VAR   long   V05 cse1         u:1 $1c0
N006 (  1,  1) [000030] -------N---                         |           |  \--*  CNS_INT   long   3 $200
N008 (  1,  1) [000032] -----------                         |           \--*  CNS_INT   long   16 $202
N013 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0 $201

optAssertionPropMain morphed tree:
N010 (  7,  7) [000011] nA--GO-----                         *  STOREIND  long   $146
N008 (  2,  3) [000035] -----O-N---                         +--*  ARR_ADDR  byref long[] $2c0
N007 (  2,  3) [000034] -------N---                         |  \--*  ADD       byref  $240
N001 (  1,  1) [000025] -----------                         |     +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N006 (  3,  3) [000033] -------N---                         |     \--*  ADD       long   $1c2
N004 (  2,  2) [000031] -------N---                         |        +--*  LSH       long   $1c1
N002 (  1,  1) [000044] -----------                         |        |  +--*  LCL_VAR   long   V05 cse1         u:1 $1c0
N003 (  1,  1) [000030] -------N---                         |        |  \--*  CNS_INT   long   3 $200
N005 (  1,  1) [000032] -----------                         |        \--*  CNS_INT   long   16 $202
N009 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0 $201

Propagating #01 #02 for BB01, stmt STMT00002, tree [000012], tree -> #NA

*************** Finishing PHASE Assertion prop
Trees after Assertion prop

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00001 ( 0x005[E-] ... 0x009 )
N010 (  7,  7) [000011] nA--GO-----                         *  STOREIND  long   $146
N008 (  2,  3) [000035] -----O-N---                         +--*  ARR_ADDR  byref long[] $2c0
N007 (  2,  3) [000034] -------N---                         |  \--*  ADD       byref  $240
N001 (  1,  1) [000025] -----------                         |     +--*  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N006 (  3,  3) [000033] -------N---                         |     \--*  ADD       long   $1c2
N004 (  2,  2) [000031] -------N---                         |        +--*  LSH       long   $1c1
N002 (  1,  1) [000044] -----------                         |        |  +--*  LCL_VAR   long   V05 cse1         u:1 $1c0
N003 (  1,  1) [000030] -------N---                         |        |  \--*  CNS_INT   long   3 $200
N005 (  1,  1) [000032] -----------                         |        \--*  CNS_INT   long   16 $202
N009 (  1,  1) [000009] -----------                         \--*  CNS_INT   long   0 $201

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0) [000012] -----------                         *  RETURN    void   $VN.Void

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE VN based intrinsic expansion

*************** Finishing PHASE VN based intrinsic expansion [no changes]

*************** Finishing PHASE Optimize index checks [no changes]

*************** Starting PHASE VN-based dead store removal

*************** Finishing PHASE VN-based dead store removal [no changes]

*************** Starting PHASE Stress gtSplitTree

*************** Finishing PHASE Stress gtSplitTree [no changes]

*************** Starting PHASE Expand runtime lookups

*************** Finishing PHASE Expand runtime lookups [no changes]

*************** Starting PHASE Expand static init
Nothing to expand.

*************** Finishing PHASE Expand static init [no changes]

*************** Starting PHASE Expand TLS access
Nothing to expand.

*************** Finishing PHASE Expand TLS access [no changes]

*************** Starting PHASE Insert GC Polls

*************** Finishing PHASE Insert GC Polls [no changes]

*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()

optimized 0 BBJ_COND cases, 0 BBJ_RETURN cases in 1 passes

*************** Finishing PHASE Optimize bools [no changes]

*************** Starting PHASE If conversion

*************** Finishing PHASE If conversion [no changes]

*************** Starting PHASE Optimize layout

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize layout
Trees after Optimize layout

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x00A[E-] ... 0x00A )
N001 (  0,  0) [000012] -----------                         *  RETURN    void   $VN.Void

*************** Starting PHASE Recognize Switch

*************** Finishing PHASE Recognize Switch [no changes]

*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method

*************** Finishing PHASE Determine first cold block [no changes]

*************** Starting PHASE Rationalize IR

*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}
               [000045] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   int    V01 arg1         u:1 $80
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
                                                            /--*  t0     ref    
N003 (  3,  3) [000015] ---X-------                   t15 = *  ARR_LENGTH int    $180
                                                            /--*  t15    int    
N004 (  3,  3) [000037] DA-X-------                         *  STORE_LCL_VAR int    V04 cse0         d:1 $VN.Void
N005 (  1,  1) [000038] -----------                   t38 =    LCL_VAR   int    V04 cse0         u:1 $180
                                                            /--*  t1     int    
                                                            +--*  t38    int    
N007 (  9, 12) [000016] -A-X-O-----                         *  BOUNDS_CHECK_Rng void   $145
N008 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 $c0
N009 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 $80
                                                            /--*  t14    int    
N010 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint $1c0
                                                            /--*  t17    long   
N011 (  2,  3) [000041] DA---------                         *  STORE_LCL_VAR long   V05 cse1         d:1 $VN.Void
N012 (  1,  1) [000042] -----------                   t42 =    LCL_VAR   long   V05 cse1         u:1 $1c0
N014 (  1,  1) [000018] -------N---                   t18 =    CNS_INT   long   3 $200
                                                            /--*  t42    long   
                                                            +--*  t18    long   
N015 (  4,  5) [000019] -A-----N---                   t19 = *  LSH       long   $1c1
N016 (  1,  1) [000020] -----------                   t20 =    CNS_INT   long   16 $202
                                                            /--*  t19    long   
                                                            +--*  t20    long   
N017 (  5,  6) [000021] -A-----N---                   t21 = *  ADD       long   $1c2
                                                            /--*  t13    ref    
                                                            +--*  t21    long   
N018 (  4,  6) [000022] -A-----N---                   t22 = *  ADD       byref  $240
N021 (  1,  1) [000003] -----------                    t3 =    CNS_INT   long   0 $201
                                                            /--*  t22    byref  
                                                            +--*  t3     long   
N022 ( 18, 22) [000005] nA-XGO-----                         *  STOREIND  long   $145
               [000046] -----------                            IL_OFFSET void   INLRT @ 0x005[E-]
N001 (  1,  1) [000025] -----------                   t25 =    LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N002 (  1,  1) [000044] -----------                   t44 =    LCL_VAR   long   V05 cse1         u:1 $1c0
N003 (  1,  1) [000030] -------N---                   t30 =    CNS_INT   long   3 $200
                                                            /--*  t44    long   
                                                            +--*  t30    long   
N004 (  2,  2) [000031] -------N---                   t31 = *  LSH       long   $1c1
N005 (  1,  1) [000032] -----------                   t32 =    CNS_INT   long   16 $202
                                                            /--*  t31    long   
                                                            +--*  t32    long   
N006 (  3,  3) [000033] -------N---                   t33 = *  ADD       long   $1c2
                                                            /--*  t25    ref    
                                                            +--*  t33    long   
N007 (  2,  3) [000034] -------N---                   t34 = *  ADD       byref  $240
N009 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 $201
                                                            /--*  t34    byref  
                                                            +--*  t9     long   
N010 (  7,  7) [000011] nA--GO-----                         *  STOREIND  long   $146
               [000047] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-]
N001 (  0,  0) [000012] -----------                            RETURN    void   $VN.Void

*************** Starting PHASE Do 'simple' lowering
Lower ARR_LENGTH:
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
                                                            /--*  t0     ref    
N003 (  3,  3) [000015] ---X-------                   t15 = *  ARR_LENGTH int    $180
After Lower IND:
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
               [000048] -----------                   t48 =    CNS_INT   long   8
                                                            /--*  t0     ref    
                                                            +--*  t48    long   
               [000049] -----------                   t49 = *  ADD       byref 
                                                            /--*  t49    byref  
N003 (  3,  3) [000015] ---X-------                   t15 = *  IND       int   
*** Computing fgRngChkTarget for block BB01
fgNewBBinRegion(jumpKind=BBJ_THROW, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=true, insertAtEnd=true): inserting after BB01
New Basic Block BB02 [0001] created.

fgAddCodeRef - Add BB in non-EH region for RNGCHK_FAIL, new block BB02 [0001]
Initializing arg info for 50.CALL:
Args for call [000050] CALL after AddFinalArgsAndDetermineABIInfo:

Morphing args for 50.CALL:
Args for [000050].CALL after fgMorphArgs:
OutgoingArgsStackSize is 32

*************** Finishing PHASE Do 'simple' lowering
Trees after Do 'simple' lowering

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}
               [000045] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   int    V01 arg1         u:1 $80
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
               [000048] -----------                   t48 =    CNS_INT   long   8
                                                            /--*  t0     ref    
                                                            +--*  t48    long   
               [000049] -----------                   t49 = *  ADD       byref 
                                                            /--*  t49    byref  
N003 (  3,  3) [000015] ---X-------                   t15 = *  IND       int   
                                                            /--*  t15    int    
N004 (  3,  3) [000037] DA-X-------                         *  STORE_LCL_VAR int    V04 cse0         d:1 $VN.Void
N005 (  1,  1) [000038] -----------                   t38 =    LCL_VAR   int    V04 cse0         u:1 $180
                                                            /--*  t1     int    
                                                            +--*  t38    int    
N007 (  9, 12) [000016] -A-X-O-----                         *  BOUNDS_CHECK_Rng -> BB02 void   $145
N008 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 $c0
N009 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 $80
                                                            /--*  t14    int    
N010 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint $1c0
                                                            /--*  t17    long   
N011 (  2,  3) [000041] DA---------                         *  STORE_LCL_VAR long   V05 cse1         d:1 $VN.Void
N012 (  1,  1) [000042] -----------                   t42 =    LCL_VAR   long   V05 cse1         u:1 $1c0
N014 (  1,  1) [000018] -------N---                   t18 =    CNS_INT   long   3 $200
                                                            /--*  t42    long   
                                                            +--*  t18    long   
N015 (  4,  5) [000019] -A-----N---                   t19 = *  LSH       long   $1c1
N016 (  1,  1) [000020] -----------                   t20 =    CNS_INT   long   16 $202
                                                            /--*  t19    long   
                                                            +--*  t20    long   
N017 (  5,  6) [000021] -A-----N---                   t21 = *  ADD       long   $1c2
                                                            /--*  t13    ref    
                                                            +--*  t21    long   
N018 (  4,  6) [000022] -A-----N---                   t22 = *  ADD       byref  $240
N021 (  1,  1) [000003] -----------                    t3 =    CNS_INT   long   0 $201
                                                            /--*  t22    byref  
                                                            +--*  t3     long   
N022 ( 18, 22) [000005] nA-XGO-----                         *  STOREIND  long   $145
               [000046] -----------                            IL_OFFSET void   INLRT @ 0x005[E-]
N001 (  1,  1) [000025] -----------                   t25 =    LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N002 (  1,  1) [000044] -----------                   t44 =    LCL_VAR   long   V05 cse1         u:1 $1c0
N003 (  1,  1) [000030] -------N---                   t30 =    CNS_INT   long   3 $200
                                                            /--*  t44    long   
                                                            +--*  t30    long   
N004 (  2,  2) [000031] -------N---                   t31 = *  LSH       long   $1c1
N005 (  1,  1) [000032] -----------                   t32 =    CNS_INT   long   16 $202
                                                            /--*  t31    long   
                                                            +--*  t32    long   
N006 (  3,  3) [000033] -------N---                   t33 = *  ADD       long   $1c2
                                                            /--*  t25    ref    
                                                            +--*  t33    long   
N007 (  2,  3) [000034] -------N---                   t34 = *  ADD       byref  $240
N009 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 $201
                                                            /--*  t34    byref  
                                                            +--*  t9     long   
N010 (  7,  7) [000011] nA--GO-----                         *  STOREIND  long   $146
               [000047] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-]
N001 (  0,  0) [000012] -----------                            RETURN    void   $VN.Void

------------ BB02 [???..???) (throw), preds={} succs={}
N001 ( 14,  5) [000050] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL

*************** Starting PHASE Lowering nodeinfo
Addressing mode:
  Base
    N002 (  1,  1) [000000] -----------                         *  LCL_VAR   ref    V02 arg2         u:1 $c0
  + 8
Removing unused node:
                 [000048] -c---------                         *  CNS_INT   long   8
New addressing mode node:
                 [000049] -----------                         *  LEA(b+8)  byref

lowering store lcl var/field (before):
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
                                                            /--*  t0     ref    
               [000049] -c---------                   t49 = *  LEA(b+8)  byref 
                                                            /--*  t49    byref  
N003 (  3,  3) [000015] ---X-------                   t15 = *  IND       int   
                                                            /--*  t15    int    
N004 (  3,  3) [000037] DA-X-------                         *  STORE_LCL_VAR int    V04 cse0         d:1 $VN.Void

lowering store lcl var/field (after):
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
                                                            /--*  t0     ref    
               [000049] -c---------                   t49 = *  LEA(b+8)  byref 
                                                            /--*  t49    byref  
N003 (  3,  3) [000015] ---X-------                   t15 = *  IND       int   
                                                            /--*  t15    int    
N004 (  3,  3) [000037] DA-X-------                         *  STORE_LCL_VAR int    V04 cse0         d:1 $VN.Void

lowering store lcl var/field (before):
N009 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 $80
                                                            /--*  t14    int    
N010 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint $1c0
                                                            /--*  t17    long   
N011 (  2,  3) [000041] DA---------                         *  STORE_LCL_VAR long   V05 cse1         d:1 $VN.Void

lowering store lcl var/field (after):
N009 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 $80
                                                            /--*  t14    int    
N010 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint $1c0
                                                            /--*  t17    long   
N011 (  2,  3) [000041] DA---------                         *  STORE_LCL_VAR long   V05 cse1         d:1 $VN.Void

Addressing mode:
  Base
    N008 (  1,  1) [000013] -----------                         *  LCL_VAR   ref    V02 arg2         u:1 $c0
  + Index * 8 + 16
    N012 (  1,  1) [000042] -----------                         *  LCL_VAR   long   V05 cse1         u:1 $1c0
Removing unused node:
  N017 (  5,  6) [000021] -A-----N---                         *  ADD       long   $1c2
Removing unused node:
  N016 (  1,  1) [000020] -c---------                         *  CNS_INT   long   16 $202
Removing unused node:
  N015 (  4,  5) [000019] -A-----N---                         *  LSH       long   $1c1
Removing unused node:
  N014 (  1,  1) [000018] -c-----N---                         *  CNS_INT   long   3 $200
New addressing mode node:
  N018 (  4,  6) [000022] -----------                         *  LEA(b+(i*8)+16) byref

Lower of StoreInd didn't mark the node as self contained for reason: oper is not supported
N008 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 $c0
N009 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 $80
                                                            /--*  t14    int    
N010 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint $1c0
                                                            /--*  t17    long   
N011 (  2,  3) [000041] DA---------                         *  STORE_LCL_VAR long   V05 cse1         d:1 $VN.Void
N012 (  1,  1) [000042] -----------                   t42 =    LCL_VAR   long   V05 cse1         u:1 $1c0
                                                            /--*  t13    ref    
                                                            +--*  t42    long   
N018 (  4,  6) [000022] -----------                   t22 = *  LEA(b+(i*8)+16) byref 
N021 (  1,  1) [000003] -----------                    t3 =    CNS_INT   long   0 $201
                                                            /--*  t22    byref  
                                                            +--*  t3     long   
N022 ( 18, 22) [000005] nA-XGO-----                         *  STOREIND  long   $145
Addressing mode:
  Base
    N001 (  1,  1) [000025] -----------                         *  LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
  + Index * 8 + 16
    N002 (  1,  1) [000044] -----------                         *  LCL_VAR   long   V05 cse1         u:1 $1c0
Removing unused node:
  N006 (  3,  3) [000033] -------N---                         *  ADD       long   $1c2
Removing unused node:
  N005 (  1,  1) [000032] -c---------                         *  CNS_INT   long   16 $202
Removing unused node:
  N004 (  2,  2) [000031] -------N---                         *  LSH       long   $1c1
Removing unused node:
  N003 (  1,  1) [000030] -c-----N---                         *  CNS_INT   long   3 $200
New addressing mode node:
  N007 (  2,  3) [000034] -----------                         *  LEA(b+(i*8)+16) byref

Lower of StoreInd didn't mark the node as self contained for reason: oper is not supported
N001 (  1,  1) [000025] -----------                   t25 =    LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N002 (  1,  1) [000044] -----------                   t44 =    LCL_VAR   long   V05 cse1         u:1 $1c0
                                                            /--*  t25    ref    
                                                            +--*  t44    long   
N007 (  2,  3) [000034] -----------                   t34 = *  LEA(b+(i*8)+16) byref 
N009 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 $201
                                                            /--*  t34    byref  
                                                            +--*  t9     long   
N010 (  7,  7) [000011] nA--GO-----                         *  STOREIND  long   $146
lowering GT_RETURN
N001 (  0,  0) [000012] -----------                         *  RETURN    void   $VN.Void
============lowering call (before):
N001 ( 14,  5) [000050] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL

args:
======

late:
======
Bumping outgoing arg space size from 0 to 32 for [000050]
lowering call (after):
N001 ( 14,  5) [000050] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL

Lower has completed modifying nodes.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}
               [000045] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   int    V01 arg1         u:1 $80
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
                                                            /--*  t0     ref    
               [000049] -c---------                   t49 = *  LEA(b+8)  byref 
                                                            /--*  t49    byref  
N003 (  3,  3) [000015] ---X-------                   t15 = *  IND       int   
                                                            /--*  t15    int    
N004 (  3,  3) [000037] DA-X-------                         *  STORE_LCL_VAR int    V04 cse0         d:1 $VN.Void
N005 (  1,  1) [000038] -----------                   t38 =    LCL_VAR   int    V04 cse0         u:1 $180
                                                            /--*  t1     int    
                                                            +--*  t38    int    
N007 (  9, 12) [000016] -A-X-O-----                         *  BOUNDS_CHECK_Rng -> BB02 void   $145
N008 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 $c0
N009 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 $80
                                                            /--*  t14    int    
N010 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint $1c0
                                                            /--*  t17    long   
N011 (  2,  3) [000041] DA---------                         *  STORE_LCL_VAR long   V05 cse1         d:1 $VN.Void
N012 (  1,  1) [000042] -----------                   t42 =    LCL_VAR   long   V05 cse1         u:1 $1c0
                                                            /--*  t13    ref    
                                                            +--*  t42    long   
N018 (  4,  6) [000022] -c---------                   t22 = *  LEA(b+(i*8)+16) byref 
N021 (  1,  1) [000003] -----------                    t3 =    CNS_INT   long   0 $201
                                                            /--*  t22    byref  
                                                            +--*  t3     long   
N022 ( 18, 22) [000005] nA-XGO-----                         *  STOREIND  long   $145
               [000046] -----------                            IL_OFFSET void   INLRT @ 0x005[E-]
N001 (  1,  1) [000025] -----------                   t25 =    LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N002 (  1,  1) [000044] -----------                   t44 =    LCL_VAR   long   V05 cse1         u:1 $1c0
                                                            /--*  t25    ref    
                                                            +--*  t44    long   
N007 (  2,  3) [000034] -c---------                   t34 = *  LEA(b+(i*8)+16) byref 
N009 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 $201
                                                            /--*  t34    byref  
                                                            +--*  t9     long   
N010 (  7,  7) [000011] nA--GO-----                         *  STOREIND  long   $146
               [000047] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-]
N001 (  0,  0) [000012] -----------                            RETURN    void   $VN.Void

------------ BB02 [???..???) (throw), preds={} succs={}
N001 ( 14,  5) [000050] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL

-------------------------------------------------------------------------------------------------------------------

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V01: refCnt =  1, refCntWtd = 1
New refCnts for V02: refCnt =  1, refCntWtd = 1
New refCnts for V04: refCnt =  1, refCntWtd = 1
New refCnts for V04: refCnt =  2, refCntWtd = 2
New refCnts for V02: refCnt =  2, refCntWtd = 2
New refCnts for V01: refCnt =  2, refCntWtd = 2
New refCnts for V05: refCnt =  1, refCntWtd = 1
New refCnts for V05: refCnt =  2, refCntWtd = 2
New refCnts for V02: refCnt =  3, refCntWtd = 3
New refCnts for V05: refCnt =  3, refCntWtd = 3

*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V01: refCnt =  3, refCntWtd = 3
New refCnts for V01: refCnt =  4, refCntWtd = 4
New refCnts for V02: refCnt =  4, refCntWtd = 4
New refCnts for V02: refCnt =  5, refCntWtd = 5
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
;  V00 this              ref  this class-hnd single-def <Program>
;  V01 arg1              int  single-def
;  V02 arg2              ref  class-hnd single-def <long[]>
;  V03 OutArgs        struct <32> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V04 cse0              int  "CSE - aggressive"
;  V05 cse1             long  "CSE - aggressive"
In fgLocalVarLivenessInit

Local V03 should not be enregistered because: struct size does not match reg size
Tracked variable (4 out of 6) table:
V02 arg2          [   ref]: refCnt =    5, refCntWtd =   5   
V01 arg1          [   int]: refCnt =    4, refCntWtd =   4   
V05 cse1          [  long]: refCnt =    3, refCntWtd =   3   
V04 cse0          [   int]: refCnt =    2, refCntWtd =   2

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V02 V01        } + ByrefExposed + GcHeap
     DEF(2)={        V05 V04} + ByrefExposed + GcHeap

BB02 USE(0)={}
     DEF(0)={}

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (2)={V02 V01} + ByrefExposed + GcHeap
     OUT(0)={       }

BB02 IN (0)={}
     OUT(0)={}

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgRemoveDeadBlocks()
New BlockSet epoch 2, # of blocks (including unused BB00): 3, bitset array size: 1 (short)

Removing unreachable blocks for fgRemoveDeadBlocks iteration #1
*************** In fgDebugCheckBBlist

*** lvaComputeRefCounts ***

*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}
               [000045] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   int    V01 arg1         u:1 $80
N002 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 $c0
                                                            /--*  t0     ref    
               [000049] -c---------                   t49 = *  LEA(b+8)  byref 
                                                            /--*  t49    byref  
N003 (  3,  3) [000015] ---X-------                   t15 = *  IND       int   
                                                            /--*  t15    int    
N004 (  3,  3) [000037] DA-X-------                         *  STORE_LCL_VAR int    V04 cse0         d:1 $VN.Void
N005 (  1,  1) [000038] -----------                   t38 =    LCL_VAR   int    V04 cse0         u:1 (last use) $180
                                                            /--*  t1     int    
                                                            +--*  t38    int    
N007 (  9, 12) [000016] -A-X-O-----                         *  BOUNDS_CHECK_Rng -> BB02 void   $145
N008 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 $c0
N009 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 (last use) $80
                                                            /--*  t14    int    
N010 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint $1c0
                                                            /--*  t17    long   
N011 (  2,  3) [000041] DA---------                         *  STORE_LCL_VAR long   V05 cse1         d:1 $VN.Void
N012 (  1,  1) [000042] -----------                   t42 =    LCL_VAR   long   V05 cse1         u:1 $1c0
                                                            /--*  t13    ref    
                                                            +--*  t42    long   
N018 (  4,  6) [000022] -c---------                   t22 = *  LEA(b+(i*8)+16) byref 
N021 (  1,  1) [000003] -----------                    t3 =    CNS_INT   long   0 $201
                                                            /--*  t22    byref  
                                                            +--*  t3     long   
N022 ( 18, 22) [000005] nA-XGO-----                         *  STOREIND  long   $145
               [000046] -----------                            IL_OFFSET void   INLRT @ 0x005[E-]
N001 (  1,  1) [000025] -----------                   t25 =    LCL_VAR   ref    V02 arg2         u:1 (last use) $c0
N002 (  1,  1) [000044] -----------                   t44 =    LCL_VAR   long   V05 cse1         u:1 (last use) $1c0
                                                            /--*  t25    ref    
                                                            +--*  t44    long   
N007 (  2,  3) [000034] -c---------                   t34 = *  LEA(b+(i*8)+16) byref 
N009 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 $201
                                                            /--*  t34    byref  
                                                            +--*  t9     long   
N010 (  7,  7) [000011] nA--GO-----                         *  STOREIND  long   $146
               [000047] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-]
N001 (  0,  0) [000012] -----------                            RETURN    void   $VN.Void

------------ BB02 [???..???) (throw), preds={} succs={}
N001 ( 14,  5) [000050] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL

*************** Starting PHASE Calculate stack level slots

*************** Finishing PHASE Calculate stack level slots [no changes]

*************** Starting PHASE Linear scan register alloc
Clearing modified regs.

buildIntervals ========

-----------------
LIVENESS:
-----------------
BB01
use: {V01 V02}
def: {V04 V05}
 in: {V01 V02}
out: {}
BB02
use: {}
def: {}
 in: {}
out: {}
Interval  0: int RefPositions {} physReg:NA Preferences=[allInt]
  Interval  0: (V01) int RefPositions {} physReg:NA Preferences=[allInt]
Interval  1: ref RefPositions {} physReg:NA Preferences=[allInt]
  Interval  1: (V02) ref RefPositions {} physReg:NA Preferences=[allInt]
Interval  2: int RefPositions {} physReg:NA Preferences=[allInt]
  Interval  2: (V04) int RefPositions {} physReg:NA Preferences=[allInt]
Interval  3: long RefPositions {} physReg:NA Preferences=[allInt]
  Interval  3: (V05) long RefPositions {} physReg:NA Preferences=[allInt]

FP callee save candidate vars: None

BB01 [000..00B) (return), preds={} succs={}
=====
  N000.                    IL_OFFSET INLRT @ 0x000[E-]
  N001.                    V01(t1)
  N002.                    V02(t0)
  N000. t49             =  LEA(b+8) ; t0
  N003. t15             =  IND      ; t49
  N004.                    V04(t37); t15
  N005.                    V04(t38*)
  N007.                    BOUNDS_CHECK_Rng -> BB02; t1,t38*
  N008.                    V02(t13)
  N009.                    V01(t14*)
  N010. t17             =  CAST     ; t14*
  N011.                    V05(t41); t17
  N012.                    V05(t42)
  N018. t22             =  LEA(b+(i*8)+16); t13,t42
  N021. t3              =  CNS_INT   0
  N022.                    STOREIND ; t22,t3
  N000.                    IL_OFFSET INLRT @ 0x005[E-]
  N001.                    V02(t25*)
  N002.                    V05(t44*)
  N007. t34             =  LEA(b+(i*8)+16); t25*,t44*
  N009. t9              =  CNS_INT   0
  N010.                    STOREIND ; t34,t9
  N000.                    IL_OFFSET INLRT @ 0x00A[E-]
  N001.                    RETURN

BB02 [???..???) (throw), preds={} succs={}
=====
  N001.                    CALL help

NEW BLOCK BB01
<RefPosition #2   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N003 (???,???) [000045] -----------                         *  IL_OFFSET void   INLRT @ 0x000[E-] REG NA

DefList: {  }
N005 (  1,  1) [000001] -----------                         *  LCL_VAR   int    V01 arg1         u:1 NA REG NA $80

DefList: {  }
N007 (  1,  1) [000000] -----------                         *  LCL_VAR   ref    V02 arg2         u:1 NA REG NA $c0

DefList: {  }
N009 (???,???) [000049] -c---------                         *  LEA(b+8)  byref  REG NA
Contained
DefList: {  }
N011 (  3,  3) [000015] ---X-------                         *  IND       int    REG NA
<RefPosition #3   @11  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=500.00>
Interval  4: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #4   @12  RefTypeDef <Ivl:4> IND BB01 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N011.t15. IND }
N013 (  3,  3) [000037] DA-X-------                         *  STORE_LCL_VAR int    V04 cse0         d:1 NA REG NA $VN.Void
<RefPosition #5   @13  RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V04/L2> to <I4>
<RefPosition #6   @14  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=200.00>

DefList: {  }
N015 (  1,  1) [000038] -----------                         *  LCL_VAR   int    V04 cse0         u:1 NA (last use) REG NA $180

DefList: {  }
N017 (  9, 12) [000016] -A-X-O-----                         *  BOUNDS_CHECK_Rng -> BB02 void   REG NA $145
<RefPosition #7   @17  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
<RefPosition #8   @17  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=200.00>

DefList: {  }
N019 (  1,  1) [000013] -----------                         *  LCL_VAR   ref    V02 arg2         u:1 NA REG NA $c0

DefList: {  }
N021 (  1,  1) [000014] -----------                         *  LCL_VAR   int    V01 arg1         u:1 NA (last use) REG NA $80

DefList: {  }
N023 (  2,  3) [000017] ---------U-                         *  CAST      long <- uint REG NA $1c0
<RefPosition #9   @23  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
Interval  5: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #10  @24  RefTypeDef <Ivl:5> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N023.t17. CAST }
N025 (  2,  3) [000041] DA---------                         *  STORE_LCL_VAR long   V05 cse1         d:1 NA REG NA $VN.Void
<RefPosition #11  @25  RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V05/L3> to <I5>
<RefPosition #12  @26  RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>

DefList: {  }
N027 (  1,  1) [000042] -----------                         *  LCL_VAR   long   V05 cse1         u:1 NA REG NA $1c0

DefList: {  }
N029 (  4,  6) [000022] -c---------                         *  LEA(b+(i*8)+16) byref  REG NA
Contained
DefList: {  }
N031 (  1,  1) [000003] -----------                         *  CNS_INT   long   0 REG NA $201
Interval  6: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #13  @32  RefTypeDef <Ivl:6> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N031.t3. CNS_INT }
N033 ( 18, 22) [000005] nA-XGO-----                         *  STOREIND  long   REG NA $145
<RefPosition #14  @33  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=500.00>
<RefPosition #15  @33  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
<RefPosition #16  @33  RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last wt=100.00>

DefList: {  }
N035 (???,???) [000046] -----------                         *  IL_OFFSET void   INLRT @ 0x005[E-] REG NA

DefList: {  }
N037 (  1,  1) [000025] -----------                         *  LCL_VAR   ref    V02 arg2         u:1 NA (last use) REG NA $c0

DefList: {  }
N039 (  1,  1) [000044] -----------                         *  LCL_VAR   long   V05 cse1         u:1 NA (last use) REG NA $1c0

DefList: {  }
N041 (  2,  3) [000034] -c---------                         *  LEA(b+(i*8)+16) byref  REG NA
Contained
DefList: {  }
N043 (  1,  1) [000009] -----------                         *  CNS_INT   long   0 REG NA $201
Interval  7: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #17  @44  RefTypeDef <Ivl:7> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N043.t9. CNS_INT }
N045 (  7,  7) [000011] nA--GO-----                         *  STOREIND  long   REG NA $146
<RefPosition #18  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=500.00>
<RefPosition #19  @45  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
<RefPosition #20  @45  RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last wt=100.00>

DefList: {  }
N047 (???,???) [000047] -----------                         *  IL_OFFSET void   INLRT @ 0x00A[E-] REG NA

DefList: {  }
N049 (  0,  0) [000012] -----------                         *  RETURN    void   REG NA $VN.Void

CHECKING LAST USES for BB01, liveout={}
==============================
use: {V01 V02}
def: {V04 V05}

NEW BLOCK BB02

No predecessor;  - throw block; <RefPosition #21  @51  RefTypeBB BB02 regmask=[] minReg=1 wt=0.00>

firstColdLoc = 53
DefList: {  }
N053 ( 14,  5) [000050] --CXG------                         *  CALL help void   CORINFO_HELP_RNGCHKFAIL REG NA
<RefPosition #22  @54  RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 wt=0.00>
<RefPosition #23  @54  RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #24  @54  RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #25  @54  RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 wt=0.00>
<RefPosition #26  @54  RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 wt=0.00>
<RefPosition #27  @54  RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 wt=0.00>
<RefPosition #28  @54  RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 wt=0.00>

CHECKING LAST USES for BB02, liveout={}
==============================
use: {}
def: {}

Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval  0: (V01) int RefPositions {#1@0 #7@17 #9@23} physReg:rdx Preferences=[rdx]
Interval  1: (V02) ref RefPositions {#0@0 #3@11 #14@33 #18@45} physReg:r8 Preferences=[r8]
Interval  2: (V04) int RefPositions {#6@14 #8@17} physReg:NA Preferences=[allInt]
Interval  3: (V05) long RefPositions {#12@26 #15@33 #19@45} physReg:NA Preferences=[allInt]
Interval  4: int RefPositions {#4@12 #5@13} physReg:NA Preferences=[allInt] RelatedInterval <V04/L2>
Interval  5: long RefPositions {#10@24 #11@25} physReg:NA Preferences=[allInt] RelatedInterval <V05/L3>
Interval  6: long (constant) RefPositions {#13@32 #16@33} physReg:NA Preferences=[allInt]
Interval  7: long (constant) RefPositions {#17@44 #20@45} physReg:NA Preferences=[allInt]

------------
REFPOSITIONS BEFORE VALIDATING INTERVALS: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:1 V02> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @0   RefTypeParamDef <Ivl:0 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3   @11  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=500.00>
<RefPosition #4   @12  RefTypeDef <Ivl:4> IND BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #5   @13  RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #6   @14  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=200.00>
<RefPosition #7   @17  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #8   @17  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=200.00>
<RefPosition #9   @23  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=400.00>
<RefPosition #10  @24  RefTypeDef <Ivl:5> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #11  @25  RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #12  @26  RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #13  @32  RefTypeDef <Ivl:6> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #14  @33  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=500.00>
<RefPosition #15  @33  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #16  @33  RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #17  @44  RefTypeDef <Ivl:7> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #18  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=500.00>
<RefPosition #19  @45  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
<RefPosition #20  @45  RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #21  @51  RefTypeBB BB02 regmask=[] minReg=1 wt=0.00>
<RefPosition #22  @54  RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last wt=0.00>
<RefPosition #23  @54  RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last wt=0.00>
<RefPosition #24  @54  RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last wt=0.00>
<RefPosition #25  @54  RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last wt=0.00>
<RefPosition #26  @54  RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last wt=0.00>
<RefPosition #27  @54  RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last wt=0.00>
<RefPosition #28  @54  RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last wt=0.00>

------------
REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval)
------------

-----------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:1 V02> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3   @11  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=500.00>
<RefPosition #14  @33  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=500.00>
<RefPosition #18  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=500.00>
-----------------
<RefPosition #1   @0   RefTypeParamDef <Ivl:0 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #7   @17  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #9   @23  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=400.00>
-----------------
<RefPosition #12  @26  RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #15  @33  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #19  @45  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
-----------------
<RefPosition #6   @14  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=200.00>
<RefPosition #8   @17  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=200.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:  V02 V01
BB01 [000..00B) (return), preds={} succs={}
=====
  N003.                    IL_OFFSET INLRT @ 0x000[E-]
  N005.                    V01(L0)
  N007.                    V02(L1)
  N009.                    LEA(b+8) 
  N011.                    IND      
                               Use:<V02/L1>(#3)
        Def:<I4>(#4) Pref:<V04/L2>
  N013.                    V04(L2)
                               Use:<I4>(#5) *
        Def:<V04/L2>(#6)
  N015.                    V04(L2)
  N017.                    BOUNDS_CHECK_Rng -> BB02
                               Use:<V01/L0>(#7)
                               Use:<V04/L2>(#8) *
  N019.                    V02(L1)
  N021.                    V01(L0)
  N023.                    CAST     
                               Use:<V01/L0>(#9) *
        Def:<I5>(#10) Pref:<V05/L3>
  N025.                    V05(L3)
                               Use:<I5>(#11) *
        Def:<V05/L3>(#12)
  N027.                    V05(L3)
  N029.                    LEA(b+(i*8)+16)
  N031.                    CNS_INT   0
        Def:<I6>(#13)
  N033.                    STOREIND 
                               Use:<V02/L1>(#14)
                               Use:<V05/L3>(#15)
                               Use:<I6>(#16) *
  N035.                    IL_OFFSET INLRT @ 0x005[E-]
  N037.                    V02(L1)
  N039.                    V05(L3)
  N041.                    LEA(b+(i*8)+16)
  N043.                    CNS_INT   0
        Def:<I7>(#17)
  N045.                    STOREIND 
                               Use:<V02/L1>(#18) *
                               Use:<V05/L3>(#19) *
                               Use:<I7>(#20) *
  N047.                    IL_OFFSET INLRT @ 0x00A[E-]
  N049.                    RETURN

BB02 [???..???) (throw), preds={} succs={}
=====
  N053.                    CALL help
        Kill: rax rcx rdx r8 r9 r10 r11

Linear scan intervals after buildIntervals:
Interval  0: (V01) int RefPositions {#1@0 #7@17 #9@23} physReg:rdx Preferences=[rdx]
Interval  1: (V02) ref RefPositions {#0@0 #3@11 #14@33 #18@45} physReg:r8 Preferences=[r8]
Interval  2: (V04) int RefPositions {#6@14 #8@17} physReg:NA Preferences=[allInt]
Interval  3: (V05) long RefPositions {#12@26 #15@33 #19@45} physReg:NA Preferences=[allInt]
Interval  4: int RefPositions {#4@12 #5@13} physReg:NA Preferences=[allInt] RelatedInterval <V04/L2>
Interval  5: long RefPositions {#10@24 #11@25} physReg:NA Preferences=[allInt] RelatedInterval <V05/L3>
Interval  6: long (constant) RefPositions {#13@32 #16@33} physReg:NA Preferences=[allInt]
Interval  7: long (constant) RefPositions {#17@44 #20@45} physReg:NA Preferences=[allInt]

*************** In LinearScan::allocateRegisters()

Linear scan intervals before allocateRegisters:
Interval  0: (V01) int RefPositions {#1@0 #7@17 #9@23} physReg:rdx Preferences=[rdx]
Interval  1: (V02) ref RefPositions {#0@0 #3@11 #14@33 #18@45} physReg:r8 Preferences=[r8]
Interval  2: (V04) int RefPositions {#6@14 #8@17} physReg:NA Preferences=[allInt]
Interval  3: (V05) long RefPositions {#12@26 #15@33 #19@45} physReg:NA Preferences=[allInt]
Interval  4: int RefPositions {#4@12 #5@13} physReg:NA Preferences=[allInt] RelatedInterval <V04/L2>
Interval  5: long RefPositions {#10@24 #11@25} physReg:NA Preferences=[allInt] RelatedInterval <V05/L3>
Interval  6: long (constant) RefPositions {#13@32 #16@33} physReg:NA Preferences=[allInt]
Interval  7: long (constant) RefPositions {#17@44 #20@45} physReg:NA Preferences=[allInt]

------------
REFPOSITIONS BEFORE ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:1 V02> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @0   RefTypeParamDef <Ivl:0 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3   @11  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=500.00>
<RefPosition #4   @12  RefTypeDef <Ivl:4> IND BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #5   @13  RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #6   @14  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=200.00>
<RefPosition #7   @17  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #8   @17  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=200.00>
<RefPosition #9   @23  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=400.00>
<RefPosition #10  @24  RefTypeDef <Ivl:5> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #11  @25  RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #12  @26  RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #13  @32  RefTypeDef <Ivl:6> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #14  @33  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=500.00>
<RefPosition #15  @33  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #16  @33  RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #17  @44  RefTypeDef <Ivl:7> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #18  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=500.00>
<RefPosition #19  @45  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
<RefPosition #20  @45  RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #21  @51  RefTypeBB BB02 regmask=[] minReg=1 wt=0.00>
<RefPosition #22  @54  RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last wt=0.00>
<RefPosition #23  @54  RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last wt=0.00>
<RefPosition #24  @54  RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last wt=0.00>
<RefPosition #25  @54  RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last wt=0.00>
<RefPosition #26  @54  RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last wt=0.00>
<RefPosition #27  @54  RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last wt=0.00>
<RefPosition #28  @54  RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last wt=0.00>

VAR REFPOSITIONS BEFORE ALLOCATION
--- V00
--- V01  (Interval 0)
<RefPosition #1   @0   RefTypeParamDef <Ivl:0 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #7   @17  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #9   @23  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=400.00>
--- V02  (Interval 1)
<RefPosition #0   @0   RefTypeParamDef <Ivl:1 V02> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3   @11  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=500.00>
<RefPosition #14  @33  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=500.00>
<RefPosition #18  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=500.00>
--- V03
--- V04  (Interval 2)
<RefPosition #6   @14  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=200.00>
<RefPosition #8   @17  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=200.00>
--- V05  (Interval 3)
<RefPosition #12  @26  RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #15  @33  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #19  @45  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>

------------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------------------+----+----+----+----+----+----+----+----+----+
                                          |    |    |V01a|    |    |    |    |V02a|    |
          0.#0  V02  Parm   Keep     r8   |    |    |V01a|    |    |    |    |V02a|    |
          0.#1  V01  Parm   Keep     rdx  |    |    |V01a|    |    |    |    |V02a|    |
          1.#2  BB1 PredBB0               |    |    |V01a|    |    |    |    |V02a|    |
[000015] 11.#3  V02  Use    Keep     r8   |    |    |V01a|    |    |    |    |V02a|    |
         12.#4  I4   Def    ORDER(A) rax  |I4 a|    |V01a|    |    |    |    |V02a|    |
[000037] 13.#5  I4   Use *  Keep     rax  |I4 a|    |V01a|    |    |    |    |V02a|    |
         14.#6  V04  Def    COVRS(A) rax  |V04a|    |V01a|    |    |    |    |V02a|    |
[000016] 17.#7  V01  Use    Keep     rdx  |V04a|    |V01a|    |    |    |    |V02a|    |
         17.#8  V04  Use *  Keep     rax  |V04a|    |V01a|    |    |    |    |V02a|    |
[000017] 23.#9  V01  Use *  Keep     rdx  |    |    |V01a|    |    |    |    |V02a|    |
         24.#10 I5   Def    ORDER(A) rax  |I5 a|    |    |    |    |    |    |V02a|    |
[000041] 25.#11 I5   Use *  Keep     rax  |I5 a|    |    |    |    |    |    |V02a|    |
         26.#12 V05  Def    COVRS(A) rax  |V05a|    |    |    |    |    |    |V02a|    |
[000003] 32.#13 C6   Def    ORDER(A) rcx  |V05a|C6 a|    |    |    |    |    |V02a|    |
[000005] 33.#14 V02  Use    Keep     r8   |V05a|C6 a|    |    |    |    |    |V02a|    |
         33.#15 V05  Use    Keep     rax  |V05a|C6 a|    |    |    |    |    |V02a|    |
         33.#16 C6   Use *  Keep     rcx  |V05a|C6 a|    |    |    |    |    |V02a|    |
[000009] 44.#17 C7   Def    CONST(R) rcx  |V05a|C7 a|    |    |    |    |    |V02a|    |
[000011] 45.#18 V02  Use *  Keep     r8   |V05a|C7 a|    |    |    |    |    |V02a|    |
         45.#19 V05  Use *  Keep     rax  |V05a|C7 a|    |    |    |    |    |V02a|    |
         45.#20 C7   Use *  Keep     rcx  |V05a|C7 a|    |    |    |    |    |V02a|    |
------------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------------------+----+----+----+----+----+----+----+----+----+
         51.#21 BB2 PredBB0               |    |    |    |    |    |    |    |    |    |
[000050] 54.#22 rax  Kill   Keep     rax  |    |    |    |    |    |    |    |    |    |
         54.#23 rcx  Kill   Keep     rcx  |    |    |    |    |    |    |    |    |    |
         54.#24 rdx  Kill   Keep     rdx  |    |    |    |    |    |    |    |    |    |
         54.#25 r8   Kill   Keep     r8   |    |    |    |    |    |    |    |    |    |
         54.#26 r9   Kill   Keep     r9   |    |    |    |    |    |    |    |    |    |
         54.#27 r10  Kill   Keep     r10  |    |    |    |    |    |    |    |    |    |
         54.#28 r11  Kill   Keep     r11  |    |    |    |    |    |    |    |    |    |

------------
REFPOSITIONS AFTER ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:1 V02> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @0   RefTypeParamDef <Ivl:0 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3   @11  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[r8] minReg=1 wt=500.00>
<RefPosition #4   @12  RefTypeDef <Ivl:4> IND BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #5   @13  RefTypeUse <Ivl:4> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #6   @14  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 wt=200.00>
<RefPosition #7   @17  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #8   @17  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[rax] minReg=1 last regOptional wt=200.00>
<RefPosition #9   @23  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 last regOptional wt=400.00>
<RefPosition #10  @24  RefTypeDef <Ivl:5> CAST BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #11  @25  RefTypeUse <Ivl:5> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #12  @26  RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #13  @32  RefTypeDef <Ivl:6> CNS_INT BB01 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #14  @33  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[r8] minReg=1 wt=500.00>
<RefPosition #15  @33  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #16  @33  RefTypeUse <Ivl:6> BB01 regmask=[rcx] minReg=1 last wt=100.00>
<RefPosition #17  @44  RefTypeDef <Ivl:7> CNS_INT BB01 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #18  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[r8] minReg=1 last wt=500.00>
<RefPosition #19  @45  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[rax] minReg=1 last wt=300.00>
<RefPosition #20  @45  RefTypeUse <Ivl:7> BB01 regmask=[rcx] minReg=1 last wt=100.00>
<RefPosition #21  @51  RefTypeBB BB02 regmask=[] minReg=1 wt=0.00>
<RefPosition #22  @54  RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last wt=0.00>
<RefPosition #23  @54  RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last wt=0.00>
<RefPosition #24  @54  RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last wt=0.00>
<RefPosition #25  @54  RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last wt=0.00>
<RefPosition #26  @54  RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last wt=0.00>
<RefPosition #27  @54  RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last wt=0.00>
<RefPosition #28  @54  RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last wt=0.00>

VAR REFPOSITIONS AFTER ALLOCATION
--- V00
--- V01  (Interval 0)
<RefPosition #1   @0   RefTypeParamDef <Ivl:0 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #7   @17  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #9   @23  RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 last regOptional wt=400.00>
--- V02  (Interval 1)
<RefPosition #0   @0   RefTypeParamDef <Ivl:1 V02> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3   @11  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[r8] minReg=1 wt=500.00>
<RefPosition #14  @33  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[r8] minReg=1 wt=500.00>
<RefPosition #18  @45  RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[r8] minReg=1 last wt=500.00>
--- V03
--- V04  (Interval 2)
<RefPosition #6   @14  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 wt=200.00>
<RefPosition #8   @17  RefTypeUse <Ivl:2 V04> LCL_VAR BB01 regmask=[rax] minReg=1 last regOptional wt=200.00>
--- V05  (Interval 3)
<RefPosition #12  @26  RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #15  @33  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #19  @45  RefTypeUse <Ivl:3 V05> LCL_VAR BB01 regmask=[rax] minReg=1 last wt=300.00>

Active intervals at end of allocation:

-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V01 V02}
Has No Critical Edges

Prior to Resolution

BB01
use: {V01 V02}
def: {V04 V05}
 in: {V01 V02}
out: {}
Var=Reg beg of BB01: V02=r8 V01=rdx 
Var=Reg end of BB01: none

BB02
use: {}
def: {}
 in: {}
out: {}
Var=Reg beg of BB02: none
Var=Reg end of BB02: none

RESOLVING EDGES
  Set V01 argument initial register to rdx
  Set V02 argument initial register to r8
Trees after linear scan register allocator (LSRA)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00B) (return), preds={} succs={}
N003 (???,???) [000045] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
N005 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   int    V01 arg1         u:1 rdx REG rdx $80
N007 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 r8 REG r8 $c0
                                                            /--*  t0     ref    
N009 (???,???) [000049] -c---------                   t49 = *  LEA(b+8)  byref  REG NA
                                                            /--*  t49    byref  
N011 (  3,  3) [000015] ---X-------                   t15 = *  IND       int    REG rax
                                                            /--*  t15    int    
N013 (  3,  3) [000037] DA-X-------                         *  STORE_LCL_VAR int    V04 cse0         d:1 rax REG rax $VN.Void
N015 (  1,  1) [000038] -----------                   t38 =    LCL_VAR   int    V04 cse0         u:1 rax (last use) REG rax $180
                                                            /--*  t1     int    
                                                            +--*  t38    int    
N017 (  9, 12) [000016] -A-X-O-----                         *  BOUNDS_CHECK_Rng -> BB02 void   REG NA $145
N019 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 r8 REG r8 $c0
N021 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 rdx (last use) REG rdx $80
                                                            /--*  t14    int    
N023 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint REG rax $1c0
                                                            /--*  t17    long   
N025 (  2,  3) [000041] DA---------                         *  STORE_LCL_VAR long   V05 cse1         d:1 rax REG rax $VN.Void
N027 (  1,  1) [000042] -----------                   t42 =    LCL_VAR   long   V05 cse1         u:1 rax REG rax $1c0
                                                            /--*  t13    ref    
                                                            +--*  t42    long   
N029 (  4,  6) [000022] -c---------                   t22 = *  LEA(b+(i*8)+16) byref  REG NA
N031 (  1,  1) [000003] -----------                    t3 =    CNS_INT   long   0 REG rcx $201
                                                            /--*  t22    byref  
                                                            +--*  t3     long   
N033 ( 18, 22) [000005] nA-XGO-----                         *  STOREIND  long   REG NA $145
N035 (???,???) [000046] -----------                            IL_OFFSET void   INLRT @ 0x005[E-] REG NA
N037 (  1,  1) [000025] -----------                   t25 =    LCL_VAR   ref    V02 arg2         u:1 r8 (last use) REG r8 $c0
N039 (  1,  1) [000044] -----------                   t44 =    LCL_VAR   long   V05 cse1         u:1 rax (last use) REG rax $1c0
                                                            /--*  t25    ref    
                                                            +--*  t44    long   
N041 (  2,  3) [000034] -c---------                   t34 = *  LEA(b+(i*8)+16) byref  REG NA
N043 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 reuse reg val REG rcx $201
                                                            /--*  t34    byref  
                                                            +--*  t9     long   
N045 (  7,  7) [000011] nA--GO-----                         *  STOREIND  long   REG NA $146
N047 (???,???) [000047] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-] REG NA
N049 (  0,  0) [000012] -----------                            RETURN    void   REG NA $VN.Void

------------ BB02 [???..???) (throw), preds={} succs={}
N053 ( 14,  5) [000050] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL REG NA

-------------------------------------------------------------------------------------------------------------------

Final allocation
------------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------------------+----+----+----+----+----+----+----+----+----+
          0.#0  V02  Parm   Alloc    r8   |    |    |    |    |    |    |    |V02a|    |
          0.#1  V01  Parm   Alloc    rdx  |    |    |V01a|    |    |    |    |V02a|    |
          1.#2  BB1 PredBB0               |    |    |V01a|    |    |    |    |V02a|    |
[000015] 11.#3  V02  Use    Keep     r8   |    |    |V01a|    |    |    |    |V02a|    |
         12.#4  I4   Def    Alloc    rax  |I4 a|    |V01a|    |    |    |    |V02a|    |
[000037] 13.#5  I4   Use *  Keep     rax  |I4 i|    |V01a|    |    |    |    |V02a|    |
         14.#6  V04  Def    Alloc    rax  |V04a|    |V01a|    |    |    |    |V02a|    |
[000016] 17.#7  V01  Use    Keep     rdx  |V04a|    |V01a|    |    |    |    |V02a|    |
         17.#8  V04  Use *  Keep     rax  |V04i|    |V01a|    |    |    |    |V02a|    |
[000017] 23.#9  V01  Use *  Keep     rdx  |    |    |V01i|    |    |    |    |V02a|    |
         24.#10 I5   Def    Alloc    rax  |I5 a|    |    |    |    |    |    |V02a|    |
[000041] 25.#11 I5   Use *  Keep     rax  |I5 i|    |    |    |    |    |    |V02a|    |
         26.#12 V05  Def    Alloc    rax  |V05a|    |    |    |    |    |    |V02a|    |
[000003] 32.#13 C6   Def    Alloc    rcx  |V05a|C6 a|    |    |    |    |    |V02a|    |
[000005] 33.#14 V02  Use    Keep     r8   |V05a|C6 a|    |    |    |    |    |V02a|    |
         33.#15 V05  Use    Keep     rax  |V05a|C6 a|    |    |    |    |    |V02a|    |
         33.#16 C6   Use *  Keep     rcx  |V05a|C6 i|    |    |    |    |    |V02a|    |
[000009] 44.#17 C7   Def    Reuse    rcx  |V05a|C7 a|    |    |    |    |    |V02a|    |
[000011] 45.#18 V02  Use *  Keep     r8   |V05a|C7 a|    |    |    |    |    |V02i|    |
         45.#19 V05  Use *  Keep     rax  |V05i|C7 a|    |    |    |    |    |    |    |
         45.#20 C7   Use *  Keep     rcx  |    |C7 i|    |    |    |    |    |    |    |
------------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------------------+----+----+----+----+----+----+----+----+----+
         51.#21 BB2 PredBB0               |    |    |    |    |    |    |    |    |    |
[000050] 54.#22 rax  Kill   Keep     rax  |    |    |    |    |    |    |    |    |    |
         54.#23 rcx  Kill   Keep     rcx  |    |    |    |    |    |    |    |    |    |
         54.#24 rdx  Kill   Keep     rdx  |    |    |    |    |    |    |    |    |    |
         54.#25 r8   Kill   Keep     r8   |    |    |    |    |    |    |    |    |    |
         54.#26 r9   Kill   Keep     r9   |    |    |    |    |    |    |    |    |    |
         54.#27 r10  Kill   Keep     r10  |    |    |    |    |    |    |    |    |    |
         54.#28 r11  Kill   Keep     r11  |    |    |    |    |    |    |    |    |    |

Recording the maximum number of concurrent spills:

----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars:  4
Total Reg Cand Vars: 4
Total number of Intervals: 7
Total number of RefPositions: 28
Total Number of spill temps created: 0
..........
BB01 [  100.00]: CONST_AVAILABLE = 1, COVERS = 2, REG_ORDER = 3
..........
Total SpillCount : 0   Weighted: 0.000000
Total CopyReg : 0   Weighted: 0.000000
Total ResolutionMovs : 0   Weighted: 0.000000
Total SplitEdges : 0   Weighted: 0.000000
..........
Total CONST_AVAILABLE [# 2] : 1   Weighted: 100.000000
Total COVERS [# 4] : 2   Weighted: 200.000000
Total REG_ORDER [#13] : 3   Weighted: 300.000000

TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:  V02(r8) V01(rdx)
BB01 [000..00B) (return), preds={} succs={}
=====
  N003.                    IL_OFFSET INLRT @ 0x000[E-]
  N005.                    V01(rdx)
  N007.                    V02(r8)
  N009. STK             =  LEA(b+8) ; r8
  N011. rax             =  IND      ; STK
* N013.                    V04(rax); rax
  N015.                    V04(rax*)
  N017.                    BOUNDS_CHECK_Rng -> BB02; rdx,rax*
  N019.                    V02(r8)
  N021.                    V01(rdx*)
  N023. rax             =  CAST     ; rdx*
* N025.                    V05(rax); rax
  N027.                    V05(rax)
  N029. STK             =  LEA(b+(i*8)+16); r8,rax
  N031. rcx             =  CNS_INT   0
  N033.                    STOREIND ; STK,rcx
  N035.                    IL_OFFSET INLRT @ 0x005[E-]
  N037.                    V02(r8*)
  N039.                    V05(rax*)
  N041. STK             =  LEA(b+(i*8)+16); r8*,rax*
  N043. rcx             =  CNS_INT   0 reuse reg val
  N045.                    STOREIND ; STK,rcx
  N047.                    IL_OFFSET INLRT @ 0x00A[E-]
  N049.                    RETURN   
Var=Reg end of BB01: none

BB02 [???..???) (throw), preds={} succs={}
=====
Predecessor for variable locations: BB00
Var=Reg beg of BB02: none
  N053.                    CALL help
Var=Reg end of BB02: none

*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB02 [???..???) (throw), preds={} succs={}
N053 ( 14,  5) [000050] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL REG NA

*************** Starting PHASE Place 'align' instructions

*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
  V02(r8)  V01(rdx)
Modified regs: [rax rcx rdx r8-r11]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V03 OutArgs, size=32, stkOffs=-0x28
--- delta bump 8 for RA
--- delta bump 40 for RSP frame
--- virtual stack offset to actual stack offset delta is 48
-- V00 was 0, now 48
-- V01 was 8, now 56
-- V02 was 16, now 64
-- V03 was -40, now 8
; Final local variable assignments
;
;* V00 this         [V00    ] (  0,  0   )     ref  ->  zero-ref    this class-hnd single-def <Program>
;  V01 arg1         [V01,T01] (  4,  4   )     int  ->  rdx         single-def
;  V02 arg2         [V02,T00] (  5,  5   )     ref  ->   r8         class-hnd single-def <long[]>
;  V03 OutArgs      [V03    ] (  1,  1   )  struct (32) [rsp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V04 cse0         [V04,T03] (  2,  2   )     int  ->  rax         "CSE - aggressive"
;  V05 cse1         [V05,T02] (  3,  3   )    long  ->  rax         "CSE - aggressive"
;
; Lcl frame size = 40
Created:
      G_M62796_IG02:        ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
  BB01 : first block
  BB02 : throw helper block
*************** After genMarkLabelsForCodegen()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..00B)        (return)                     i label idxlen LIR 
BB02 [0001]  0                             0       [???..???)        (throw )                     keep i internal rare label LIR 
-----------------------------------------------------------------------------------------------------------------------------------------
Setting stack level from -572662307 to 0

=============== Generating BB01 [000..00B) (return), preds={} succs={} flags=0x00000000.00420011: i label idxlen LIR 
BB01 IN (2)={V02 V01} + ByrefExposed + GcHeap
     OUT(0)={       }

L_M62796_BB01:
Label: G_M62796_IG02, GCvars=0000000000000000 {}, gcrefRegs=0100 {r8}, byrefRegs=0000 {}

Scope info: begin block BB01, IL range [000..00B)
Added IP mapping: 0x0000 STACK_EMPTY (G_M62796_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000045] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
Generating: N005 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   int    V01 arg1         u:1 rdx REG rdx $80
Generating: N007 (  1,  1) [000000] -----------                    t0 =    LCL_VAR   ref    V02 arg2         u:1 r8 REG r8 $c0
                                                                        /--*  t0     ref    
Generating: N009 (???,???) [000049] -c---------                   t49 = *  LEA(b+8)  byref  REG NA
                                                                        /--*  t49    byref  
Generating: N011 (  3,  3) [000015] ---X-------                   t15 = *  IND       int    REG rax
Mapped BB01 to G_M62796_IG02
IN0001:        mov      eax, dword ptr [r8+0x08]
                                                                        /--*  t15    int    
Generating: N013 (  3,  3) [000037] DA-X-------                         *  STORE_LCL_VAR int    V04 cse0         d:1 rax REG rax $VN.Void
							V04 in reg rax is becoming live  [000037]
							Live regs: 0000000000000104 {rdx r8} + {rax} => 0000000000000105 {rax rdx r8}
							Live vars after [000037]: {V01 V02} +{V04} => {V01 V02 V04}
Generating: N015 (  1,  1) [000038] -----------                   t38 =    LCL_VAR   int    V04 cse0         u:1 rax (last use) REG rax $180
                                                                        /--*  t1     int    
                                                                        +--*  t38    int    
Generating: N017 (  9, 12) [000016] -A-X-O-----                         *  BOUNDS_CHECK_Rng -> BB02 void   REG NA $145
							V04 in reg rax is becoming dead  [000038]
							Live regs: 0000000000000105 {rax rdx r8} - {rax} => 0000000000000104 {rdx r8}
							Live vars after [000038]: {V01 V02 V04} -{V04} => {V01 V02}
IN0002:        cmp      edx, eax
IN0003:        jae      L_M62796_BB02
Generating: N019 (  1,  1) [000013] -----------                   t13 =    LCL_VAR   ref    V02 arg2         u:1 r8 REG r8 $c0
Generating: N021 (  1,  1) [000014] -----------                   t14 =    LCL_VAR   int    V01 arg1         u:1 rdx (last use) REG rdx $80
                                                                        /--*  t14    int    
Generating: N023 (  2,  3) [000017] ---------U-                   t17 = *  CAST      long <- uint REG rax $1c0
							V01 in reg rdx is becoming dead  [000014]
							Live regs: 0000000000000104 {rdx r8} - {rdx} => 0000000000000100 {r8}
Debug: Closing V01 debug range.
							Live vars after [000014]: {V01 V02} -{V01} => {V02}
IN0004:        mov      eax, edx
                                                                        /--*  t17    long   
Generating: N025 (  2,  3) [000041] DA---------                         *  STORE_LCL_VAR long   V05 cse1         d:1 rax REG rax $VN.Void
							V05 in reg rax is becoming live  [000041]
							Live regs: 0000000000000100 {r8} + {rax} => 0000000000000101 {rax r8}
							Live vars after [000041]: {V02} +{V05} => {V02 V05}
Generating: N027 (  1,  1) [000042] -----------                   t42 =    LCL_VAR   long   V05 cse1         u:1 rax REG rax $1c0
                                                                        /--*  t13    ref    
                                                                        +--*  t42    long   
Generating: N029 (  4,  6) [000022] -c---------                   t22 = *  LEA(b+(i*8)+16) byref  REG NA
Generating: N031 (  1,  1) [000003] -----------                    t3 =    CNS_INT   long   0 REG rcx $201
IN0005:        xor      rcx, rcx
                                                                        /--*  t22    byref  
                                                                        +--*  t3     long   
Generating: N033 ( 18, 22) [000005] nA-XGO-----                         *  STOREIND  long   REG NA $145
IN0006:        mov      qword ptr [r8+8*rax+0x10], rcx
Added IP mapping: 0x0005 STACK_EMPTY (G_M62796_IG02,ins#6,ofs#21)
Generating: N035 (???,???) [000046] -----------                            IL_OFFSET void   INLRT @ 0x005[E-] REG NA
Generating: N037 (  1,  1) [000025] -----------                   t25 =    LCL_VAR   ref    V02 arg2         u:1 r8 (last use) REG r8 $c0
Generating: N039 (  1,  1) [000044] -----------                   t44 =    LCL_VAR   long   V05 cse1         u:1 rax (last use) REG rax $1c0
                                                                        /--*  t25    ref    
                                                                        +--*  t44    long   
Generating: N041 (  2,  3) [000034] -c---------                   t34 = *  LEA(b+(i*8)+16) byref  REG NA
Generating: N043 (  1,  1) [000009] -----------                    t9 =    CNS_INT   long   0 reuse reg val REG rcx $201
  TreeNode is marked ReuseReg
New Basic Block BB03 [0002] created.
Mark BB03 as label: codegen temp block

L_M62796_BB03:
Saved:
      G_M62796_IG02:        ; offs=0x000000, size=0x0015, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
Created:
      G_M62796_IG03:        ; offs=0x000015, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Label: G_M62796_IG03, GCvars=0000000000000000 {}, gcrefRegs=0100 {r8}, byrefRegs=0000 {}
                                                                        /--*  t34    byref  
                                                                        +--*  t9     long   
Generating: N045 (  7,  7) [000011] nA--GO-----                         *  STOREIND  long   REG NA $146
							V02 in reg r8 is becoming dead  [000025]
							Live regs: 0000000000000101 {rax r8} - {r8} => 0000000000000001 {rax}
Debug: Closing V02 debug range.
							Live vars after [000025]: {V02 V05} -{V02} => {V05}
							GC regs: 0100 {r8} => 0000 {}
							V05 in reg rax is becoming dead  [000044]
							Live regs: 0000000000000001 {rax} - {rax} => 0000000000000000 {}
							Live vars after [000044]: {V05} -{V05} => {}
Mapped BB01 to G_M62796_IG03
IN0007:        mov      qword ptr [r8+8*rax+0x10], rcx
Added IP mapping: 0x000A STACK_EMPTY (G_M62796_IG03,ins#1,ofs#5)
Generating: N047 (???,???) [000047] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-] REG NA
Generating: N049 (  0,  0) [000012] -----------                            RETURN    void   REG NA $VN.Void
Added IP mapping: EPILOG (G_M62796_IG03,ins#1,ofs#5) label
Reserving epilog IG for block BB01
Saved:
      G_M62796_IG03:        ; offs=0x000015, size=0x0005, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
Created:
      G_M62796_IG04:        ; offs=0x00001A, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Created:
      G_M62796_IG05:        ; offs=0x00011A, size=0x0000, bbWeight=1, gcrefRegs=0000 {}, epilog
*************** After placeholder IG creation
G_M62796_IG01:        ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M62796_IG02:        ; offs=0x000000, size=0x0015, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
G_M62796_IG03:        ; offs=0x000015, size=0x0005, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
G_M62796_IG04:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0100 {r8}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0100 {r8}, InitByrefRegs=0000 {}
G_M62796_IG05:        ; offs=0x00011A, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Current IG

Variable Live Range History Dump for BB01
V01 arg1: rdx [(G_M62796_IG02,ins#0,ofs#0), (G_M62796_IG02,ins#3,ofs#12)]
V02 arg2: r8 [(G_M62796_IG02,ins#0,ofs#0), (G_M62796_IG03,ins#0,ofs#0)]

=============== Generating BB02 [???..???) (throw), preds={} succs={} flags=0x00000000.00022039: keep i internal rare label LIR 
BB02 IN (0)={}
     OUT(0)={}

Recording Var Locations at start of BB02
  <none>

Liveness not changing: 0000000000000000 {}
							Live regs: (unchanged) 0000000000000000 {}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 0000 {}

L_M62796_BB02:
Label: G_M62796_IG05, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}

Scope info: begin block BB02, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP (G_M62796_IG05,ins#0,ofs#0) label
Generating: N053 ( 14,  5) [000050] --CXG------                            CALL help void   CORINFO_HELP_RNGCHKFAIL REG NA
							Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Mapped BB02 to G_M62796_IG05
IN0008:        call     CORINFO_HELP_RNGCHKFAIL
Scope info: ignoring block end
IN0009:        int3

Variable Live Range History Dump for BB02
..None..
Liveness not changing: 0000000000000000 {}

# compCycleEstimate =     25, compSizeEstimate =    29 Program:Test(int,long[]):this
; Final local variable assignments
;
;* V00 this         [V00    ] (  0,  0   )     ref  ->  zero-ref    this class-hnd single-def <Program>
;  V01 arg1         [V01,T01] (  4,  4   )     int  ->  rdx         single-def
;  V02 arg2         [V02,T00] (  5,  5   )     ref  ->   r8         class-hnd single-def <long[]>
;  V03 OutArgs      [V03    ] (  1,  1   )  struct (32) [rsp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V04 cse0         [V04,T03] (  2,  2   )     int  ->  rax         "CSE - aggressive"
;  V05 cse1         [V05,T02] (  3,  3   )    long  ->  rax         "CSE - aggressive"
;
; Lcl frame size = 40
*************** Before prolog / epilog generation
G_M62796_IG01:        ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M62796_IG02:        ; offs=0x000000, size=0x0015, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
G_M62796_IG03:        ; offs=0x000015, size=0x0005, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
G_M62796_IG04:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0100 {r8}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0100 {r8}, InitByrefRegs=0000 {}
G_M62796_IG05:        ; offs=0x00011A, size=0x0000, bbWeight=0, gcrefRegs=0000 {}, BB02 [0001] <-- Current IG
Recording Var Locations at start of BB01
  V02(r8)  V01(rdx)
Saved:
      G_M62796_IG05:        ; offs=0x00011A, size=0x0006, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], gcvars, byref
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M62796_IG01,ins#0,ofs#0) label

__prolog:
Debug: New V00 debug range: first
Debug: New V01 debug range: first
Debug: New V02 debug range: first
IN000a:        sub      rsp, 40
*************** In genFnPrologCalleeRegArgs() for int regs
*************** In genEnregisterIncomingStackArgs()
Debug: Closing V00 debug range.
Debug: Closing V01 debug range.
Debug: Closing V02 debug range.

Saved:
      G_M62796_IG01:        ; offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc
*************** In genFnEpilog()

__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0100 {r8}, gcRegByrefSetCur=0000 {}
IN000b:        add      rsp, 40
IN000c:        ret      
Saved:
      G_M62796_IG04:        ; offs=0x00001A, size=0x0005, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M62796_IG01:        ; func=00, offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M62796_IG02:        ; offs=0x000004, size=0x0015, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
G_M62796_IG03:        ; offs=0x000019, size=0x0005, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
G_M62796_IG04:        ; offs=0x00001E, size=0x0005, bbWeight=1, epilog, nogc, extend
G_M62796_IG05:        ; offs=0x000023, size=0x0006, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], gcvars, byref
*************** In emitJumpDistBind()
Emitter Jump List:
IG02 IN0003 jae[6] -> IG05
  total jump count: 1
Binding: IN0003: 000000 jae      L_M62796_BB02
Binding L_M62796_BB02 to G_M62796_IG05
Estimate of fwd jump [D1FFAB1E/003]: 000A -> 0023 = 0017
Shrinking jump [D1FFAB1E/003]
Adjusted offset of BB03 from 0019 to 0015
Adjusted offset of BB04 from 001E to 001A
Adjusted offset of BB05 from 0023 to 001F
Total shrinkage =   4, min extra jump size = 4294967295

*************** Finishing PHASE Generate code

*************** Starting PHASE Emit code

Hot  code size = 0x25 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x6)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)

***************************************************************************
Instructions as they come out of the scheduler

G_M62796_IG01:        ; offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN000a: 000000 sub      rsp, 40
						;; size=4 bbWeight=1 PerfScore 0.25
G_M62796_IG02:        ; offs=0x000004, size=0x0011, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref, isz
       ; gcrRegs +[r8]
IN0001: 000004 mov      eax, dword ptr [r8+0x08]
IN0002: 000008 cmp      edx, eax
IN0003: 00000A jae      SHORT G_M62796_IG05
IN0004: 00000C mov      eax, edx
IN0005: 00000E xor      ecx, ecx
IN0006: 000010 mov      qword ptr [r8+8*rax+0x10], rcx
						;; size=17 bbWeight=1 PerfScore 4.75
G_M62796_IG03:        ; offs=0x000015, size=0x0005, bbWeight=1, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref
IN0007: 000015 mov      qword ptr [r8+8*rax+0x10], rcx
						;; size=5 bbWeight=1 PerfScore 1.00
G_M62796_IG04:        ; offs=0x00001A, size=0x0005, bbWeight=1, epilog, nogc, extend
IN000b: 00001A add      rsp, 40
IN000c: 00001E ret      
						;; size=5 bbWeight=1 PerfScore 1.25
G_M62796_IG05:        ; offs=0x00001F, size=0x0006, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], gcvars, byref
       ; gcrRegs -[r8]
recordRelocation: 00000000D1FFAB1E (rw: 00000000D1FFAB1E) => 00000000D1FFAB1E, type 16 (IMAGE_REL_BASED_REL32), delta 0
IN0008: 00001F call     CORINFO_HELP_RNGCHKFAIL
       ; gcr arg pop 0
IN0009: 000024 int3     
						;; size=6 bbWeight=0 PerfScore 0.00

Allocated method code size =   37 , actual size =   37, unused size =    0

; Total bytes of code 37, prolog size 4, PerfScore 10.95, instruction count 12, allocated bytes for code 37 (MethodHash=57540ab3) for method Program:Test(int,long[]):this (FullOpts)
; ============================================================

IN000a: 000000 sub      rsp, 40

G_M62796_IG02:        ; offs=0x000004, size=0x0011, bbWeight=1, PerfScore 4.75, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref, isz

IN0001: 000004 mov      eax, dword ptr [r8+0x08]
IN0002: 000008 cmp      edx, eax
IN0003: 00000A jae      SHORT G_M62796_IG05
IN0004: 00000C mov      eax, edx
IN0005: 00000E xor      ecx, ecx
IN0006: 000010 mov      qword ptr [r8+8*rax+0x10], rcx

G_M62796_IG03:        ; offs=0x000015, size=0x0005, bbWeight=1, PerfScore 1.00, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, BB01 [0000], byref

IN0007: 000015 mov      qword ptr [r8+8*rax+0x10], rcx

G_M62796_IG04:        ; offs=0x00001A, size=0x0005, bbWeight=1, PerfScore 1.25, epilog, nogc, extend

IN000b: 00001A add      rsp, 40
IN000c: 00001E ret

G_M62796_IG05:        ; offs=0x00001F, size=0x0006, bbWeight=0, PerfScore 0.00, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], gcvars, byref

IN0008: 00001F call     CORINFO_HELP_RNGCHKFAIL
IN0009: 000024 int3

*************** Finishing PHASE Emit code

*************** Starting PHASE Emit GC+EH tables
Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0xd1ffab1e (not in unwind data)
  Version           : 1
  Flags             : 0x00
  SizeOfProlog      : 0x04
  CountOfUnwindCodes: 1
  FrameRegister     : none (0)
  FrameOffset       : N/A (no FrameRegister) (Value=0)
  UnwindCodes       :
    CodeOffset: 0x04 UnwindOp: UWOP_ALLOC_SMALL (2)     OpInfo: 4 * 8 + 8 = 40 = 0x28
allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x25, unwindSize=0x6, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 6
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000004 ( STACK_EMPTY )
IL offs 0x0005 : 0x00000015 ( STACK_EMPTY )
IL offs 0x000A : 0x0000001A ( STACK_EMPTY )
IL offs EPILOG : 0x0000001A ( STACK_EMPTY )
IL offs NO_MAP : 0x0000001F ( STACK_EMPTY )

*************** In genSetScopeInfo()
VarLocInfo count is 5
; Variable debug info: 3 live ranges, 3 vars for method Program:Test(int,long[]):this
(V00 this) : From 00000000h to 00000004h, in rcx
(V01 arg1) : From 00000000h to 0000000Ch, in rdx
(V02 arg2) : From 00000000h to 00000015h, in r8
*************** In gcInfoBlockHdrSave()
Set code length to 37.
Set ReturnKind to Scalar.
Set Outgoing stack arg area size to 32.
Defining 1 call sites:
    Offset 0x1f, size 5.

*************** Finishing PHASE Emit GC+EH tables
Method code size: 37

Allocations for Program:Test(int,long[]):this (MethodHash=57540ab3)
count:        683, size:      75127, max =       5488
allocateMemory:     131072, nraUsed:      78096

Alloc'd bytes by kind:
                  kind |       size |     pct
  ---------------------+------------+--------
         AssertionProp |       6652 |   8.85%
               ASTNode |       6928 |   9.22%
              InstDesc |       3136 |   4.17%
              ImpStack |        384 |   0.51%
            BasicBlock |       1440 |   1.92%
              CallArgs |          0 |   0.00%
              FlowEdge |          0 |   0.00%
     TreeStatementList |        128 |   0.17%
               SiScope |          0 |   0.00%
       DominatorMemory |         96 |   0.13%
                  LSRA |       7180 |   9.56%
         LSRA_Interval |        640 |   0.85%
      LSRA_RefPosition |       2320 |   3.09%
          Reachability |         40 |   0.05%
                   SSA |        400 |   0.53%
           ValueNumber |      15514 |  20.65%
              LvaTable |       1576 |   2.10%
            UnwindInfo |          0 |   0.00%
                hashBv |        128 |   0.17%
                bitset |         32 |   0.04%
          FixedBitVect |         16 |   0.02%
               Generic |        998 |   1.33%
   LocalAddressVisitor |          0 |   0.00%
         FieldSeqStore |          0 |   0.00%
          MemorySsaMap |         40 |   0.05%
          MemoryPhiArg |          0 |   0.00%
                   CSE |       1536 |   2.04%
                    GC |       1349 |   1.80%
       CorTailCallInfo |          0 |   0.00%
              Inlining |        440 |   0.59%
            ArrayStack |        128 |   0.17%
             DebugInfo |        408 |   0.54%
             DebugOnly |      20399 |  27.15%
               Codegen |       1240 |   1.65%
               LoopOpt |          0 |   0.00%
             LoopClone |          0 |   0.00%
             LoopHoist |          0 |   0.00%
               Unknown |        107 |   0.14%
            RangeCheck |        336 |   0.45%
              CopyProp |        424 |   0.56%
             Promotion |          0 |   0.00%
           SideEffects |          0 |   0.00%
       ObjectAllocator |          0 |   0.00%
    VariableLiveRanges |        880 |   1.17%
           ClassLayout |        128 |   0.17%
       TailMergeThrows |          0 |   0.00%
             EarlyProp |          0 |   0.00%
              ZeroInit |        104 |   0.14%
                   Pgo |          0 |   0.00%

****** DONE compiling Program:Test(int,long[]):this