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****** START compiling Program:IsHttps(System.String):bool (MethodHash=9eee6331)

Generating code for Windows x64

OPTIONS: compCodeOpt = BLENDED_CODE

OPTIONS: compDbgCode = false

OPTIONS: compDbgInfo = true

OPTIONS: compDbgEnC = false

OPTIONS: compProcedureSplitting = false

OPTIONS: compProcedureSplittingEH = false

OPTIONS: No PGO data

IL to import:

IL_0000 02 ldarg.0

IL_0001 72 01 00 00 70 ldstr 0x70000001

IL_0006 1b ldc.i4.5

IL_0007 6f 11 00 00 0a callvirt 0xA000011

IL_000c 2a ret

lvaSetClass: setting class for V00 to (00000000D1FFAB1E) System.String

Arg #0 passed in register(s) rcx

lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.

; Initial local variable assignments

;

; V00 arg0 ref class-hnd

; V01 OutArgs lclBlk <na> "OutgoingArgSpace"

*************** In compInitDebuggingInfo() for Program:IsHttps(System.String):bool

getVars() returned cVars = 0, extendOthers = true

info.compVarScopesCount = 1

VarNum LVNum Name Beg End

0: 00h 00h V00 arg0 000h 00Dh

info.compStmtOffsetsCount = 0

info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )

*************** In fgFindBasicBlocks() for Program:IsHttps(System.String):bool

Jump targets:

none

New Basic Block BB01 [0000] created.

BB01 [000..00D)

IL Code Size,Instr 13, 5, Basic Block count 1, Local Variable Num,Ref count 2, 1 for method Program:IsHttps(System.String):bool

OPTIONS: opts.MinOpts() == false

Basic block list for 'Program:IsHttps(System.String):bool'

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00D) (return)

-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import

Trees after Pre-import

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00D) (return)

-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00D) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Profile incorporation

BBOPT set, but no profile data available (hr=80004001)

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation

*************** In impImport() for Program:IsHttps(System.String):bool

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'Program:IsHttps(System.String):bool'

[ 0] 0 (0x000) ldarg.0

[ 1] 1 (0x001) ldstr 70000001

[ 2] 6 (0x006) ldc.i4.5 5

[ 3] 7 (0x007) callvirt 0A000011

(Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT)

In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is bool, structSize is 0

Named Intrinsic System.String.StartsWith: Recognized

Trying to unroll String.Equals|StartsWith(op1, "cns")...

lvaGrabTemp returning 2 (V02 tmp1) called for spilling varStr.

Notify VM instruction set (SSE2) must be supported.

Notify VM instruction set (Vector256) must be supported.

STMT00000 ( 0x000[E-] ... ??? )

[000041] -A--------- * ASG ref

[000040] D------N--- +--* LCL_VAR ref V02 tmp1

[000000] ----------- \--* LCL_VAR ref V00 arg0

lvaGrabTemp returning 3 (V03 tmp2) called for spilling unroll qmark.

STMT00001 ( ??? ... ??? )

[000043] -A-X------- * ASG int

[000042] D------N--- +--* LCL_VAR int V03 tmp2

[000039] ---X------- \--* QMARK int

[000039] ---X------- \--* QMARK bool

[000038] ---X------- if +--* GE int

[000006] ---X------- | +--* IND int

[000005] ----------- | | \--* ADD byref

[000003] ----------- | | +--* LCL_VAR ref V02 tmp1

[000004] ----------- | | \--* CNS_INT long 8

[000008] ----------- | \--* CNS_INT int 8

[000037] ---X------- if \--* COLON int

[000036] ----------- else +--* CNS_INT int 0

[000035] ---X------- then \--* HWINTRINSIC bool ulong op_Equality

[000032] ---X------- +--* HWINTRINSIC simd16 ulong Xor

[000030] ---X------- | +--* HWINTRINSIC simd16 ulong Or

[000028] ---X------- | | +--* IND simd16

[000025] ----------- | | | \--* ADD byref

[000009] ----------- | | | +--* LCL_VAR ref V02 tmp1

[000023] ----------- | | | \--* CNS_INT long 12

[000018] ----------- | | \--* HWINTRINSIC simd16 ulong Create

[000016] ----------- | | +--* CNS_INT long 0x20002000200020

[000017] ----------- | | \--* CNS_INT long 32

[000012] ----------- | \--* HWINTRINSIC simd16 ulong Create

[000010] ----------- | +--* CNS_INT long 0x70007400740068

[000011] ----------- | \--* CNS_INT long 0x2f002f003a0073

[000022] ----------- \--* CNS_VEC simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

... Successfully unrolled to:

[000044] ----------- * LCL_VAR int V03 tmp2

[ 1] 12 (0x00c) ret

STMT00002 ( ??? ... ??? )

[000045] ----------- * RETURN int

[000044] ----------- \--* LCL_VAR int V03 tmp2

*************** Finishing PHASE Importation

Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00D) (return) i

-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00D) (return), preds={} succs={}

***** BB01

STMT00000 ( 0x000[E-] ... 0x00C )

[000041] -A--------- * ASG ref

[000040] D------N--- +--* LCL_VAR ref V02 tmp1

[000000] ----------- \--* LCL_VAR ref V00 arg0

***** BB01

STMT00001 ( ??? ... ??? )

[000043] -A-X------- * ASG int

[000042] D------N--- +--* LCL_VAR int V03 tmp2

[000039] ---X------- \--* QMARK int

[000039] ---X------- \--* QMARK bool

[000038] ---X------- if +--* GE int

[000006] ---X------- | +--* IND int

[000005] ----------- | | \--* ADD byref

[000003] ----------- | | +--* LCL_VAR ref V02 tmp1

[000004] ----------- | | \--* CNS_INT long 8

[000008] ----------- | \--* CNS_INT int 8

[000037] ---X------- if \--* COLON int

[000036] ----------- else +--* CNS_INT int 0

[000035] ---X------- then \--* HWINTRINSIC bool ulong op_Equality

[000032] ---X------- +--* HWINTRINSIC simd16 ulong Xor

[000030] ---X------- | +--* HWINTRINSIC simd16 ulong Or

[000028] ---X------- | | +--* IND simd16

[000025] ----------- | | | \--* ADD byref

[000009] ----------- | | | +--* LCL_VAR ref V02 tmp1

[000023] ----------- | | | \--* CNS_INT long 12

[000018] ----------- | | \--* HWINTRINSIC simd16 ulong Create

[000016] ----------- | | +--* CNS_INT long 0x20002000200020

[000017] ----------- | | \--* CNS_INT long 32

[000012] ----------- | \--* HWINTRINSIC simd16 ulong Create

[000010] ----------- | +--* CNS_INT long 0x70007400740068

[000011] ----------- | \--* CNS_INT long 0x2f002f003a0073

[000022] ----------- \--* CNS_VEC simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

***** BB01

STMT00002 ( ??? ... ??? )

[000045] ----------- * RETURN int

[000044] ----------- \--* LCL_VAR int V03 tmp2

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Expand patchpoints

-- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Indirect call transform

-- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import [no changes]

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Init [no changes]

*************** Starting PHASE Morph - Inlining

*************** In fgDebugCheckBBlist

**************** Inline Tree

Inlines into 06000006 [via ExtendedDefaultPolicy] Program:IsHttps(System.String):bool:

Budget: initialTime=99, finalTime=99, initialBudget=990, currentBudget=990

Budget: initialSize=427, finalSize=427

*************** Finishing PHASE Morph - Inlining

Trees after Morph - Inlining

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00D) (return) i

-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00D) (return), preds={} succs={}

***** BB01

STMT00000 ( 0x000[E-] ... 0x00C )

[000041] -A--------- * ASG ref

[000040] D------N--- +--* LCL_VAR ref V02 tmp1

[000000] ----------- \--* LCL_VAR ref V00 arg0

***** BB01

STMT00001 ( ??? ... ??? )

[000043] -A-X------- * ASG int

[000042] D------N--- +--* LCL_VAR int V03 tmp2

[000039] ---X------- \--* QMARK int

[000039] ---X------- \--* QMARK bool

[000038] ---X------- if +--* GE int

[000006] ---X------- | +--* IND int

[000005] ----------- | | \--* ADD byref

[000003] ----------- | | +--* LCL_VAR ref V02 tmp1

[000004] ----------- | | \--* CNS_INT long 8

[000008] ----------- | \--* CNS_INT int 8

[000037] ---X------- if \--* COLON int

[000036] ----------- else +--* CNS_INT int 0

[000035] ---X------- then \--* HWINTRINSIC bool ulong op_Equality

[000032] ---X------- +--* HWINTRINSIC simd16 ulong Xor

[000030] ---X------- | +--* HWINTRINSIC simd16 ulong Or

[000028] ---X------- | | +--* IND simd16

[000025] ----------- | | | \--* ADD byref

[000009] ----------- | | | +--* LCL_VAR ref V02 tmp1

[000023] ----------- | | | \--* CNS_INT long 12

[000018] ----------- | | \--* HWINTRINSIC simd16 ulong Create

[000016] ----------- | | +--* CNS_INT long 0x20002000200020

[000017] ----------- | | \--* CNS_INT long 32

[000012] ----------- | \--* HWINTRINSIC simd16 ulong Create

[000010] ----------- | +--* CNS_INT long 0x70007400740068

[000011] ----------- | \--* CNS_INT long 0x2f002f003a0073

[000022] ----------- \--* CNS_VEC simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

***** BB01

STMT00002 ( ??? ... ??? )

[000045] ----------- * RETURN int

[000044] ----------- \--* LCL_VAR int V03 tmp2

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Allocate Objects

no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00D) (return) i

-----------------------------------------------------------------------------------------------------------------------------------------

*************** Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks [no changes]

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()

No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally

No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains

No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally

No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Compute preds

Renumbering the basic blocks for fgComputePred

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00D) (return) i

-----------------------------------------------------------------------------------------------------------------------------------------

*************** Exception Handling table is empty

*************** After renumbering the basic blocks

=============== No blocks renumbered!

*************** Finishing PHASE Compute preds

Trees after Compute preds

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00D) (return) i

-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00D) (return), preds={} succs={}

***** BB01

STMT00000 ( 0x000[E-] ... 0x00C )

[000041] -A--------- * ASG ref

[000040] D------N--- +--* LCL_VAR ref V02 tmp1

[000000] ----------- \--* LCL_VAR ref V00 arg0

***** BB01

STMT00001 ( ??? ... ??? )

[000043] -A-X------- * ASG int

[000042] D------N--- +--* LCL_VAR int V03 tmp2

[000039] ---X------- \--* QMARK int

[000039] ---X------- \--* QMARK bool

[000038] ---X------- if +--* GE int

[000006] ---X------- | +--* IND int

[000005] ----------- | | \--* ADD byref

[000003] ----------- | | +--* LCL_VAR ref V02 tmp1

[000004] ----------- | | \--* CNS_INT long 8

[000008] ----------- | \--* CNS_INT int 8

[000037] ---X------- if \--* COLON int

[000036] ----------- else +--* CNS_INT int 0

[000035] ---X------- then \--* HWINTRINSIC bool ulong op_Equality

[000032] ---X------- +--* HWINTRINSIC simd16 ulong Xor

[000030] ---X------- | +--* HWINTRINSIC simd16 ulong Or

[000028] ---X------- | | +--* IND simd16

[000025] ----------- | | | \--* ADD byref

[000009] ----------- | | | +--* LCL_VAR ref V02 tmp1

[000023] ----------- | | | \--* CNS_INT long 12

[000018] ----------- | | \--* HWINTRINSIC simd16 ulong Create

[000016] ----------- | | +--* CNS_INT long 0x20002000200020

[000017] ----------- | | \--* CNS_INT long 32

[000012] ----------- | \--* HWINTRINSIC simd16 ulong Create

[000010] ----------- | +--* CNS_INT long 0x70007400740068

[000011] ----------- | \--* CNS_INT long 0x2f002f003a0073

[000022] ----------- \--* CNS_VEC simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

***** BB01

STMT00002 ( ??? ... ??? )

[000045] ----------- * RETURN int

[000044] ----------- \--* LCL_VAR int V03 tmp2

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Merge throw blocks

*************** In fgTailMergeThrows

Method does not have multiple noreturn calls.

*************** Finishing PHASE Merge throw blocks [no changes]

*************** Starting PHASE Update flow graph early pass

*************** Finishing PHASE Update flow graph early pass [no changes]

*************** Starting PHASE Morph - Promote Structs

lvaTable before fgPromoteStructs

; Initial local variable assignments

;

; V00 arg0 ref class-hnd

; V01 OutArgs lclBlk <na> "OutgoingArgSpace"

; V02 tmp1 ref "spilling varStr"

; V03 tmp2 int "spilling unroll qmark"

*************** Finishing PHASE Morph - Promote Structs [no changes]

*************** Starting PHASE Morph - Structs/AddrExp

LocalAddressVisitor visiting statement:

STMT00000 ( 0x000[E-] ... 0x00C )

[000041] -A--------- * ASG ref

[000040] D------N--- +--* LCL_VAR ref V02 tmp1

[000000] ----------- \--* LCL_VAR ref V00 arg0

LocalAddressVisitor visiting statement:

STMT00001 ( ??? ... ??? )

[000043] -A-X------- * ASG int

[000042] D------N--- +--* LCL_VAR int V03 tmp2

[000039] ---X------- \--* QMARK int

[000039] ---X------- \--* QMARK bool

[000038] ---X------- if +--* GE int

[000006] ---X------- | +--* IND int

[000005] ----------- | | \--* ADD byref

[000003] ----------- | | +--* LCL_VAR ref V02 tmp1

[000004] ----------- | | \--* CNS_INT long 8

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****** START compiling Program:IsHttps(System.String):bool (MethodHash=9eee6331)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC  = false
OPTIONS: compProcedureSplitting   = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: No PGO data
IL to import:
IL_0000  02                ldarg.0     
IL_0001  72 01 00 00 70    ldstr        0x70000001
IL_0006  1b                ldc.i4.5    
IL_0007  6f 11 00 00 0a    callvirt     0xA000011
IL_000c  2a                ret

lvaSetClass: setting class for V00 to (00000000D1FFAB1E) System.String 
Arg #0    passed in register(s) rcx

lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
;  V00 arg0              ref  class-hnd
;  V01 OutArgs        lclBlk <na>  "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for Program:IsHttps(System.String):bool
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 1
    	VarNum 	LVNum 	      Name 	Beg 	End
 0: 	00h 	00h 	  V00 arg0 	000h   	00Dh
info.compStmtOffsetsCount    = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:IsHttps(System.String):bool
Jump targets:
  none
New Basic Block BB01 [0000] created.
BB01 [000..00D)
IL Code Size,Instr   13,   5, Basic Block count   1, Local Variable Num,Ref count   2,  1 for method Program:IsHttps(System.String):bool
OPTIONS: opts.MinOpts() == false
Basic block list for 'Program:IsHttps(System.String):bool'

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import
Trees after Pre-import

------------ BB01 [000..00D) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation
*************** In impImport() for Program:IsHttps(System.String):bool

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'Program:IsHttps(System.String):bool'
    [ 0]   0 (0x000) ldarg.0
    [ 1]   1 (0x001) ldstr 70000001
    [ 2]   6 (0x006) ldc.i4.5 5
    [ 3]   7 (0x007) callvirt 0A000011
 (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT)
In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is bool, structSize is 0
Named Intrinsic System.String.StartsWith: Recognized
Trying to unroll String.Equals|StartsWith(op1, "cns")...

lvaGrabTemp returning 2 (V02 tmp1) called for spilling varStr.
Notify VM instruction set (SSE2) must be supported.
Notify VM instruction set (Vector256) must be supported.

STMT00000 ( 0x000[E-] ... ??? )
               [000041] -A---------                         *  ASG       ref   
               [000040] D------N---                         +--*  LCL_VAR   ref    V02 tmp1         
               [000000] -----------                         \--*  LCL_VAR   ref    V00 arg0

lvaGrabTemp returning 3 (V03 tmp2) called for spilling unroll qmark.

STMT00001 ( ??? ... ??? )
               [000043] -A-X-------                         *  ASG       int   
               [000042] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-------                         \--*  QMARK     int   
               [000038] ---X-------    if                      +--*  GE        int   
               [000006] ---X-------                            |  +--*  IND       int   
               [000005] -----------                            |  |  \--*  ADD       byref 
               [000003] -----------                            |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000004] -----------                            |  |     \--*  CNS_INT   long   8
               [000008] -----------                            |  \--*  CNS_INT   int    8
               [000037] ---X-------    if                      \--*  COLON     int   
               [000036] ----------- else                          +--*  CNS_INT   int    0
               [000035] ---X------- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-------                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-------                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-------                                  |  |  +--*  IND       simd16
               [000025] -----------                                  |  |  |  \--*  ADD       byref 
               [000009] -----------                                  |  |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000023] -----------                                  |  |  |     \--*  CNS_INT   long   12
               [000018] -----------                                  |  |  \--*  HWINTRINSIC simd16 ulong Create
               [000016] -----------                                  |  |     +--*  CNS_INT   long   0x20002000200020
               [000017] -----------                                  |  |     \--*  CNS_INT   long   32
               [000012] -----------                                  |  \--*  HWINTRINSIC simd16 ulong Create
               [000010] -----------                                  |     +--*  CNS_INT   long   0x70007400740068
               [000011] -----------                                  |     \--*  CNS_INT   long   0x2f002f003a0073
               [000022] -----------                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

... Successfully unrolled to:
               [000044] -----------                         *  LCL_VAR   int    V03 tmp2

[ 1]  12 (0x00c) ret

STMT00002 ( ??? ... ??? )
               [000045] -----------                         *  RETURN    int   
               [000044] -----------                         \--*  LCL_VAR   int    V03 tmp2

*************** Finishing PHASE Importation
Trees after Importation

------------ BB01 [000..00D) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00C )
               [000041] -A---------                         *  ASG       ref   
               [000040] D------N---                         +--*  LCL_VAR   ref    V02 tmp1         
               [000000] -----------                         \--*  LCL_VAR   ref    V00 arg0

***** BB01
STMT00001 ( ??? ... ??? )
               [000043] -A-X-------                         *  ASG       int   
               [000042] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-------                         \--*  QMARK     int   
               [000038] ---X-------    if                      +--*  GE        int   
               [000006] ---X-------                            |  +--*  IND       int   
               [000005] -----------                            |  |  \--*  ADD       byref 
               [000003] -----------                            |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000004] -----------                            |  |     \--*  CNS_INT   long   8
               [000008] -----------                            |  \--*  CNS_INT   int    8
               [000037] ---X-------    if                      \--*  COLON     int   
               [000036] ----------- else                          +--*  CNS_INT   int    0
               [000035] ---X------- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-------                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-------                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-------                                  |  |  +--*  IND       simd16
               [000025] -----------                                  |  |  |  \--*  ADD       byref 
               [000009] -----------                                  |  |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000023] -----------                                  |  |  |     \--*  CNS_INT   long   12
               [000018] -----------                                  |  |  \--*  HWINTRINSIC simd16 ulong Create
               [000016] -----------                                  |  |     +--*  CNS_INT   long   0x20002000200020
               [000017] -----------                                  |  |     \--*  CNS_INT   long   32
               [000012] -----------                                  |  \--*  HWINTRINSIC simd16 ulong Create
               [000010] -----------                                  |     +--*  CNS_INT   long   0x70007400740068
               [000011] -----------                                  |     \--*  CNS_INT   long   0x2f002f003a0073
               [000022] -----------                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

***** BB01
STMT00002 ( ??? ... ??? )
               [000045] -----------                         *  RETURN    int   
               [000044] -----------                         \--*  LCL_VAR   int    V03 tmp2

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Expand patchpoints

-- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Indirect call transform

-- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import [no changes]

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Init [no changes]

*************** Starting PHASE Morph - Inlining
*************** In fgDebugCheckBBlist
**************** Inline Tree

Inlines into 06000006 [via ExtendedDefaultPolicy] Program:IsHttps(System.String):bool:
Budget: initialTime=99, finalTime=99, initialBudget=990, currentBudget=990
Budget: initialSize=427, finalSize=427

*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining

------------ BB01 [000..00D) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Allocate Objects
no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

***************  Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks [no changes]

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally
No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Compute preds

Renumbering the basic blocks for fgComputePred

*************** Before renumbering the basic blocks

***************  Exception Handling table is empty

*************** After renumbering the basic blocks
=============== No blocks renumbered!

*************** Finishing PHASE Compute preds
Trees after Compute preds

------------ BB01 [000..00D) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Merge throw blocks

*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.

*************** Finishing PHASE Merge throw blocks [no changes]

*************** Starting PHASE Update flow graph early pass

*************** Finishing PHASE Update flow graph early pass [no changes]

*************** Starting PHASE Morph - Promote Structs

lvaTable before fgPromoteStructs
; Initial local variable assignments
;
;  V00 arg0              ref  class-hnd
;  V01 OutArgs        lclBlk <na>  "OutgoingArgSpace"
;  V02 tmp1              ref  "spilling varStr"
;  V03 tmp2              int  "spilling unroll qmark"

*************** Finishing PHASE Morph - Promote Structs [no changes]

*************** Starting PHASE Morph - Structs/AddrExp
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x00C )
               [000041] -A---------                         *  ASG       ref   
               [000040] D------N---                         +--*  LCL_VAR   ref    V02 tmp1         
               [000000] -----------                         \--*  LCL_VAR   ref    V00 arg0

LocalAddressVisitor visiting statement:
STMT00001 ( ??? ... ??? )
               [000043] -A-X-------                         *  ASG       int   
               [000042] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-------                         \--*  QMARK     int   
               [000038] ---X-------    if                      +--*  GE        int   
               [000006] ---X-------                            |  +--*  IND       int   
               [000005] -----------                            |  |  \--*  ADD       byref 
               [000003] -----------                            |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000004] -----------                            |  |     \--*  CNS_INT   long   8
               [000008] -----------                            |  \--*  CNS_INT   int    8
               [000037] ---X-------    if                      \--*  COLON     int   
               [000036] ----------- else                          +--*  CNS_INT   int    0
               [000035] ---X------- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-------                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-------                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-------                                  |  |  +--*  IND       simd16
               [000025] -----------                                  |  |  |  \--*  ADD       byref 
               [000009] -----------                                  |  |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000023] -----------                                  |  |  |     \--*  CNS_INT   long   12
               [000018] -----------                                  |  |  \--*  HWINTRINSIC simd16 ulong Create
               [000016] -----------                                  |  |     +--*  CNS_INT   long   0x20002000200020
               [000017] -----------                                  |  |     \--*  CNS_INT   long   32
               [000012] -----------                                  |  \--*  HWINTRINSIC simd16 ulong Create
               [000010] -----------                                  |     +--*  CNS_INT   long   0x70007400740068
               [000011] -----------                                  |     \--*  CNS_INT   long   0x2f002f003a0073
               [000022] -----------                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

LocalAddressVisitor visiting statement:
STMT00002 ( ??? ... ??? )
               [000045] -----------                         *  RETURN    int   
               [000044] -----------                         \--*  LCL_VAR   int    V03 tmp2

*************** Finishing PHASE Morph - Structs/AddrExp [no changes]

*************** Starting PHASE Forward Substitution

===> BB01
    [000041]:  not asg (single-use lcl)
    [000043]:  tree to sub is qmark, catch arg, or lcl heap

*************** Finishing PHASE Forward Substitution [no changes]

*************** Starting PHASE Morph - ByRefs

*************** Finishing PHASE Morph - ByRefs [no changes]

*************** Starting PHASE Morph - Global

*************** In fgMorphBlocks()

Morphing BB01 of 'Program:IsHttps(System.String):bool'

fgMorphTree BB01, STMT00000 (before)
               [000041] -A---------                         *  ASG       ref   
               [000040] D------N---                         +--*  LCL_VAR   ref    V02 tmp1         
               [000000] -----------                         \--*  LCL_VAR   ref    V00 arg0         
GenTreeNode creates assertion:
               [000041] -A---+-----                         *  ASG       ref   
In BB01 New Local Copy     Assertion: V02 == V00, index = #01

fgMorphTree BB01, STMT00001 (before)
               [000043] -A-X-------                         *  ASG       int   
               [000042] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-------                         \--*  QMARK     int   
               [000038] ---X-------    if                      +--*  GE        int   
               [000006] ---X-------                            |  +--*  IND       int   
               [000005] -----------                            |  |  \--*  ADD       byref 
               [000003] -----------                            |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000004] -----------                            |  |     \--*  CNS_INT   long   8
               [000008] -----------                            |  \--*  CNS_INT   int    8
               [000037] ---X-------    if                      \--*  COLON     int   
               [000036] ----------- else                          +--*  CNS_INT   int    0
               [000035] ---X------- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-------                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-------                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-------                                  |  |  +--*  IND       simd16
               [000025] -----------                                  |  |  |  \--*  ADD       byref 
               [000009] -----------                                  |  |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000023] -----------                                  |  |  |     \--*  CNS_INT   long   12
               [000018] -----------                                  |  |  \--*  HWINTRINSIC simd16 ulong Create
               [000016] -----------                                  |  |     +--*  CNS_INT   long   0x20002000200020
               [000017] -----------                                  |  |     \--*  CNS_INT   long   32
               [000012] -----------                                  |  \--*  HWINTRINSIC simd16 ulong Create
               [000010] -----------                                  |     +--*  CNS_INT   long   0x70007400740068
               [000011] -----------                                  |     \--*  CNS_INT   long   0x2f002f003a0073
               [000022] -----------                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

Assertion prop in BB01:
Copy     Assertion: V02 == V00, index = #01
               [000003] -----------                         *  LCL_VAR   ref    V00 arg0         
GenTreeNode creates assertion:
               [000006] ---X-+-----                         *  IND       int   
In BB01 New Local Constant Assertion: V00 != null, index = #02

Assertion prop in BB01:
Copy     Assertion: V02 == V00, index = #01
               [000009] -----------                         *  LCL_VAR   ref    V00 arg0

fgMorphTree BB01, STMT00001 (after)
               [000043] -A-X-+-----                         *  ASG       int   
               [000042] D----+-N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-+-----                         \--*  QMARK     int   
               [000038] J--X-+-N---    if                      +--*  GE        int   
               [000006] ---X-+-----                            |  +--*  IND       int   
               [000005] -----+-----                            |  |  \--*  ADD       byref 
               [000003] -----+-----                            |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000004] -----+-----                            |  |     \--*  CNS_INT   long   8
               [000008] -----+-----                            |  \--*  CNS_INT   int    8
               [000037] ---X-+?----    if                      \--*  COLON     int   
               [000036] -----+?---- else                          +--*  CNS_INT   int    0
               [000035] ---X-+?---- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-+?----                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-+?----                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-+?----                                  |  |  +--*  IND       simd16
               [000025] -----+?----                                  |  |  |  \--*  ADD       byref 
               [000009] -----+?----                                  |  |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000023] -----+?----                                  |  |  |     \--*  CNS_INT   long   12
               [000046] -----+?----                                  |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
               [000047] -----+?----                                  |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
               [000022] -----+?----                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

fgMorphTree BB01, STMT00002 (before)
               [000045] -----------                         *  RETURN    int   
               [000044] -----------                         \--*  LCL_VAR   int    V03 tmp2

fgMorphTree BB01, STMT00002 (after)
               [000045] -----+-----                         *  RETURN    int   
               [000048] -----+-----                         \--*  CAST      int <- bool <- int
               [000044] -----+-----                            \--*  LCL_VAR   int    V03 tmp2

*************** In fgMarkDemotedImplicitByRefArgs()

Expanding top-level qmark in BB01 (before)

------------ BB01 [000..00D) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00C )
               [000041] -A---+-----                         *  ASG       ref   
               [000040] D----+-N---                         +--*  LCL_VAR   ref    V02 tmp1         
               [000000] -----+-----                         \--*  LCL_VAR   ref    V00 arg0

***** BB01
STMT00001 ( ??? ... ??? )
               [000043] -A-X-+-----                         *  ASG       int   
               [000042] D----+-N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-+-----                         \--*  QMARK     int   
               [000038] J--X-+-N---    if                      +--*  GE        int   
               [000006] ---X-+-----                            |  +--*  IND       int   
               [000005] -----+-----                            |  |  \--*  ADD       byref 
               [000003] -----+-----                            |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000004] -----+-----                            |  |     \--*  CNS_INT   long   8
               [000008] -----+-----                            |  \--*  CNS_INT   int    8
               [000037] ---X-+?----    if                      \--*  COLON     int   
               [000036] -----+?---- else                          +--*  CNS_INT   int    0
               [000035] ---X-+?---- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-+?----                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-+?----                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-+?----                                  |  |  +--*  IND       simd16
               [000025] -----+?----                                  |  |  |  \--*  ADD       byref 
               [000009] -----+?----                                  |  |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000023] -----+?----                                  |  |  |     \--*  CNS_INT   long   12
               [000046] -----+?----                                  |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
               [000047] -----+?----                                  |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
               [000022] -----+?----                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

***** BB01
STMT00002 ( ??? ... ??? )
               [000045] -----+-----                         *  RETURN    int   
               [000048] -----+-----                         \--*  CAST      int <- bool <- int
               [000044] -----+-----                            \--*  LCL_VAR   int    V03 tmp2

-------------------------------------------------------------------------------------------------------------------
New Basic Block BB02 [0001] created.
Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38]
New Basic Block BB03 [0002] created.
New Basic Block BB04 [0003] created.
Setting edge weights for BB01 -> BB03 to [0 .. 3.402823e+38]
Setting edge weights for BB03 -> BB04 to [0 .. 3.402823e+38]
Setting edge weights for BB04 -> BB02 to [0 .. 3.402823e+38]
New Basic Block BB05 [0004] created.
Setting edge weights for BB03 -> BB05 to [0 .. 3.402823e+38]
Setting edge weights for BB05 -> BB02 to [0 .. 3.402823e+38]

removing useless STMT00001 ( ??? ... ??? )
               [000043] -A-X-+-----                         *  ASG       int   
               [000042] D----+-N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-+-----                         \--*  QMARK     int   
               [000038] J--X-+-N---    if                      +--*  LT        int   
               [000006] ---X-+-----                            |  +--*  IND       int   
               [000005] -----+-----                            |  |  \--*  ADD       byref 
               [000003] -----+-----                            |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000004] -----+-----                            |  |     \--*  CNS_INT   long   8
               [000008] -----+-----                            |  \--*  CNS_INT   int    8
               [000037] ---X-+?----    if                      \--*  COLON     int   
               [000036] -----+?---- else                          +--*  CNS_INT   int    0
               [000035] ---X-+?---- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-+?----                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-+?----                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-+?----                                  |  |  +--*  IND       simd16
               [000025] -----+?----                                  |  |  |  \--*  ADD       byref 
               [000009] -----+?----                                  |  |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000023] -----+?----                                  |  |  |     \--*  CNS_INT   long   12
               [000046] -----+?----                                  |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
               [000047] -----+?----                                  |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
               [000022] -----+?----                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>
 from BB01

Expanding top-level qmark in BB01 (after)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)                                     i 
BB03 [0002]  1       BB01                  1       [???..???)-> BB04 ( cond )                     i 
BB05 [0004]  1       BB03                  0.50    [???..???)-> BB02 (always)                     i 
BB04 [0003]  1       BB03                  0.50    [???..???)                                     i 
BB02 [0001]  2       BB04,BB05             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???), preds={} succs={BB03}

------------ BB03 [???..???) -> BB04 (cond), preds={BB01} succs={BB05,BB04}

***** BB03
STMT00003 ( ??? ... ??? )
               [000049] ---X-------                         *  JTRUE     void  
               [000038] J--X-+-N---                         \--*  LT        int   
               [000006] ---X-+-----                            +--*  IND       int   
               [000005] -----+-----                            |  \--*  ADD       byref 
               [000003] -----+-----                            |     +--*  LCL_VAR   ref    V00 arg0         
               [000004] -----+-----                            |     \--*  CNS_INT   long   8
               [000008] -----+-----                            \--*  CNS_INT   int    8

------------ BB05 [???..???) -> BB02 (always), preds={BB03} succs={BB02}

***** BB05
STMT00004 ( ??? ... ??? )
               [000051] -A-X-------                         *  ASG       int   
               [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000035] ---X-+?----                         \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-+?----                            +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-+?----                            |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-+?----                            |  |  +--*  IND       simd16
               [000025] -----+?----                            |  |  |  \--*  ADD       byref 
               [000009] -----+?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000023] -----+?----                            |  |  |     \--*  CNS_INT   long   12
               [000046] -----+?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
               [000047] -----+?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
               [000022] -----+?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

------------ BB04 [???..???), preds={BB03} succs={BB02}

***** BB04
STMT00005 ( ??? ... ??? )
               [000053] -A---------                         *  ASG       int   
               [000052] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000036] -----+?----                         \--*  CNS_INT   int    0

------------ BB02 [???..00D) (return), preds={BB04,BB05} succs={}

***** BB02
STMT00002 ( ??? ... ??? )
               [000045] -----+-----                         *  RETURN    int   
               [000048] -----+-----                         \--*  CAST      int <- bool <- int
               [000044] -----+-----                            \--*  LCL_VAR   int    V03 tmp2

-------------------------------------------------------------------------------------------------------------------

*************** Before renumbering the basic blocks

***************  Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB05 to BB03
Renumber BB02 to BB05

*************** After renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)                                     i 
BB02 [0002]  1       BB01                  1       [???..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB02                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB02                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

New BlockSet epoch 2, # of blocks (including unused BB00): 6, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Global
Trees after Morph - Global

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)                                     i 
BB02 [0002]  1       BB01                  1       [???..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB02                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB02                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???), preds={} succs={BB02}

------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}

***** BB02
STMT00003 ( ??? ... ??? )
               [000049] ---X-------                         *  JTRUE     void  
               [000038] J--X-+-N---                         \--*  LT        int   
               [000006] ---X-+-----                            +--*  IND       int   
               [000005] -----+-----                            |  \--*  ADD       byref 
               [000003] -----+-----                            |     +--*  LCL_VAR   ref    V00 arg0         
               [000004] -----+-----                            |     \--*  CNS_INT   long   8
               [000008] -----+-----                            \--*  CNS_INT   int    8

------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}

***** BB03
STMT00004 ( ??? ... ??? )
               [000051] -A-X-------                         *  ASG       int   
               [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000035] ---X-+?----                         \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-+?----                            +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-+?----                            |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-+?----                            |  |  +--*  IND       simd16
               [000025] -----+?----                            |  |  |  \--*  ADD       byref 
               [000009] -----+?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000023] -----+?----                            |  |  |     \--*  CNS_INT   long   12
               [000046] -----+?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
               [000047] -----+?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
               [000022] -----+?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

------------ BB04 [???..???), preds={BB02} succs={BB05}

------------ BB05 [???..00D) (return), preds={BB03,BB04} succs={}

***** BB05
STMT00002 ( ??? ... ??? )
               [000045] -----+-----                         *  RETURN    int   
               [000048] -----+-----                         \--*  CAST      int <- bool <- int
               [000044] -----+-----                            \--*  LCL_VAR   int    V03 tmp2

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE GS Cookie
No GS security needed

*************** Finishing PHASE GS Cookie [no changes]

*************** Starting PHASE Compute edge weights (1, false)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)                                     i 
BB02 [0002]  1       BB01                  1       [???..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB02                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB02                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

-- no profile data, so using default called count
 -- not optimizing or no profile data, so not computing edge weights

*************** Finishing PHASE Compute edge weights (1, false) [no changes]

*************** Starting PHASE Create EH funclets

*************** Finishing PHASE Create EH funclets [no changes]

*************** Starting PHASE Invert loops

*************** Finishing PHASE Invert loops [no changes]

*************** Starting PHASE Optimize control flow

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)                                     i 
BB02 [0002]  1       BB01                  1       [???..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB02                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB02                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

Considering uncond to cond BB01 -> BB02

Compacting blocks BB01 and BB02:
*************** In fgDebugCheckBBlist
Considering uncond to cond BB03 -> BB05
Considering uncond to cond BB04 -> BB05
Considering uncond to cond BB03 -> BB05
Considering uncond to cond BB04 -> BB05

After updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB01                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
*************** In fgDebugCheckBBlist

*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()

Initial BasicBlocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB01                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB01                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize control flow
Trees after Optimize control flow

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB01                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB04 (cond), preds={} succs={BB03,BB04}

***** BB01
STMT00003 ( ??? ... ??? )
               [000049] ---X-------                         *  JTRUE     void  
               [000038] J--X-+-N---                         \--*  LT        int   
               [000006] ---X-+-----                            +--*  IND       int   
               [000005] -----+-----                            |  \--*  ADD       byref 
               [000003] -----+-----                            |     +--*  LCL_VAR   ref    V00 arg0         
               [000004] -----+-----                            |     \--*  CNS_INT   long   8
               [000008] -----+-----                            \--*  CNS_INT   int    8

------------ BB03 [???..???) -> BB05 (always), preds={BB01} succs={BB05}

------------ BB04 [???..???), preds={BB01} succs={BB05}

------------ BB05 [???..00D) (return), preds={BB03,BB04} succs={}

*************** Starting PHASE Compute blocks reachability
Return blocks: BB05

Renumbering the basic blocks for fgComputeReachability pass #1

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB01                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB04 to BB03
Renumber BB05 to BB04

*************** After renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.50    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

New BlockSet epoch 3, # of blocks (including unused BB00): 5, bitset array size: 1 (short)
Enter blocks: BB01

After computing reachability sets:
------------------------------------------------
BBnum  Reachable by 
------------------------------------------------
BB01 : BB01 
BB02 : BB01 BB02 
BB03 : BB01 BB03 
BB04 : BB01 BB02 BB03 BB04 
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist

Dominator computation start blocks (those blocks with no incoming edges):
BB01 
------------------------------------------------
BBnum  Dominated by
------------------------------------------------
BB01:  BB01 
BB02:  BB02 BB01 
BB03:  BB03 BB01 
BB04:  BB04 BB01

Inside fgBuildDomTree

After computing the Dominance Tree:
BB01 : BB04 BB03 BB02

After numbering the dominator tree:
BB01: pre=01, post=04
BB02: pre=04, post=03
BB03: pre=03, post=02
BB04: pre=02, post=01

*************** Finishing PHASE Compute blocks reachability
Trees after Compute blocks reachability

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.50    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( ??? ... ??? )
               [000051] -A-X-------                         *  ASG       int   
               [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000035] ---X-+?----                         \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-+?----                            +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-+?----                            |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-+?----                            |  |  +--*  IND       simd16
               [000025] -----+?----                            |  |  |  \--*  ADD       byref 
               [000009] -----+?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000023] -----+?----                            |  |  |     \--*  CNS_INT   long   12
               [000046] -----+?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
               [000047] -----+?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
               [000022] -----+?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

------------ BB03 [???..???), preds={BB01} succs={BB04}

***** BB03
STMT00005 ( ??? ... ??? )
               [000053] -A---------                         *  ASG       int   
               [000052] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000036] -----+?----                         \--*  CNS_INT   int    0

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00002 ( ??? ... ??? )
               [000045] -----+-----                         *  RETURN    int   
               [000048] -----+-----                         \--*  CAST      int <- bool <- int
               [000044] -----+-----                            \--*  LCL_VAR   int    V03 tmp2

*************** Starting PHASE Set block weights

*************** Finishing PHASE Set block weights
Trees after Set block weights

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

*************** Starting PHASE Find loops
*************** In optFindLoops()
*************** In optMarkLoopHeads()
0 loop heads marked

*************** Finishing PHASE Find loops
Trees after Find loops

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Clone loops

*************** In optCloneLoops()
  No loops to clone

*************** Finishing PHASE Clone loops [no changes]

*************** Starting PHASE Unroll loops

*************** Finishing PHASE Unroll loops [no changes]

*************** Starting PHASE Clear loop info

*************** Finishing PHASE Clear loop info [no changes]

*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function

*************** Finishing PHASE Morph array ops [no changes]

*************** Starting PHASE Mark local vars

*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** marking local variables in block BB01 (weight=1   )
STMT00000 ( 0x000[E-] ... 0x00C )
               [000041] -A---+-----                         *  ASG       ref   
               [000040] D----+-N---                         +--*  LCL_VAR   ref    V02 tmp1         
               [000000] -----+-----                         \--*  LCL_VAR   ref    V00 arg0         
New refCnts for V02: refCnt =  1, refCntWtd = 2   
Marking EH Var V02 as a register candidate.
New refCnts for V00: refCnt =  1, refCntWtd = 1   
STMT00003 ( ??? ... ??? )
               [000049] ---X-------                         *  JTRUE     void  
               [000038] J--X-+-N---                         \--*  LT        int   
               [000006] ---X-+-----                            +--*  IND       int   
               [000005] -----+-----                            |  \--*  ADD       byref 
               [000003] -----+-----                            |     +--*  LCL_VAR   ref    V00 arg0         
               [000004] -----+-----                            |     \--*  CNS_INT   long   8
               [000008] -----+-----                            \--*  CNS_INT   int    8
New refCnts for V00: refCnt =  2, refCntWtd = 2

*** marking local variables in block BB02 (weight=0.25)
STMT00004 ( ??? ... ??? )
               [000051] -A-X-------                         *  ASG       int   
               [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000035] ---X-+?----                         \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-+?----                            +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-+?----                            |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-+?----                            |  |  +--*  IND       simd16
               [000025] -----+?----                            |  |  |  \--*  ADD       byref 
               [000009] -----+?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000023] -----+?----                            |  |  |     \--*  CNS_INT   long   12
               [000046] -----+?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
               [000047] -----+?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
               [000022] -----+?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>
New refCnts for V03: refCnt =  1, refCntWtd = 0.50
V03 needs explicit zero init. Disqualified as a single-def register candidate.
New refCnts for V00: refCnt =  3, refCntWtd = 2.25

*** marking local variables in block BB03 (weight=0.25)
STMT00005 ( ??? ... ??? )
               [000053] -A---------                         *  ASG       int   
               [000052] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000036] -----+?----                         \--*  CNS_INT   int    0
New refCnts for V03: refCnt =  2, refCntWtd = 1

*** marking local variables in block BB04 (weight=1   )
STMT00002 ( ??? ... ??? )
               [000045] -----+-----                         *  RETURN    int   
               [000048] -----+-----                         \--*  CAST      int <- bool <- int
               [000044] -----+-----                            \--*  LCL_VAR   int    V03 tmp2         
New refCnts for V03: refCnt =  3, refCntWtd = 3

*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt =  4, refCntWtd = 3.25
New refCnts for V00: refCnt =  5, refCntWtd = 4.25

*************** Finishing PHASE Mark local vars [no changes]

*************** Starting PHASE Opt add copies

*************** In optAddCopies()

*************** Finishing PHASE Opt add copies [no changes]

*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()

*************** Finishing PHASE Find oper order
Trees after Find oper order

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00C )
     (  5,  4) [000041] -A------R--                         *  ASG       ref   
     (  3,  2) [000040] D------N---                         +--*  LCL_VAR   ref    V02 tmp1         
     (  1,  1) [000000] -----------                         \--*  LCL_VAR   ref    V00 arg0

***** BB01
STMT00003 ( ??? ... ??? )
     (  8,  8) [000049] ---X-------                         *  JTRUE     void  
     (  6,  6) [000038] J--X---N---                         \--*  LT        int   
     (  4,  4) [000006] ---X-------                            +--*  IND       int   
     (  2,  2) [000005] -------N---                            |  \--*  ADD       byref 
     (  1,  1) [000003] -----------                            |     +--*  LCL_VAR   ref    V00 arg0         
     (  1,  1) [000004] -----------                            |     \--*  CNS_INT   long   8
     (  1,  1) [000008] -----------                            \--*  CNS_INT   int    8

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( ??? ... ??? )
     ( 14, 13) [000051] -A-X----R--                         *  ASG       int   
     (  1,  1) [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
     ( 14, 13) [000035] ---X--?----                         \--*  HWINTRINSIC bool   ulong op_Equality
     ( 12, 10) [000032] ---X--?----                            +--*  HWINTRINSIC simd16 ulong Xor
     (  8,  7) [000030] ---X--?----                            |  +--*  HWINTRINSIC simd16 ulong Or
     (  4,  4) [000028] ---X--?----                            |  |  +--*  IND       simd16
     (  2,  2) [000025] ------?N---                            |  |  |  \--*  ADD       byref 
     (  1,  1) [000009] ------?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         
     (  1,  1) [000023] ------?----                            |  |  |     \--*  CNS_INT   long   12
     (  3,  2) [000046] ------?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
     (  3,  2) [000047] ------?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
     (  1,  2) [000022] ------?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

------------ BB03 [???..???), preds={BB01} succs={BB04}

***** BB03
STMT00005 ( ??? ... ??? )
     (  1,  3) [000053] -A------R--                         *  ASG       int   
     (  1,  1) [000052] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
     (  1,  1) [000036] ------?----                         \--*  CNS_INT   int    0

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00002 ( ??? ... ??? )
     (  3,  4) [000045] -----------                         *  RETURN    int   
     (  2,  3) [000048] -----------                         \--*  CAST      int <- bool <- int
     (  1,  1) [000044] -----------                            \--*  LCL_VAR   int    V03 tmp2

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has   12 tree nodes

*************** Finishing PHASE Set block order
Trees after Set block order

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00C )
N003 (  5,  4) [000041] -A------R--                         *  ASG       ref   
N002 (  3,  2) [000040] D------N---                         +--*  LCL_VAR   ref    V02 tmp1         
N001 (  1,  1) [000000] -----------                         \--*  LCL_VAR   ref    V00 arg0

***** BB01
STMT00003 ( ??? ... ??? )
N007 (  8,  8) [000049] ---X-------                         *  JTRUE     void  
N006 (  6,  6) [000038] J--X---N---                         \--*  LT        int   
N004 (  4,  4) [000006] ---X-------                            +--*  IND       int   
N003 (  2,  2) [000005] -------N---                            |  \--*  ADD       byref 
N001 (  1,  1) [000003] -----------                            |     +--*  LCL_VAR   ref    V00 arg0         
N002 (  1,  1) [000004] -----------                            |     \--*  CNS_INT   long   8
N005 (  1,  1) [000008] -----------                            \--*  CNS_INT   int    8

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( ??? ... ??? )
N012 ( 14, 13) [000051] -A-X----R--                         *  ASG       int   
N011 (  1,  1) [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
N010 ( 14, 13) [000035] ---X--?----                         \--*  HWINTRINSIC bool   ulong op_Equality
N008 ( 12, 10) [000032] ---X--?----                            +--*  HWINTRINSIC simd16 ulong Xor
N006 (  8,  7) [000030] ---X--?----                            |  +--*  HWINTRINSIC simd16 ulong Or
N004 (  4,  4) [000028] ---X--?----                            |  |  +--*  IND       simd16
N003 (  2,  2) [000025] ------?N---                            |  |  |  \--*  ADD       byref 
N001 (  1,  1) [000009] ------?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         
N002 (  1,  1) [000023] ------?----                            |  |  |     \--*  CNS_INT   long   12
N005 (  3,  2) [000046] ------?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
N007 (  3,  2) [000047] ------?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
N009 (  1,  2) [000022] ------?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

------------ BB03 [???..???), preds={BB01} succs={BB04}

***** BB03
STMT00005 ( ??? ... ??? )
N003 (  1,  3) [000053] -A------R--                         *  ASG       int   
N002 (  1,  1) [000052] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
N001 (  1,  1) [000036] ------?----                         \--*  CNS_INT   int    0

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00002 ( ??? ... ??? )
N003 (  3,  4) [000045] -----------                         *  RETURN    int   
N002 (  2,  3) [000048] -----------                         \--*  CAST      int <- bool <- int
N001 (  1,  1) [000044] -----------                            \--*  LCL_VAR   int    V03 tmp2

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 5.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]

Inside fgBuildDomTree

After computing the Dominance Tree:
BB01 : BB04 BB03 BB02

*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Tracked variable (3 out of 4) table:
V00 arg0          [   ref]: refCnt =    5, refCntWtd =   4.25
V03 tmp2          [   int]: refCnt =    3, refCntWtd =   3   
V02 tmp1          [   ref]: refCnt =    1, refCntWtd =   2

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00    } + ByrefExposed + GcHeap
     DEF(1)={    V02}

BB02 USE(1)={V00    } + ByrefExposed + GcHeap
     DEF(1)={    V03}

BB03 USE(0)={   }
     DEF(1)={V03}

BB04 USE(1)={V03}
     DEF(0)={   }

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(1)={V00} + ByrefExposed + GcHeap

BB02 IN (1)={V00    } + ByrefExposed + GcHeap
     OUT(1)={    V03}

BB03 IN (0)={   }
     OUT(1)={V03}

BB04 IN (1)={V03}
     OUT(0)={   }

top level assign
removing stmt with no side effects

removing useless STMT00000 ( 0x000[E-] ... 0x00C )
N003 (  5,  4) [000041] -A------R--                         *  ASG       ref   
N002 (  3,  2) [000040] D------N---                         +--*  LCL_VAR   ref    V02 tmp1         
N001 (  1,  1) [000000] -----------                         \--*  LCL_VAR   ref    V00 arg0         
 from BB01
*************** In optRemoveRedundantZeroInits()
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
Added PHI definition for V03 at start of BB04.
*************** In SsaBuilder::RenameVariables()

*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00003 ( ??? ... ??? )
N007 (  8,  8) [000049] ---X-------                         *  JTRUE     void  
N006 (  6,  6) [000038] J--X---N---                         \--*  LT        int   
N004 (  4,  4) [000006] ---X-------                            +--*  IND       int   
N003 (  2,  2) [000005] -------N---                            |  \--*  ADD       byref 
N001 (  1,  1) [000003] -----------                            |     +--*  LCL_VAR   ref    V00 arg0         u:1
N002 (  1,  1) [000004] -----------                            |     \--*  CNS_INT   long   8
N005 (  1,  1) [000008] -----------                            \--*  CNS_INT   int    8

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( ??? ... ??? )
N012 ( 14, 13) [000051] -A-X----R--                         *  ASG       int   
N011 (  1,  1) [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:3
N010 ( 14, 13) [000035] ---X--?----                         \--*  HWINTRINSIC bool   ulong op_Equality
N008 ( 12, 10) [000032] ---X--?----                            +--*  HWINTRINSIC simd16 ulong Xor
N006 (  8,  7) [000030] ---X--?----                            |  +--*  HWINTRINSIC simd16 ulong Or
N004 (  4,  4) [000028] ---X--?----                            |  |  +--*  IND       simd16
N003 (  2,  2) [000025] ------?N---                            |  |  |  \--*  ADD       byref 
N001 (  1,  1) [000009] ------?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         u:1 (last use)
N002 (  1,  1) [000023] ------?----                            |  |  |     \--*  CNS_INT   long   12
N005 (  3,  2) [000046] ------?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
N007 (  3,  2) [000047] ------?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
N009 (  1,  2) [000022] ------?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

------------ BB03 [???..???), preds={BB01} succs={BB04}

***** BB03
STMT00005 ( ??? ... ??? )
N003 (  1,  3) [000053] -A------R--                         *  ASG       int   
N002 (  1,  1) [000052] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:2
N001 (  1,  1) [000036] ------?----                         \--*  CNS_INT   int    0

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00006 ( ??? ... ??? )
N005 (  0,  0) [000056] -A------R--                         *  ASG       int   
N004 (  0,  0) [000054] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:1
N003 (  0,  0) [000055] -----------                         \--*  PHI       int   
N001 (  0,  0) [000058] ----------- pred BB02                  +--*  PHI_ARG   int    V03 tmp2         u:3
N002 (  0,  0) [000057] ----------- pred BB03                  \--*  PHI_ARG   int    V03 tmp2         u:2

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method

*************** Finishing PHASE Early Value Propagation [no changes]

*************** Starting PHASE Do value numbering

*************** In fgValueNumber()
Memory Initial Value in BB01 is: $c0
The SSA definition for ByrefExposed (#1) at start of BB01 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB01 is $c0 {InitVal($41)}

***** BB01, STMT00003(before)
N007 (  8,  8) [000049] ---X-------                         *  JTRUE     void  
N006 (  6,  6) [000038] J--X---N---                         \--*  LT        int   
N004 (  4,  4) [000006] ---X-------                            +--*  IND       int   
N003 (  2,  2) [000005] -------N---                            |  \--*  ADD       byref 
N001 (  1,  1) [000003] -----------                            |     +--*  LCL_VAR   ref    V00 arg0         u:1
N002 (  1,  1) [000004] -----------                            |     \--*  CNS_INT   long   8
N005 (  1,  1) [000008] -----------                            \--*  CNS_INT   int    8

N001 [000003]   LCL_VAR   V00 arg0         u:1 => $80 {InitVal($40)}
N002 [000004]   CNS_INT   8 => $100 {LngCns:  8}
N003 [000005]   ADD       => $140 {ADD($80, $100)}
N004 [000006]   IND       => <l:$240 {norm=$180 {ByrefExposedLoad($42, $140, $c0)}, exc=$200 {NullPtrExc($80)}}, c:$241 {norm=$1c0 {MemOpaque:NotInLoop}, exc=$200 {NullPtrExc($80)}}>
N005 [000008]   CNS_INT   8 => $43 {IntCns 8}
N006 [000038]   LT        => <l:$245 {norm=$242 {LT($180, $43)}, exc=$200 {NullPtrExc($80)}}, c:$244 {norm=$243 {LT($1c0, $43)}, exc=$200 {NullPtrExc($80)}}>
N007 [000049]   JTRUE     => $201 {norm=$VN.Void, exc=$200 {NullPtrExc($80)}}

***** BB01, STMT00003(after)
N007 (  8,  8) [000049] ---X-------                         *  JTRUE     void   $201
N006 (  6,  6) [000038] J--X---N---                         \--*  LT        int    <l:$245, c:$244>
N004 (  4,  4) [000006] ---X-------                            +--*  IND       int    <l:$240, c:$241>
N003 (  2,  2) [000005] -------N---                            |  \--*  ADD       byref  $140
N001 (  1,  1) [000003] -----------                            |     +--*  LCL_VAR   ref    V00 arg0         u:1 $80
N002 (  1,  1) [000004] -----------                            |     \--*  CNS_INT   long   8 $100
N005 (  1,  1) [000008] -----------                            \--*  CNS_INT   int    8 $43

finish(BB01).
   Succ(BB02).
     Not yet completed.
     All preds complete, adding to allDone.
   Succ(BB03).
     Not yet completed.
     All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#1) at start of BB03 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB03 is $c0 {InitVal($41)}

***** BB03, STMT00005(before)
N003 (  1,  3) [000053] -A------R--                         *  ASG       int   
N002 (  1,  1) [000052] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:2
N001 (  1,  1) [000036] ------?----                         \--*  CNS_INT   int    0

N001 [000036]   CNS_INT   0 => $40 {IntCns 0}
N002 [000052]   LCL_VAR   V03 tmp2         d:2 => $VN.Void
Tree [000053] assigned VN to local var V03/2: $40 {IntCns 0}
N003 [000053]   ASG       => $VN.Void

***** BB03, STMT00005(after)
N003 (  1,  3) [000053] -A------R--                         *  ASG       int    $VN.Void
N002 (  1,  1) [000052] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:2 $VN.Void
N001 (  1,  1) [000036] ------?----                         \--*  CNS_INT   int    0 $40

finish(BB03).
   Succ(BB04).
     Not yet completed.
     Not all preds complete  Adding to notallDone, if necessary...
       Was necessary.
The SSA definition for ByrefExposed (#1) at start of BB02 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB02 is $c0 {InitVal($41)}

***** BB02, STMT00004(before)
N012 ( 14, 13) [000051] -A-X----R--                         *  ASG       int   
N011 (  1,  1) [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:3
N010 ( 14, 13) [000035] ---X--?----                         \--*  HWINTRINSIC bool   ulong op_Equality
N008 ( 12, 10) [000032] ---X--?----                            +--*  HWINTRINSIC simd16 ulong Xor
N006 (  8,  7) [000030] ---X--?----                            |  +--*  HWINTRINSIC simd16 ulong Or
N004 (  4,  4) [000028] ---X--?----                            |  |  +--*  IND       simd16
N003 (  2,  2) [000025] ------?N---                            |  |  |  \--*  ADD       byref 
N001 (  1,  1) [000009] ------?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         u:1 (last use)
N002 (  1,  1) [000023] ------?----                            |  |  |     \--*  CNS_INT   long   12
N005 (  3,  2) [000046] ------?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
N007 (  3,  2) [000047] ------?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
N009 (  1,  2) [000022] ------?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

N001 [000009]   LCL_VAR   V00 arg0         u:1 (last use) => $80 {InitVal($40)}
N002 [000023]   CNS_INT   12 => $101 {LngCns:  12}
N003 [000025]   ADD       => $141 {ADD($80, $101)}
N004 [000028]   IND       => <l:$300 {norm=$280 {ByrefExposedLoad($44, $141, $c0)}, exc=$200 {NullPtrExc($80)}}, c:$301 {norm=$2c0 {MemOpaque:NotInLoop}, exc=$200 {NullPtrExc($80)}}>
N005 [000046]   CNS_VEC  <0x00200020, 0x00200020, 0x00000020, 0x00000000> => $340 {Simd16Cns[0x00200020, 0x00200020, 0x00000020, 0x00000000]}
    simdTypeVN is $202 {SimdType(simd16, ulong)}
N006 [000030]   HWINTRINSIC => <l:$303 {norm=$281 {HWI_SSE2_Or($280, $340, $202)}, exc=$200 {NullPtrExc($80)}}, c:$302 {norm=$282 {HWI_SSE2_Or($2c0, $340, $202)}, exc=$200 {NullPtrExc($80)}}>
N007 [000047]   CNS_VEC  <0x00740068, 0x00700074, 0x003a0073, 0x002f002f> => $341 {Simd16Cns[0x00740068, 0x00700074, 0x003a0073, 0x002f002f]}
    simdTypeVN is $202 {SimdType(simd16, ulong)}
N008 [000032]   HWINTRINSIC => <l:$305 {norm=$283 {HWI_SSE2_Xor($281, $341, $202)}, exc=$200 {NullPtrExc($80)}}, c:$304 {norm=$284 {HWI_SSE2_Xor($282, $341, $202)}, exc=$200 {NullPtrExc($80)}}>
N009 [000022]   CNS_VEC  <0x00000000, 0x00000000, 0x00000000, 0x00000000> => $342 {Simd16Cns[0x00000000, 0x00000000, 0x00000000, 0x00000000]}
N010 [000035]   HWINTRINSIC => <l:$383 {norm=$380 {HWI_Vector128_op_Equality($283, $342)}, exc=$200 {NullPtrExc($80)}}, c:$382 {norm=$381 {HWI_Vector128_op_Equality($284, $342)}, exc=$200 {NullPtrExc($80)}}>
N011 [000050]   LCL_VAR   V03 tmp2         d:3 => $VN.Void
Tree [000051] assigned VN to local var V03/3: <l:$246 {$380, int <- bool}, c:$247 {$381, int <- bool}>
N012 [000051]   ASG       => $201 {norm=$VN.Void, exc=$200 {NullPtrExc($80)}}

***** BB02, STMT00004(after)
N012 ( 14, 13) [000051] -A-X----R--                         *  ASG       int    $201
N011 (  1,  1) [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:3 $VN.Void
N010 ( 14, 13) [000035] ---X--?----                         \--*  HWINTRINSIC bool   ulong op_Equality <l:$383, c:$382>
N008 ( 12, 10) [000032] ---X--?----                            +--*  HWINTRINSIC simd16 ulong Xor <l:$305, c:$304>
N006 (  8,  7) [000030] ---X--?----                            |  +--*  HWINTRINSIC simd16 ulong Or <l:$303, c:$302>
N004 (  4,  4) [000028] ---X--?----                            |  |  +--*  IND       simd16 <l:$300, c:$301>
N003 (  2,  2) [000025] ------?N---                            |  |  |  \--*  ADD       byref  $141
N001 (  1,  1) [000009] ------?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         u:1 (last use) $80
N002 (  1,  1) [000023] ------?----                            |  |  |     \--*  CNS_INT   long   12 $101
N005 (  3,  2) [000046] ------?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> $340
N007 (  3,  2) [000047] ------?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> $341
N009 (  1,  2) [000022] ------?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000> $342

finish(BB02).
   Succ(BB04).
     Not yet completed.
     All preds complete, adding to allDone.
SSA PHI definition: set VN of local 3/1 to $181 {PhiDef($3, $1, $248)} .
The SSA definition for ByrefExposed (#1) at start of BB04 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB04 is $c0 {InitVal($41)}

***** BB04, STMT00002(before)
N003 (  3,  4) [000045] -----------                         *  RETURN    int   
N002 (  2,  3) [000048] -----------                         \--*  CAST      int <- bool <- int
N001 (  1,  1) [000044] -----------                            \--*  LCL_VAR   int    V03 tmp2         u:1 (last use)

N001 [000044]   LCL_VAR   V03 tmp2         u:1 (last use) => $181 {PhiDef($3, $1, $248)}
N002 [000048]   CAST      => $249 {$181, int <- bool <- int}
N003 [000045]   RETURN    => $VN.Void

***** BB04, STMT00002(after)
N003 (  3,  4) [000045] -----------                         *  RETURN    int    $VN.Void
N002 (  2,  3) [000048] -----------                         \--*  CAST      int <- bool <- int $249
N001 (  1,  1) [000044] -----------                            \--*  LCL_VAR   int    V03 tmp2         u:1 (last use) $181

finish(BB04).

*************** Finishing PHASE Do value numbering
Trees after Do value numbering

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00003 ( ??? ... ??? )
N007 (  8,  8) [000049] ---X-------                         *  JTRUE     void   $201
N006 (  6,  6) [000038] J--X---N---                         \--*  LT        int    <l:$245, c:$244>
N004 (  4,  4) [000006] ---X-------                            +--*  IND       int    <l:$240, c:$241>
N003 (  2,  2) [000005] -------N---                            |  \--*  ADD       byref  $140
N001 (  1,  1) [000003] -----------                            |     +--*  LCL_VAR   ref    V00 arg0         u:1 $80
N002 (  1,  1) [000004] -----------                            |     \--*  CNS_INT   long   8 $100
N005 (  1,  1) [000008] -----------                            \--*  CNS_INT   int    8 $43

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( ??? ... ??? )
N012 ( 14, 13) [000051] -A-X----R--                         *  ASG       int    $201
N011 (  1,  1) [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:3 $VN.Void
N010 ( 14, 13) [000035] ---X--?----                         \--*  HWINTRINSIC bool   ulong op_Equality <l:$383, c:$382>
N008 ( 12, 10) [000032] ---X--?----                            +--*  HWINTRINSIC simd16 ulong Xor <l:$305, c:$304>
N006 (  8,  7) [000030] ---X--?----                            |  +--*  HWINTRINSIC simd16 ulong Or <l:$303, c:$302>
N004 (  4,  4) [000028] ---X--?----                            |  |  +--*  IND       simd16 <l:$300, c:$301>
N003 (  2,  2) [000025] ------?N---                            |  |  |  \--*  ADD       byref  $141
N001 (  1,  1) [000009] ------?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         u:1 (last use) $80
N002 (  1,  1) [000023] ------?----                            |  |  |     \--*  CNS_INT   long   12 $101
N005 (  3,  2) [000046] ------?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> $340
N007 (  3,  2) [000047] ------?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> $341
N009 (  1,  2) [000022] ------?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000> $342

------------ BB03 [???..???), preds={BB01} succs={BB04}

***** BB03
STMT00005 ( ??? ... ??? )
N003 (  1,  3) [000053] -A------R--                         *  ASG       int    $VN.Void
N002 (  1,  1) [000052] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:2 $VN.Void
N001 (  1,  1) [000036] ------?----                         \--*  CNS_INT   int    0 $40

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00006 ( ??? ... ??? )
N005 (  0,  0) [000056] -A------R--                         *  ASG       int    $VN.Void
N004 (  0,  0) [000054] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:1 $VN.Void
N003 (  0,  0) [000055] -----------                         \--*  PHI       int    $181
N001 (  0,  0) [000058] ----------- pred BB02                  +--*  PHI_ARG   int    V03 tmp2         u:3 <l:$246, c:$247>
N002 (  0,  0) [000057] ----------- pred BB03                  \--*  PHI_ARG   int    V03 tmp2         u:2 $40

***** BB04
STMT00002 ( ??? ... ??? )
N003 (  3,  4) [000045] -----------                         *  RETURN    int    $VN.Void
N002 (  2,  3) [000048] -----------                         \--*  CAST      int <- bool <- int $249
N001 (  1,  1) [000044] -----------                            \--*  LCL_VAR   int    V03 tmp2         u:1 (last use) $181

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Hoist loop code

No loops; no hoisting

*************** Finishing PHASE Hoist loop code [no changes]

*************** Starting PHASE VN based copy prop
Copy Assertion for BB01
  curSsaName stack: { }

Copy Assertion for BB04
  curSsaName stack: { 0-[000003]:V00 }

Live vars: {V03} => {}
Copy Assertion for BB03
  curSsaName stack: { 0-[000003]:V00 }

Live vars: {} => {V03}
Copy Assertion for BB02
  curSsaName stack: { 0-[000003]:V00 }

Live vars: {V00} => {}
							Live vars: {} => {V03}

*************** Finishing PHASE VN based copy prop [no changes]

*************** Starting PHASE Redundant branch opts

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

--- Trying RBO in BB01 ---

*************** Finishing PHASE Redundant branch opts [no changes]

*************** Starting PHASE Optimize Valnum CSEs

*************** Finishing PHASE Optimize Valnum CSEs
Trees after Optimize Valnum CSEs

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Assertion prop
GenTreeNode creates assertion:
N004 (  4,  4) [000006] ---X-------                         *  IND       int    <l:$240, c:$241>
In BB01 New Global Constant Assertion: ($80,$0) V00.01 != null, index = #01
GenTreeNode creates assertion:
N007 (  8,  8) [000049] ---X-------                         *  JTRUE     void   $201
In BB01 New Global Constant Assertion: ($243,$40) Const_Loop_Bnd {LT($1c0, $43)} is not  {IntCns 0}, index = #02
GenTreeNode creates assertion:
N007 (  8,  8) [000049] ---X-------                         *  JTRUE     void   $201
In BB01 New Global Constant Assertion: ($243,$40) Const_Loop_Bnd {LT($1c0, $43)} is  {IntCns 0}, index = #03
GenTreeNode creates assertion:
N002 (  2,  3) [000048] -----------                         *  CAST      int <- bool <- int $249
In BB04 New Global Subrange Assertion: ($181,$0) V03.01 in [0..255], index = #04

BB01 valueGen = #01 #03 => BB03 valueGen = #01 #02
BB02 valueGen = #01
BB03 valueGen = #NA
BB04 valueGen = #NA

BB01:
 in   = #NA
 out  = #01 #03
 BB03 = #01 #02
BB02:
 in   = #01 #03
 out  = #01 #03
BB03:
 in   = #01 #02
 out  = #01 #02
BB04:
 in   = #01
 out  = #01

Propagating #NA for BB01, stmt STMT00003, tree [000003], tree -> #NA
Propagating #NA for BB01, stmt STMT00003, tree [000004], tree -> #NA
Propagating #NA for BB01, stmt STMT00003, tree [000005], tree -> #NA
Propagating #NA for BB01, stmt STMT00003, tree [000006], tree -> #01
Propagating #01 for BB01, stmt STMT00003, tree [000008], tree -> #NA
Propagating #01 for BB01, stmt STMT00003, tree [000038], tree -> #NA
Propagating #01 for BB01, stmt STMT00003, tree [000049], tree -> #02
Propagating #01 #03 for BB02, stmt STMT00004, tree [000009], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000023], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000025], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000028], tree -> #01

VN based non-null prop in BB02:
N004 (  4,  4) [000028] ---X--?----                         *  IND       simd16 <l:$300, c:$301>
Propagating #01 #03 for BB02, stmt STMT00004, tree [000046], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000030], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000047], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000032], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000022], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000035], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000050], tree -> #NA
Propagating #01 #03 for BB02, stmt STMT00004, tree [000051], tree -> #NA
Re-morphing this stmt:
STMT00004 ( ??? ... ??? )
N012 ( 14, 13) [000051] -A-X----R--                         *  ASG       int    $201
N011 (  1,  1) [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:3 $VN.Void
N010 ( 14, 13) [000035] ---X--?----                         \--*  HWINTRINSIC bool   ulong op_Equality <l:$383, c:$382>
N008 ( 12, 10) [000032] ---X--?----                            +--*  HWINTRINSIC simd16 ulong Xor <l:$305, c:$304>
N006 (  8,  7) [000030] ---X--?----                            |  +--*  HWINTRINSIC simd16 ulong Or <l:$303, c:$302>
N004 (  4,  4) [000028] n----O?----                            |  |  +--*  IND       simd16 <l:$300, c:$301>
N003 (  2,  2) [000025] ------?N---                            |  |  |  \--*  ADD       byref  $141
N001 (  1,  1) [000009] ------?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         u:1 (last use) $80
N002 (  1,  1) [000023] ------?----                            |  |  |     \--*  CNS_INT   long   12 $101
N005 (  3,  2) [000046] ------?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> $340
N007 (  3,  2) [000047] ------?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> $341
N009 (  1,  2) [000022] ------?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000> $342

optAssertionPropMain morphed tree:
N012 ( 14, 13) [000051] -A---O--R--                         *  ASG       int    $201
N011 (  1,  1) [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:3 $VN.Void
N010 ( 14, 13) [000035] -----O?----                         \--*  HWINTRINSIC bool   ulong op_Equality <l:$383, c:$382>
N008 ( 12, 10) [000032] -----O?----                            +--*  HWINTRINSIC simd16 ulong Xor <l:$305, c:$304>
N006 (  8,  7) [000030] -----O?----                            |  +--*  HWINTRINSIC simd16 ulong Or <l:$303, c:$302>
N004 (  4,  4) [000028] n----O?----                            |  |  +--*  IND       simd16 <l:$300, c:$301>
N003 (  2,  2) [000025] ------?N---                            |  |  |  \--*  ADD       byref  $141
N001 (  1,  1) [000009] ------?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         u:1 (last use) $80
N002 (  1,  1) [000023] ------?----                            |  |  |     \--*  CNS_INT   long   12 $101
N005 (  3,  2) [000046] ------?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> $340
N007 (  3,  2) [000047] ------?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> $341
N009 (  1,  2) [000022] ------?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000> $342

Propagating #01 #02 for BB03, stmt STMT00005, tree [000036], tree -> #NA
Propagating #01 #02 for BB03, stmt STMT00005, tree [000052], tree -> #NA
Propagating #01 #02 for BB03, stmt STMT00005, tree [000053], tree -> #NA
Propagating #01 for BB04, stmt STMT00002, tree [000044], tree -> #NA
Propagating #01 for BB04, stmt STMT00002, tree [000048], tree -> #NA
Propagating #01 for BB04, stmt STMT00002, tree [000045], tree -> #NA

*************** Finishing PHASE Assertion prop
Trees after Assertion prop

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( ??? ... ??? )
N012 ( 14, 13) [000051] -A---O--R--                         *  ASG       int    $201
N011 (  1,  1) [000050] D------N---                         +--*  LCL_VAR   int    V03 tmp2         d:3 $VN.Void
N010 ( 14, 13) [000035] -----O?----                         \--*  HWINTRINSIC bool   ulong op_Equality <l:$383, c:$382>
N008 ( 12, 10) [000032] -----O?----                            +--*  HWINTRINSIC simd16 ulong Xor <l:$305, c:$304>
N006 (  8,  7) [000030] -----O?----                            |  +--*  HWINTRINSIC simd16 ulong Or <l:$303, c:$302>
N004 (  4,  4) [000028] n----O?----                            |  |  +--*  IND       simd16 <l:$300, c:$301>
N003 (  2,  2) [000025] ------?N---                            |  |  |  \--*  ADD       byref  $141
N001 (  1,  1) [000009] ------?----                            |  |  |     +--*  LCL_VAR   ref    V00 arg0         u:1 (last use) $80
N002 (  1,  1) [000023] ------?----                            |  |  |     \--*  CNS_INT   long   12 $101
N005 (  3,  2) [000046] ------?----                            |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> $340
N007 (  3,  2) [000047] ------?----                            |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> $341
N009 (  1,  2) [000022] ------?----                            \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000> $342

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Optimize index checks

*************** Finishing PHASE Optimize index checks [no changes]

*************** Starting PHASE Insert GC Polls

*************** Finishing PHASE Insert GC Polls [no changes]

*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()

optimized 0 BBJ_COND cases, 0 BBJ_RETURN cases in 1 passes

*************** Finishing PHASE Optimize bools
Trees after Optimize bools

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

*************** Starting PHASE Optimize layout

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()

Initial BasicBlocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize layout
Trees after Optimize layout

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method

*************** Finishing PHASE Determine first cold block [no changes]

*************** Starting PHASE Rationalize IR
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N012 ( 14, 13) [000051] DA---O-----                         *  STORE_LCL_VAR int    V03 tmp2         d:3

rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 (  1,  3) [000053] DA---------                         *  STORE_LCL_VAR int    V03 tmp2         d:2

*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i LIR 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i LIR 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i LIR 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}
N001 (  1,  1) [000003] -----------                    t3 =    LCL_VAR   ref    V00 arg0         u:1 $80
N002 (  1,  1) [000004] -----------                    t4 =    CNS_INT   long   8 $100
                                                            /--*  t3     ref    
                                                            +--*  t4     long   
N003 (  2,  2) [000005] -------N---                    t5 = *  ADD       byref  $140
                                                            /--*  t5     byref  
N004 (  4,  4) [000006] ---X-------                    t6 = *  IND       int    <l:$240, c:$241>
N005 (  1,  1) [000008] -----------                    t8 =    CNS_INT   int    8 $43
                                                            /--*  t6     int    
                                                            +--*  t8     int    
N006 (  6,  6) [000038] J--X---N---                   t38 = *  LT        int    <l:$245, c:$244>
                                                            /--*  t38    int    
N007 (  8,  8) [000049] ---X-------                         *  JTRUE     void   $201

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}
N001 (  1,  1) [000009] ------?----                    t9 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
N002 (  1,  1) [000023] ------?----                   t23 =    CNS_INT   long   12 $101
                                                            /--*  t9     ref    
                                                            +--*  t23    long   
N003 (  2,  2) [000025] ------?N---                   t25 = *  ADD       byref  $141
                                                            /--*  t25    byref  
N004 (  4,  4) [000028] n----O?----                   t28 = *  IND       simd16 <l:$300, c:$301>
N005 (  3,  2) [000046] ------?----                   t46 =    CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> $340
                                                            /--*  t28    simd16 
                                                            +--*  t46    simd16 
N006 (  8,  7) [000030] -----O?----                   t30 = *  HWINTRINSIC simd16 ulong Or <l:$303, c:$302>
N007 (  3,  2) [000047] ------?----                   t47 =    CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> $341
                                                            /--*  t30    simd16 
                                                            +--*  t47    simd16 
N008 ( 12, 10) [000032] -----O?----                   t32 = *  HWINTRINSIC simd16 ulong Xor <l:$305, c:$304>
N009 (  1,  2) [000022] ------?----                   t22 =    CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000> $342
                                                            /--*  t32    simd16 
                                                            +--*  t22    simd16 
N010 ( 14, 13) [000035] -----O?----                   t35 = *  HWINTRINSIC bool   ulong op_Equality <l:$383, c:$382>
                                                            /--*  t35    bool   
N012 ( 14, 13) [000051] DA---O-----                         *  STORE_LCL_VAR int    V03 tmp2         d:3

------------ BB03 [???..???), preds={BB01} succs={BB04}
N001 (  1,  1) [000036] ------?----                   t36 =    CNS_INT   int    0 $40
                                                            /--*  t36    int    
N003 (  1,  3) [000053] DA---------                         *  STORE_LCL_VAR int    V03 tmp2         d:2

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}
N001 (  1,  1) [000044] -----------                   t44 =    LCL_VAR   int    V03 tmp2         u:1 (last use) $181
                                                            /--*  t44    int    
N002 (  2,  3) [000048] -----------                   t48 = *  CAST      int <- bool <- int $249
                                                            /--*  t48    int    
N003 (  3,  4) [000045] -----------                         *  RETURN    int    $VN.Void

*************** Starting PHASE Do 'simple' lowering

*************** Finishing PHASE Do 'simple' lowering [no changes]

*************** Starting PHASE Lowering nodeinfo
Addressing mode:
  Base
    N001 (  1,  1) [000003] -----------                         *  LCL_VAR   ref    V00 arg0         u:1 $80
  + 8
Removing unused node:
  N002 (  1,  1) [000004] -c---------                         *  CNS_INT   long   8 $100
New addressing mode node:
  N003 (  2,  2) [000005] -----------                         *  LEA(b+8)  byref

Addressing mode:
  Base
    N001 (  1,  1) [000009] ------?----                         *  LCL_VAR   ref    V00 arg0         u:1 (last use) $80
  + 12
Removing unused node:
  N002 (  1,  1) [000023] -c----?----                         *  CNS_INT   long   12 $101
New addressing mode node:
  N003 (  2,  2) [000025] ------?----                         *  LEA(b+12) byref

Notify VM instruction set (SSE41) must be supported.

lvaGrabTemp returning 4 (V04 rat0) called for ReplaceWithLclVar is creating a new local variable.
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
               [000061] DA---O-----                         *  STORE_LCL_VAR simd16 V04 rat0

ReplaceWithLclVar created store :
               [000061] DA---O-----                         *  STORE_LCL_VAR simd16 V04 rat0         
lowering store lcl var/field (before):
N001 (  1,  1) [000009] ------?----                    t9 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
                                                            /--*  t9     ref    
N003 (  2,  2) [000025] -c----?----                   t25 = *  LEA(b+12) byref 
                                                            /--*  t25    byref  
N004 (  4,  4) [000028] n----O?----                   t28 = *  IND       simd16 <l:$300, c:$301>
N005 (  3,  2) [000046] -c----?----                   t46 =    CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> $340
                                                            /--*  t28    simd16 
                                                            +--*  t46    simd16 
N006 (  8,  7) [000030] -----O?----                   t30 = *  HWINTRINSIC simd16 ulong Or <l:$303, c:$302>
N007 (  3,  2) [000047] -c----?----                   t47 =    CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> $341
                                                            /--*  t30    simd16 
                                                            +--*  t47    simd16 
N008 ( 12, 10) [000032] -----O?N---                   t32 = *  HWINTRINSIC simd16 ulong Xor <l:$305, c:$304>
                                                            /--*  t32    simd16 
               [000061] DA---O-----                         *  STORE_LCL_VAR simd16 V04 rat0

lowering store lcl var/field (after):
N001 (  1,  1) [000009] ------?----                    t9 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
                                                            /--*  t9     ref    
N003 (  2,  2) [000025] -c----?----                   t25 = *  LEA(b+12) byref 
                                                            /--*  t25    byref  
N004 (  4,  4) [000028] n----O?----                   t28 = *  IND       simd16 <l:$300, c:$301>
N005 (  3,  2) [000046] -c----?----                   t46 =    CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> $340
                                                            /--*  t28    simd16 
                                                            +--*  t46    simd16 
N006 (  8,  7) [000030] -----O?----                   t30 = *  HWINTRINSIC simd16 ulong Or <l:$303, c:$302>
N007 (  3,  2) [000047] -c----?----                   t47 =    CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> $341
                                                            /--*  t30    simd16 
                                                            +--*  t47    simd16 
N008 ( 12, 10) [000032] -----O?N---                   t32 = *  HWINTRINSIC simd16 ulong Xor <l:$305, c:$304>
                                                            /--*  t32    simd16 
               [000061] DA---O-----                         *  STORE_LCL_VAR simd16 V04 rat0

lowering store lcl var/field (before):
               [000064] -----------                   t64 =    SETCC     int    cond=UEQ
                                                            /--*  t64    int    
N012 ( 14, 13) [000051] DA---O-----                         *  STORE_LCL_VAR int    V03 tmp2         d:3

lowering store lcl var/field (after):
               [000064] -----------                   t64 =    SETCC     int    cond=UEQ
                                                            /--*  t64    int    
N012 ( 14, 13) [000051] DA---O-----                         *  STORE_LCL_VAR int    V03 tmp2         d:3

lowering store lcl var/field (before):
N001 (  1,  1) [000036] ------?----                   t36 =    CNS_INT   int    0 $40
                                                            /--*  t36    int    
N003 (  1,  3) [000053] DA---------                         *  STORE_LCL_VAR int    V03 tmp2         d:2

lowering store lcl var/field (after):
N001 (  1,  1) [000036] ------?----                   t36 =    CNS_INT   int    0 $40
                                                            /--*  t36    int    
N003 (  1,  3) [000053] DA---------                         *  STORE_LCL_VAR int    V03 tmp2         d:2

lowering GT_RETURN
N003 (  3,  4) [000045] -----------                         *  RETURN    int    $VN.Void
============Lower has completed modifying nodes.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i LIR 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i LIR 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i LIR 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}
N001 (  1,  1) [000003] -----------                    t3 =    LCL_VAR   ref    V00 arg0         u:1 $80
                                                            /--*  t3     ref    
N003 (  2,  2) [000005] -c---------                    t5 = *  LEA(b+8)  byref 
                                                            /--*  t5     byref  
N004 (  4,  4) [000006] -c-X-------                    t6 = *  IND       int    <l:$240, c:$241>
N005 (  1,  1) [000008] -c---------                    t8 =    CNS_INT   int    8 $43
                                                            /--*  t6     int    
                                                            +--*  t8     int    
N006 (  6,  6) [000038] J--X---N---                         *  LT        void   <l:$245, c:$244>
N007 (  8,  8) [000049] ---X-------                         *  JTRUE     void   $201

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}
N001 (  1,  1) [000009] ------?----                    t9 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
                                                            /--*  t9     ref    
N003 (  2,  2) [000025] -c----?----                   t25 = *  LEA(b+12) byref 
                                                            /--*  t25    byref  
N004 (  4,  4) [000028] n----O?----                   t28 = *  IND       simd16 <l:$300, c:$301>
N005 (  3,  2) [000046] -c----?----                   t46 =    CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> $340
                                                            /--*  t28    simd16 
                                                            +--*  t46    simd16 
N006 (  8,  7) [000030] -----O?----                   t30 = *  HWINTRINSIC simd16 ulong Or <l:$303, c:$302>
N007 (  3,  2) [000047] -c----?----                   t47 =    CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> $341
                                                            /--*  t30    simd16 
                                                            +--*  t47    simd16 
N008 ( 12, 10) [000032] -----O?N---                   t32 = *  HWINTRINSIC simd16 ulong Xor <l:$305, c:$304>
                                                            /--*  t32    simd16 
               [000061] DA---O-----                         *  STORE_LCL_VAR simd16 V04 rat0         
               [000062] -----------                   t62 =    LCL_VAR   simd16 V04 rat0         
               [000063] -----------                   t63 =    LCL_VAR   simd16 V04 rat0         
                                                            /--*  t62    simd16 
                                                            +--*  t63    simd16 
N010 ( 14, 13) [000035] -----O?----                         *  HWINTRINSIC void   ulong PTEST <l:$383, c:$382>
               [000064] -----------                   t64 =    SETCC     int    cond=UEQ
                                                            /--*  t64    int    
N012 ( 14, 13) [000051] DA---O-----                         *  STORE_LCL_VAR int    V03 tmp2         d:3

-------------------------------------------------------------------------------------------------------------------

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt =  1, refCntWtd = 1   
New refCnts for V00: refCnt =  2, refCntWtd = 1.25
New refCnts for V04: refCnt =  1, refCntWtd = 0.50
New refCnts for V04: refCnt =  2, refCntWtd = 1   
New refCnts for V04: refCnt =  3, refCntWtd = 1.50
New refCnts for V03: refCnt =  1, refCntWtd = 0.50
New refCnts for V03: refCnt =  2, refCntWtd = 1   
New refCnts for V03: refCnt =  3, refCntWtd = 3

*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt =  3, refCntWtd = 2.25
New refCnts for V00: refCnt =  4, refCntWtd = 3.25
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
;  V00 arg0              ref  class-hnd single-def
;  V01 OutArgs        lclBlk <0>  "OutgoingArgSpace"
;  V02 tmp1              ref  single-def "spilling varStr"
;  V03 tmp2              int  "spilling unroll qmark"
;  V04 rat0           simd16  "ReplaceWithLclVar is creating a new local variable"
In fgLocalVarLivenessInit
Tracked variable (3 out of 5) table:
V00 arg0          [   ref]: refCnt =    4, refCntWtd =   3.25
V03 tmp2          [   int]: refCnt =    3, refCntWtd =   3   
V04 rat0          [simd16]: refCnt =    3, refCntWtd =   1.50

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00} + ByrefExposed + GcHeap
     DEF(0)={   }

BB02 USE(1)={V00        } + ByrefExposed + GcHeap
     DEF(2)={    V03 V04}

BB03 USE(0)={   }
     DEF(1)={V03}

BB04 USE(1)={V03}
     DEF(0)={   }

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(1)={V00} + ByrefExposed + GcHeap

BB02 IN (1)={V00    } + ByrefExposed + GcHeap
     OUT(1)={    V03}

BB03 IN (0)={   }
     OUT(1)={V03}

BB04 IN (1)={V03}
     OUT(0)={   }

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i LIR 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i LIR 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i LIR 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgRemoveDeadBlocks()
Removing unreachable blocks for fgRemoveDeadBlocks iteration #1
*************** In fgDebugCheckBBlist

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt =  3, refCntWtd = 2.25
New refCnts for V00: refCnt =  4, refCntWtd = 3.25

*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i LIR 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i LIR 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i LIR 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}
N001 (  1,  1) [000009] ------?----                    t9 =    LCL_VAR   ref    V00 arg0         u:1 (last use) $80
                                                            /--*  t9     ref    
N003 (  2,  2) [000025] -c----?----                   t25 = *  LEA(b+12) byref 
                                                            /--*  t25    byref  
N004 (  4,  4) [000028] n----O?----                   t28 = *  IND       simd16 <l:$300, c:$301>
N005 (  3,  2) [000046] -c----?----                   t46 =    CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> $340
                                                            /--*  t28    simd16 
                                                            +--*  t46    simd16 
N006 (  8,  7) [000030] -----O?----                   t30 = *  HWINTRINSIC simd16 ulong Or <l:$303, c:$302>
N007 (  3,  2) [000047] -c----?----                   t47 =    CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> $341
                                                            /--*  t30    simd16 
                                                            +--*  t47    simd16 
N008 ( 12, 10) [000032] -----O?N---                   t32 = *  HWINTRINSIC simd16 ulong Xor <l:$305, c:$304>
                                                            /--*  t32    simd16 
               [000061] DA---O-----                         *  STORE_LCL_VAR simd16 V04 rat0         
               [000062] -----------                   t62 =    LCL_VAR   simd16 V04 rat0         
               [000063] -----------                   t63 =    LCL_VAR   simd16 V04 rat0          (last use)
                                                            /--*  t62    simd16 
                                                            +--*  t63    simd16 
N010 ( 14, 13) [000035] -----O?----                         *  HWINTRINSIC void   ulong PTEST <l:$383, c:$382>
               [000064] -----------                   t64 =    SETCC     int    cond=UEQ
                                                            /--*  t64    int    
N012 ( 14, 13) [000051] DA---O-----                         *  STORE_LCL_VAR int    V03 tmp2         d:3

*************** Starting PHASE Calculate stack level slots

*************** Finishing PHASE Calculate stack level slots [no changes]

*************** Starting PHASE Linear scan register alloc
Clearing modified regs.

buildIntervals ========

-----------------
LIVENESS:
-----------------
BB01
use: {V00}
def: {}
 in: {V00}
out: {V00}
BB02
use: {V00}
def: {V03 V04}
 in: {V00}
out: {V03}
BB03
use: {}
def: {V03}
 in: {}
out: {V03}
BB04
use: {V03}
def: {}
 in: {V03}
out: {}
Interval  0: ref RefPositions {} physReg:NA Preferences=[allInt]
  Interval  0: (V00) ref RefPositions {} physReg:NA Preferences=[allInt]
Interval  1: int RefPositions {} physReg:NA Preferences=[allInt]
  Interval  1: (V03) int RefPositions {} physReg:NA Preferences=[allInt]
Interval  2: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
  Interval  2: (V04) simd16 RefPositions {} physReg:NA Preferences=[allFloat]

FP callee save candidate vars: None

floatVarCount = 1; hasLoops = false, singleExit = true
TUPLE STYLE DUMP BEFORE LSRA
Start LSRA Block Sequence: 
Current block: BB01
	Succ block: BB02, Criteria: weight, Worklist: [BB02 ]
	Succ block: BB03, Criteria: bbNum, Worklist: [BB02 BB03 ]
Current block: BB02
	Succ block: BB04, Criteria: weight, Worklist: [BB03 BB04 ]
Current block: BB03
Current block: BB04
Final LSRA Block Sequence:
BB01 (  1   )
BB02 (  0.25)
BB03 (  0.25)
BB04 (  1   )

BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
  N001.                    V00(t3)
  N003. t5              =  LEA(b+8) ; t3
  N004. t6              =  IND      ; t5
  N005.                    CNS_INT   8
  N006.                    LT       ; t6
  N007.                    JTRUE

BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}
=====
  N001.                    V00(t9*)
  N003. t25             =  LEA(b+12); t9*
  N004. t28             =  IND      ; t25
  N005.                    CNS_VEC  <0x00200020, 0x00200020, 0x00000020, 0x00000000>
  N006. t30             =  HWINTRINSIC; t28
  N007.                    CNS_VEC  <0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
  N008. t32             =  HWINTRINSIC; t30
  N000.                    V04(t61); t32
  N000.                    V04(t62)
  N000.                    V04(t63*)
  N010.                    HWINTRINSIC; t62,t63*
  N000. t64             =  SETCC     cond=UEQ
  N012.                    V03(t51); t64

BB03 [???..???), preds={BB01} succs={BB04}
=====
  N001. t36             =  CNS_INT   0
  N003.                    V03(t53); t36

BB04 [???..00D) (return), preds={BB02,BB03} succs={}
=====
  N001.                    V03(t44*)
  N002. t48             =  CAST     ; t44*
  N003.                    RETURN   ; t48

buildIntervals second part ========
Int arg V00 in reg rcx
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed wt=100.00>

NEW BLOCK BB01
<RefPosition #1   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N003 (  1,  1) [000003] -----------                         *  LCL_VAR   ref    V00 arg0         u:1 NA REG NA $80

DefList: {  }
N005 (  2,  2) [000005] -c---------                         *  LEA(b+8)  byref  REG NA
Contained
DefList: {  }
N007 (  4,  4) [000006] -c-X-------                         *  IND       int    REG NA <l:$240, c:$241>
Contained
DefList: {  }
N009 (  1,  1) [000008] -c---------                         *  CNS_INT   int    8 REG NA $43
Contained
DefList: {  }
N011 (  6,  6) [000038] J--X---N---                         *  LT        void   REG NA <l:$245, c:$244>
<RefPosition #2   @11  RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=325.00>

DefList: {  }
N013 (  8,  8) [000049] ---X-------                         *  JTRUE     void   REG NA $201

CHECKING LAST USES for BB01, liveout={V00}
==============================
use: {V00}
def: {}

NEW BLOCK BB02

Setting BB01 as the predecessor for determining incoming variable registers of BB02
<RefPosition #3   @15  RefTypeBB BB02 regmask=[] minReg=1 wt=25.00>

DefList: {  }
N017 (  1,  1) [000009] ------?----                         *  LCL_VAR   ref    V00 arg0         u:1 NA (last use) REG NA $80

DefList: {  }
N019 (  2,  2) [000025] -c----?----                         *  LEA(b+12) byref  REG NA
Contained
DefList: {  }
N021 (  4,  4) [000028] n----O?----                         *  IND       simd16 REG NA <l:$300, c:$301>
<RefPosition #4   @21  RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last wt=325.00>
Interval  3: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #5   @22  RefTypeDef <Ivl:3> IND BB02 regmask=[allFloat] minReg=1 wt=100.00>

DefList: { N021.t28. IND }
N023 (  3,  2) [000046] -c----?----                         *  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> REG NA $340
Contained
DefList: { N021.t28. IND }
N025 (  8,  7) [000030] -----O?----                         *  HWINTRINSIC simd16 ulong Or REG NA <l:$303, c:$302>
<RefPosition #6   @25  RefTypeUse <Ivl:3> BB02 regmask=[allFloat] minReg=1 last wt=25.00>
Interval  4: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #7   @26  RefTypeDef <Ivl:4> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=100.00>

DefList: { N025.t30. HWINTRINSIC }
N027 (  3,  2) [000047] -c----?----                         *  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> REG NA $341
Contained
DefList: { N025.t30. HWINTRINSIC }
N029 ( 12, 10) [000032] -----O?N---                         *  HWINTRINSIC simd16 ulong Xor REG NA <l:$305, c:$304>
<RefPosition #8   @29  RefTypeUse <Ivl:4> BB02 regmask=[allFloat] minReg=1 last wt=25.00>
Interval  5: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #9   @30  RefTypeDef <Ivl:5> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=100.00>

DefList: { N029.t32. HWINTRINSIC }
N031 (???,???) [000061] DA---O-----                         *  STORE_LCL_VAR simd16 V04 rat0          NA REG NA
<RefPosition #10  @31  RefTypeUse <Ivl:5> BB02 regmask=[allFloat] minReg=1 last wt=25.00>
Assigning related <V04/L2> to <I5>
<RefPosition #11  @32  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=150.00>

DefList: {  }
N033 (???,???) [000062] -----------                         *  LCL_VAR   simd16 V04 rat0          NA REG NA

DefList: {  }
N035 (???,???) [000063] -----------                         *  LCL_VAR   simd16 V04 rat0          NA (last use) REG NA

DefList: {  }
N037 ( 14, 13) [000035] -----O?----                         *  HWINTRINSIC void   ulong PTEST REG NA <l:$383, c:$382>
<RefPosition #12  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=150.00>
<RefPosition #13  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=150.00>

DefList: {  }
N039 (???,???) [000064] -----------                         *  SETCC     int    cond=UEQ REG NA
Interval  6: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #14  @40  RefTypeDef <Ivl:6> SETCC BB02 regmask=[allInt] minReg=1 wt=100.00>

DefList: { N039.t64. SETCC }
N041 ( 14, 13) [000051] DA---O-----                         *  STORE_LCL_VAR int    V03 tmp2         d:3 NA REG NA
<RefPosition #15  @41  RefTypeUse <Ivl:6> BB02 regmask=[allInt] minReg=1 last wt=25.00>
Assigning related <V03/L1> to <I6>
<RefPosition #16  @42  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last wt=300.00>

CHECKING LAST USES for BB02, liveout={V03}
==============================
use: {V00}
def: {V03 V04}

NEW BLOCK BB03

Setting BB01 as the predecessor for determining incoming variable registers of BB03
<RefPosition #17  @43  RefTypeBB BB03 regmask=[] minReg=1 wt=25.00>

DefList: {  }
N045 (  1,  1) [000036] ------?----                         *  CNS_INT   int    0 REG NA $40
Interval  7: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #18  @46  RefTypeDef <Ivl:7> CNS_INT BB03 regmask=[allInt] minReg=1 wt=100.00>

DefList: { N045.t36. CNS_INT }
N047 (  1,  3) [000053] DA---------                         *  STORE_LCL_VAR int    V03 tmp2         d:2 NA REG NA
<RefPosition #19  @47  RefTypeUse <Ivl:7> BB03 regmask=[allInt] minReg=1 last wt=25.00>
Assigning related <V03/L1> to <I7>
<RefPosition #20  @48  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=300.00>

CHECKING LAST USES for BB03, liveout={V03}
==============================
use: {}
def: {V03}

NEW BLOCK BB04

Setting BB02 as the predecessor for determining incoming variable registers of BB04
<RefPosition #21  @49  RefTypeBB BB04 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N051 (  1,  1) [000044] -----------                         *  LCL_VAR   int    V03 tmp2         u:1 NA (last use) REG NA $181

DefList: {  }
N053 (  2,  3) [000048] -----------                         *  CAST      int <- bool <- int REG NA $249
<RefPosition #22  @53  RefTypeUse <Ivl:1 V03> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=300.00>
Interval  8: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #23  @54  RefTypeDef <Ivl:8> CAST BB04 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N053.t48. CAST }
N055 (  3,  4) [000045] -----------                         *  RETURN    int    REG NA $VN.Void
<RefPosition #24  @55  RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #25  @55  RefTypeUse <Ivl:8> BB04 regmask=[rax] minReg=1 last fixed wt=100.00>

CHECKING LAST USES for BB04, liveout={}
==============================
use: {V03}
def: {}

Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval  0: (V00) ref RefPositions {#0@0 #2@11 #4@21} physReg:rcx Preferences=[rcx]
Interval  1: (V03) int RefPositions {#16@42 #20@48 #22@53} physReg:NA Preferences=[allInt]
Interval  2: (V04) simd16 RefPositions {#11@32 #12@37 #13@37} physReg:NA Preferences=[allFloat]
Interval  3: simd16 RefPositions {#5@22 #6@25} physReg:NA Preferences=[allFloat]
Interval  4: simd16 RefPositions {#7@26 #8@29} physReg:NA Preferences=[allFloat]
Interval  5: simd16 RefPositions {#9@30 #10@31} physReg:NA Preferences=[allFloat] RelatedInterval <V04/L2>
Interval  6: int RefPositions {#14@40 #15@41} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval  7: int (constant) RefPositions {#18@46 #19@47} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval  8: int RefPositions {#23@54 #25@55} physReg:NA Preferences=[rax]

------------
REFPOSITIONS BEFORE VALIDATING INTERVALS: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #2   @11  RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=325.00>
<RefPosition #3   @15  RefTypeBB BB02 regmask=[] minReg=1 wt=25.00>
<RefPosition #4   @21  RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last wt=325.00>
<RefPosition #5   @22  RefTypeDef <Ivl:3> IND BB02 regmask=[allFloat] minReg=1 wt=100.00>
<RefPosition #6   @25  RefTypeUse <Ivl:3> BB02 regmask=[allFloat] minReg=1 last wt=25.00>
<RefPosition #7   @26  RefTypeDef <Ivl:4> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=100.00>
<RefPosition #8   @29  RefTypeUse <Ivl:4> BB02 regmask=[allFloat] minReg=1 last wt=25.00>
<RefPosition #9   @30  RefTypeDef <Ivl:5> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=100.00>
<RefPosition #10  @31  RefTypeUse <Ivl:5> BB02 regmask=[allFloat] minReg=1 last wt=25.00>
<RefPosition #11  @32  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=150.00>
<RefPosition #12  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=150.00>
<RefPosition #13  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=150.00>
<RefPosition #14  @40  RefTypeDef <Ivl:6> SETCC BB02 regmask=[allInt] minReg=1 wt=100.00>
<RefPosition #15  @41  RefTypeUse <Ivl:6> BB02 regmask=[allInt] minReg=1 last wt=25.00>
<RefPosition #16  @42  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #17  @43  RefTypeBB BB03 regmask=[] minReg=1 wt=25.00>
<RefPosition #18  @46  RefTypeDef <Ivl:7> CNS_INT BB03 regmask=[allInt] minReg=1 wt=100.00>
<RefPosition #19  @47  RefTypeUse <Ivl:7> BB03 regmask=[allInt] minReg=1 last wt=25.00>
<RefPosition #20  @48  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #21  @49  RefTypeBB BB04 regmask=[] minReg=1 wt=100.00>
<RefPosition #22  @53  RefTypeUse <Ivl:1 V03> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional wt=300.00>
<RefPosition #23  @54  RefTypeDef <Ivl:8> CAST BB04 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #24  @55  RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #25  @55  RefTypeUse <Ivl:8> BB04 regmask=[rax] minReg=1 last fixed wt=100.00>

------------
REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval)
------------

-----------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @11  RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=325.00>
<RefPosition #4   @21  RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last wt=325.00>
-----------------
<RefPosition #16  @42  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #20  @48  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #22  @53  RefTypeUse <Ivl:1 V03> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional wt=300.00>
-----------------
<RefPosition #11  @32  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=150.00>
<RefPosition #12  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=150.00>
<RefPosition #13  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=150.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:  V00
BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
  N003.                    V00(L0)
  N005.                    LEA(b+8) 
  N007.                    IND      
  N009.                    CNS_INT   8
  N011.                    LT       
                               Use:<V00/L0>(#2)
  N013.                    JTRUE

BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}
=====
  N017.                    V00(L0)
  N019.                    LEA(b+12)
  N021.                    IND      
                               Use:<V00/L0>(#4) *
        Def:<I3>(#5)
  N023.                    CNS_VEC  <0x00200020, 0x00200020, 0x00000020, 0x00000000>
  N025.                    HWINTRINSIC
                               Use:<I3>(#6) *
        Def:<I4>(#7)
  N027.                    CNS_VEC  <0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
  N029.                    HWINTRINSIC
                               Use:<I4>(#8) *
        Def:<I5>(#9) Pref:<V04/L2>
  N031.                    V04(L2)
                               Use:<I5>(#10) *
        Def:<V04/L2>(#11)
  N033.                    V04(L2)
  N035.                    V04(L2)
  N037.                    HWINTRINSIC
                               Use:<V04/L2>(#12)
                               Use:<V04/L2>(#13) *
  N039.                    SETCC     cond=UEQ
        Def:<I6>(#14) Pref:<V03/L1>
  N041.                    V03(L1)
                               Use:<I6>(#15) *
        Def:<V03/L1>(#16)

BB03 [???..???), preds={BB01} succs={BB04}
=====
  N045.                    CNS_INT   0
        Def:<I7>(#18) Pref:<V03/L1>
  N047.                    V03(L1)
                               Use:<I7>(#19) *
        Def:<V03/L1>(#20)

BB04 [???..00D) (return), preds={BB02,BB03} succs={}
=====
  N051.                    V03(L1)
  N053.                    CAST     
                               Use:<V03/L1>(#22) *
        Def:<I8>(#23)
  N055.                    RETURN   
                               Use:<I8>(#25) Fixed:rax(#24) *

Linear scan intervals after buildIntervals:
Interval  0: (V00) ref RefPositions {#0@0 #2@11 #4@21} physReg:rcx Preferences=[rcx]
Interval  1: (V03) int RefPositions {#16@42 #20@48 #22@53} physReg:NA Preferences=[allInt]
Interval  2: (V04) simd16 RefPositions {#11@32 #12@37 #13@37} physReg:NA Preferences=[allFloat]
Interval  3: simd16 RefPositions {#5@22 #6@25} physReg:NA Preferences=[allFloat]
Interval  4: simd16 RefPositions {#7@26 #8@29} physReg:NA Preferences=[allFloat]
Interval  5: simd16 RefPositions {#9@30 #10@31} physReg:NA Preferences=[allFloat] RelatedInterval <V04/L2>
Interval  6: int RefPositions {#14@40 #15@41} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval  7: int (constant) RefPositions {#18@46 #19@47} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval  8: int RefPositions {#23@54 #25@55} physReg:NA Preferences=[rax]

*************** In LinearScan::allocateRegisters()

Linear scan intervals before allocateRegisters:
Interval  0: (V00) ref RefPositions {#0@0 #2@11 #4@21} physReg:rcx Preferences=[rcx]
Interval  1: (V03) int RefPositions {#16@42 #20@48 #22@53} physReg:NA Preferences=[allInt]
Interval  2: (V04) simd16 RefPositions {#11@32 #12@37 #13@37} physReg:NA Preferences=[allFloat]
Interval  3: simd16 RefPositions {#5@22 #6@25} physReg:NA Preferences=[allFloat]
Interval  4: simd16 RefPositions {#7@26 #8@29} physReg:NA Preferences=[allFloat]
Interval  5: simd16 RefPositions {#9@30 #10@31} physReg:NA Preferences=[allFloat] RelatedInterval <V04/L2>
Interval  6: int RefPositions {#14@40 #15@41} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval  7: int (constant) RefPositions {#18@46 #19@47} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval  8: int RefPositions {#23@54 #25@55} physReg:NA Preferences=[rax]

------------
REFPOSITIONS BEFORE ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #2   @11  RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=325.00>
<RefPosition #3   @15  RefTypeBB BB02 regmask=[] minReg=1 wt=25.00>
<RefPosition #4   @21  RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last wt=325.00>
<RefPosition #5   @22  RefTypeDef <Ivl:3> IND BB02 regmask=[allFloat] minReg=1 wt=100.00>
<RefPosition #6   @25  RefTypeUse <Ivl:3> BB02 regmask=[allFloat] minReg=1 last wt=25.00>
<RefPosition #7   @26  RefTypeDef <Ivl:4> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=100.00>
<RefPosition #8   @29  RefTypeUse <Ivl:4> BB02 regmask=[allFloat] minReg=1 last wt=25.00>
<RefPosition #9   @30  RefTypeDef <Ivl:5> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=100.00>
<RefPosition #10  @31  RefTypeUse <Ivl:5> BB02 regmask=[allFloat] minReg=1 last wt=25.00>
<RefPosition #11  @32  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=150.00>
<RefPosition #12  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=150.00>
<RefPosition #13  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=150.00>
<RefPosition #14  @40  RefTypeDef <Ivl:6> SETCC BB02 regmask=[allInt] minReg=1 wt=100.00>
<RefPosition #15  @41  RefTypeUse <Ivl:6> BB02 regmask=[allInt] minReg=1 last wt=25.00>
<RefPosition #16  @42  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #17  @43  RefTypeBB BB03 regmask=[] minReg=1 wt=25.00>
<RefPosition #18  @46  RefTypeDef <Ivl:7> CNS_INT BB03 regmask=[allInt] minReg=1 wt=100.00>
<RefPosition #19  @47  RefTypeUse <Ivl:7> BB03 regmask=[allInt] minReg=1 last wt=25.00>
<RefPosition #20  @48  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #21  @49  RefTypeBB BB04 regmask=[] minReg=1 wt=100.00>
<RefPosition #22  @53  RefTypeUse <Ivl:1 V03> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional wt=300.00>
<RefPosition #23  @54  RefTypeDef <Ivl:8> CAST BB04 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #24  @55  RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #25  @55  RefTypeUse <Ivl:8> BB04 regmask=[rax] minReg=1 last fixed wt=100.00>

VAR REFPOSITIONS BEFORE ALLOCATION
--- V00  (Interval 0)
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @11  RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=325.00>
<RefPosition #4   @21  RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last wt=325.00>
--- V01
--- V02
--- V03  (Interval 1)
<RefPosition #16  @42  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #20  @48  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #22  @53  RefTypeUse <Ivl:1 V03> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional wt=300.00>
--- V04  (Interval 2)
<RefPosition #11  @32  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=150.00>
<RefPosition #12  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=150.00>
<RefPosition #13  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=150.00>

Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.

---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |mm0 |mm1 |mm2 |mm6 |mm7 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
                                 |    |V0 a|    |    |    |    |    |    |    |    |    |    |    |    |
 0.#0  V0   Parm   Keep     rcx  |    |V0 a|    |    |    |    |    |    |    |    |    |    |    |    |
 1.#1  BB1 PredBB0               |    |V0 a|    |    |    |    |    |    |    |    |    |    |    |    |
11.#2  V0   Use    Keep     rcx  |    |V0 a|    |    |    |    |    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |mm0 |mm1 |mm2 |mm6 |mm7 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
15.#3  BB2 PredBB1               |    |V0 a|    |    |    |    |    |    |    |    |    |    |    |    |
21.#4  V0   Use *  Keep     rcx  |    |V0 a|    |    |    |    |    |    |    |    |    |    |    |    |
22.#5  I3   Def    ORDER(A) mm0  |    |    |    |    |    |    |    |    |    |I3 a|    |    |    |    |
25.#6  I3   Use *  Keep     mm0  |    |    |    |    |    |    |    |    |    |I3 a|    |    |    |    |
26.#7  I4   Def    ORDER(A) mm0  |    |    |    |    |    |    |    |    |    |I4 a|    |    |    |    |
29.#8  I4   Use *  Keep     mm0  |    |    |    |    |    |    |    |    |    |I4 a|    |    |    |    |
30.#9  I5   Def    ORDER(A) mm0  |    |    |    |    |    |    |    |    |    |I5 a|    |    |    |    |
31.#10 I5   Use *  Keep     mm0  |    |    |    |    |    |    |    |    |    |I5 a|    |    |    |    |
32.#11 V4   Def    COVRS(A) mm0  |    |    |    |    |    |    |    |    |    |V4 a|    |    |    |    |
37.#12 V4   Use    Keep     mm0  |    |    |    |    |    |    |    |    |    |V4 a|    |    |    |    |
37.#13 V4   Use *  Keep     mm0  |    |    |    |    |    |    |    |    |    |V4 a|    |    |    |    |
40.#14 I6   Def    BSFIT(A) rax  |I6 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
41.#15 I6   Use *  Keep     rax  |I6 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
42.#16 V3   Def    COVRS(A) rax  |V3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |mm0 |mm1 |mm2 |mm6 |mm7 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
43.#17 BB3 PredBB1               |V3 i|    |    |    |    |    |    |    |    |    |    |    |    |    |
46.#18 C7   Def    RELPR(A) rax  |C7 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
47.#19 C7   Use *  Keep     rax  |C7 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
48.#20 V3   Def    Restr    rax  |V3 i|    |    |    |    |    |    |    |    |    |    |    |    |    |
                   THISA(A) rax  |V3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |mm0 |mm1 |mm2 |mm6 |mm7 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
49.#21 BB4 PredBB2               |V3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
53.#22 V3   Use *  Keep     rax  |V3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
54.#23 I8   Def    Alloc    rax  |I8 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
55.#24 rax  Fixd   Keep     rax  |I8 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
55.#25 I8   Use *  Keep     rax  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |

------------
REFPOSITIONS AFTER ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1   @1   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #2   @11  RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=325.00>
<RefPosition #3   @15  RefTypeBB BB02 regmask=[] minReg=1 wt=25.00>
<RefPosition #4   @21  RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[rcx] minReg=1 last wt=325.00>
<RefPosition #5   @22  RefTypeDef <Ivl:3> IND BB02 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #6   @25  RefTypeUse <Ivl:3> BB02 regmask=[mm0] minReg=1 last wt=25.00>
<RefPosition #7   @26  RefTypeDef <Ivl:4> HWINTRINSIC BB02 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #8   @29  RefTypeUse <Ivl:4> BB02 regmask=[mm0] minReg=1 last wt=25.00>
<RefPosition #9   @30  RefTypeDef <Ivl:5> HWINTRINSIC BB02 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #10  @31  RefTypeUse <Ivl:5> BB02 regmask=[mm0] minReg=1 last wt=25.00>
<RefPosition #11  @32  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB02 regmask=[mm0] minReg=1 wt=150.00>
<RefPosition #12  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[mm0] minReg=1 wt=150.00>
<RefPosition #13  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[mm0] minReg=1 last wt=150.00>
<RefPosition #14  @40  RefTypeDef <Ivl:6> SETCC BB02 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #15  @41  RefTypeUse <Ivl:6> BB02 regmask=[rax] minReg=1 last wt=25.00>
<RefPosition #16  @42  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #17  @43  RefTypeBB BB03 regmask=[] minReg=1 wt=25.00>
<RefPosition #18  @46  RefTypeDef <Ivl:7> CNS_INT BB03 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #19  @47  RefTypeUse <Ivl:7> BB03 regmask=[rax] minReg=1 last wt=25.00>
<RefPosition #20  @48  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB03 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #21  @49  RefTypeBB BB04 regmask=[] minReg=1 wt=100.00>
<RefPosition #22  @53  RefTypeUse <Ivl:1 V03> LCL_VAR BB04 regmask=[rax] minReg=1 last regOptional wt=300.00>
<RefPosition #23  @54  RefTypeDef <Ivl:8> CAST BB04 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #24  @55  RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #25  @55  RefTypeUse <Ivl:8> BB04 regmask=[rax] minReg=1 last fixed wt=100.00>

VAR REFPOSITIONS AFTER ALLOCATION
--- V00  (Interval 0)
<RefPosition #0   @0   RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2   @11  RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=325.00>
<RefPosition #4   @21  RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[rcx] minReg=1 last wt=325.00>
--- V01
--- V02
--- V03  (Interval 1)
<RefPosition #16  @42  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #20  @48  RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB03 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #22  @53  RefTypeUse <Ivl:1 V03> LCL_VAR BB04 regmask=[rax] minReg=1 last regOptional wt=300.00>
--- V04  (Interval 2)
<RefPosition #11  @32  RefTypeDef <Ivl:2 V04> STORE_LCL_VAR BB02 regmask=[mm0] minReg=1 wt=150.00>
<RefPosition #12  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[mm0] minReg=1 wt=150.00>
<RefPosition #13  @37  RefTypeUse <Ivl:2 V04> LCL_VAR BB02 regmask=[mm0] minReg=1 last wt=150.00>

Active intervals at end of allocation:

-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V03}
Has No Critical Edges

Prior to Resolution

BB01
use: {V00}
def: {}
 in: {V00}
out: {V00}
Var=Reg beg of BB01: V00=rcx 
Var=Reg end of BB01: V00=rcx

BB02
use: {V00}
def: {V03 V04}
 in: {V00}
out: {V03}
Var=Reg beg of BB02: V00=rcx 
Var=Reg end of BB02: V03=rax

BB03
use: {}
def: {V03}
 in: {}
out: {V03}
Var=Reg beg of BB03: none
Var=Reg end of BB03: V03=rax

BB04
use: {V03}
def: {}
 in: {V03}
out: {}
Var=Reg beg of BB04: V03=rax 
Var=Reg end of BB04: none

RESOLVING EDGES
  Set V00 argument initial register to rcx
Trees after linear scan register allocator (LSRA)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i LIR 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i LIR 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i LIR 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}
N003 (  1,  1) [000003] -----------                    t3 =    LCL_VAR   ref    V00 arg0         u:1 rcx REG rcx $80
                                                            /--*  t3     ref    
N005 (  2,  2) [000005] -c---------                    t5 = *  LEA(b+8)  byref  REG NA
                                                            /--*  t5     byref  
N007 (  4,  4) [000006] -c-X-------                    t6 = *  IND       int    REG NA <l:$240, c:$241>
N009 (  1,  1) [000008] -c---------                    t8 =    CNS_INT   int    8 REG NA $43
                                                            /--*  t6     int    
                                                            +--*  t8     int    
N011 (  6,  6) [000038] J--X---N---                         *  LT        void   REG NA <l:$245, c:$244>
N013 (  8,  8) [000049] ---X-------                         *  JTRUE     void   REG NA $201

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}
N017 (  1,  1) [000009] ------?----                    t9 =    LCL_VAR   ref    V00 arg0         u:1 rcx (last use) REG rcx $80
                                                            /--*  t9     ref    
N019 (  2,  2) [000025] -c----?----                   t25 = *  LEA(b+12) byref  REG NA
                                                            /--*  t25    byref  
N021 (  4,  4) [000028] n----O?----                   t28 = *  IND       simd16 REG mm0 <l:$300, c:$301>
N023 (  3,  2) [000046] -c----?----                   t46 =    CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> REG NA $340
                                                            /--*  t28    simd16 
                                                            +--*  t46    simd16 
N025 (  8,  7) [000030] -----O?----                   t30 = *  HWINTRINSIC simd16 ulong Or REG mm0 <l:$303, c:$302>
N027 (  3,  2) [000047] -c----?----                   t47 =    CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> REG NA $341
                                                            /--*  t30    simd16 
                                                            +--*  t47    simd16 
N029 ( 12, 10) [000032] -----O?N---                   t32 = *  HWINTRINSIC simd16 ulong Xor REG mm0 <l:$305, c:$304>
                                                            /--*  t32    simd16 
N031 (???,???) [000061] DA---O-----                         *  STORE_LCL_VAR simd16 V04 rat0          mm0 REG mm0
N033 (???,???) [000062] -----------                   t62 =    LCL_VAR   simd16 V04 rat0          mm0 REG mm0
N035 (???,???) [000063] -----------                   t63 =    LCL_VAR   simd16 V04 rat0          mm0 (last use) REG mm0
                                                            /--*  t62    simd16 
                                                            +--*  t63    simd16 
N037 ( 14, 13) [000035] -----O?----                         *  HWINTRINSIC void   ulong PTEST REG NA <l:$383, c:$382>
N039 (???,???) [000064] -----------                   t64 =    SETCC     int    cond=UEQ REG rax
                                                            /--*  t64    int    
N041 ( 14, 13) [000051] DA---O-----                         *  STORE_LCL_VAR int    V03 tmp2         d:3 rax REG rax

------------ BB03 [???..???), preds={BB01} succs={BB04}
N045 (  1,  1) [000036] ------?----                   t36 =    CNS_INT   int    0 REG rax $40
                                                            /--*  t36    int    
N047 (  1,  3) [000053] DA---------                         *  STORE_LCL_VAR int    V03 tmp2         d:2 rax REG rax

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}
N051 (  1,  1) [000044] -----------                   t44 =    LCL_VAR   int    V03 tmp2         u:1 rax (last use) REG rax $181
                                                            /--*  t44    int    
N053 (  2,  3) [000048] -----------                   t48 = *  CAST      int <- bool <- int REG rax $249
                                                            /--*  t48    int    
N055 (  3,  4) [000045] -----------                         *  RETURN    int    REG NA $VN.Void

-------------------------------------------------------------------------------------------------------------------

Final allocation
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |mm0 |mm1 |mm2 |mm6 |mm7 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
 0.#0  V0   Parm   Alloc    rcx  |    |V0 a|    |    |    |    |    |    |    |    |    |    |    |    |
 1.#1  BB1 PredBB0               |    |V0 a|    |    |    |    |    |    |    |    |    |    |    |    |
11.#2  V0   Use    Keep     rcx  |    |V0 a|    |    |    |    |    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |mm0 |mm1 |mm2 |mm6 |mm7 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
15.#3  BB2 PredBB1               |    |V0 a|    |    |    |    |    |    |    |    |    |    |    |    |
21.#4  V0   Use *  Keep     rcx  |    |V0 i|    |    |    |    |    |    |    |    |    |    |    |    |
22.#5  I3   Def    Alloc    mm0  |    |    |    |    |    |    |    |    |    |I3 a|    |    |    |    |
25.#6  I3   Use *  Keep     mm0  |    |    |    |    |    |    |    |    |    |I3 i|    |    |    |    |
26.#7  I4   Def    Alloc    mm0  |    |    |    |    |    |    |    |    |    |I4 a|    |    |    |    |
29.#8  I4   Use *  Keep     mm0  |    |    |    |    |    |    |    |    |    |I4 i|    |    |    |    |
30.#9  I5   Def    Alloc    mm0  |    |    |    |    |    |    |    |    |    |I5 a|    |    |    |    |
31.#10 I5   Use *  Keep     mm0  |    |    |    |    |    |    |    |    |    |I5 i|    |    |    |    |
32.#11 V4   Def    Alloc    mm0  |    |    |    |    |    |    |    |    |    |V4 a|    |    |    |    |
37.#12 V4   Use    Keep     mm0  |    |    |    |    |    |    |    |    |    |V4 a|    |    |    |    |
37.#13 V4   Use *  Keep     mm0  |    |    |    |    |    |    |    |    |    |V4 i|    |    |    |    |
40.#14 I6   Def    Alloc    rax  |I6 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
41.#15 I6   Use *  Keep     rax  |I6 i|    |    |    |    |    |    |    |    |    |    |    |    |    |
42.#16 V3   Def    Alloc    rax  |V3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |mm0 |mm1 |mm2 |mm6 |mm7 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
43.#17 BB3 PredBB1               |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
46.#18 C7   Def    Alloc    rax  |C7 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
47.#19 C7   Use *  Keep     rax  |C7 i|    |    |    |    |    |    |    |    |    |    |    |    |    |
48.#20 V3   Def    Alloc    rax  |V3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |mm0 |mm1 |mm2 |mm6 |mm7 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
49.#21 BB4 PredBB2               |V3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
53.#22 V3   Use *  Keep     rax  |V3 i|    |    |    |    |    |    |    |    |    |    |    |    |    |
54.#23 I8   Def    Alloc    rax  |I8 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
55.#24 rax  Fixd   Keep     rax  |I8 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
55.#25 I8   Use *  Keep     rax  |I8 i|    |    |    |    |    |    |    |    |    |    |    |    |    |

Recording the maximum number of concurrent spills:

----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars:  3
Total Reg Cand Vars: 3
Total number of Intervals: 8
Total number of RefPositions: 25
Total Number of spill temps created: 0
..........
BB02 [   25.00]: COVERS = 2, BEST_FIT = 1, REG_ORDER = 3
BB03 [   25.00]: THIS_ASSIGNED = 1, RELATED_PREFERENCE = 1
..........
Total SpillCount : 0   Weighted: 0.000000
Total CopyReg : 0   Weighted: 0.000000
Total ResolutionMovs : 0   Weighted: 0.000000
Total SplitEdges : 0   Weighted: 0.000000
..........
Total THIS_ASSIGNED [# 3] : 1   Weighted: 25.000000
Total COVERS [# 4] : 2   Weighted: 50.000000
Total RELATED_PREFERENCE [# 7] : 1   Weighted: 25.000000
Total BEST_FIT [#11] : 1   Weighted: 25.000000
Total REG_ORDER [#13] : 3   Weighted: 75.000000

TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:  V00(rcx)
BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
  N003.                    V00(rcx)
  N005. STK             =  LEA(b+8) ; rcx
  N007. STK             =  IND      ; STK
  N009.                    CNS_INT   8
  N011.                    LT       ; STK
  N013.                    JTRUE    
Var=Reg end of BB01: V00=rcx

BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB02: V00=rcx 
  N017.                    V00(rcx*)
  N019. STK             =  LEA(b+12); rcx*
  N021. mm0             =  IND      ; STK
  N023.                    CNS_VEC  <0x00200020, 0x00200020, 0x00000020, 0x00000000>
  N025. mm0             =  HWINTRINSIC; mm0
  N027.                    CNS_VEC  <0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
  N029. mm0             =  HWINTRINSIC; mm0
* N031.                    V04(mm0); mm0
  N033.                    V04(mm0)
  N035.                    V04(mm0*)
  N037.                    HWINTRINSIC; mm0,mm0*
  N039. rax             =  SETCC     cond=UEQ
* N041.                    V03(rax); rax
Var=Reg end of BB02: V03=rax

BB03 [???..???), preds={BB01} succs={BB04}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB03: none
  N045. rax             =  CNS_INT   0
* N047.                    V03(rax); rax
Var=Reg end of BB03: V03=rax

BB04 [???..00D) (return), preds={BB02,BB03} succs={}
=====
Predecessor for variable locations: BB02
Var=Reg beg of BB04: V03=rax 
  N051.                    V03(rax*)
  N053. rax             =  CAST     ; rax*
  N055.                    RETURN   ; rax
Var=Reg end of BB04: none

*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i LIR 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i LIR 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i LIR 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Place 'align' instructions

*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i LIR 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i LIR 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i LIR 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
  V00(rcx)
Modified regs: [rax rcx mm0]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
--- delta bump 8 for RA
--- delta bump 0 for RSP frame
--- virtual stack offset to actual stack offset delta is 8
-- V00 was 0, now 8
-- V01 was 0, now 8
; Final local variable assignments
;
;  V00 arg0         [V00,T00] (  4,  3.25)     ref  ->  rcx         class-hnd single-def
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [rsp+00H]   "OutgoingArgSpace"
;* V02 tmp1         [V02    ] (  0,  0   )     ref  ->  zero-ref    single-def "spilling varStr"
;  V03 tmp2         [V03,T01] (  3,  3   )     int  ->  rax         "spilling unroll qmark"
;  V04 rat0         [V04,T02] (  3,  1.50)  simd16  ->  mm0         "ReplaceWithLclVar is creating a new local variable"
;
; Lcl frame size = 0
Mark labels for codegen
  BB01 : first block
  BB03 : branch target
  BB04 : branch target
*************** After genMarkLabelsForCodegen()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i label LIR 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i LIR 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i label LIR 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i label LIR 
-----------------------------------------------------------------------------------------------------------------------------------------
Setting stack level from -572662307 to 0

=============== Generating BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03} flags=0x00000000.20010020: i label LIR 
BB01 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(1)={V00} + ByrefExposed + GcHeap

Recording Var Locations at start of BB01
  V00(rcx)
Change life 0000000000000000 {} -> 0000000000000001 {V00}
							V00 in reg rcx is becoming live  [------]
							Live regs: 00000000 {} => 00000002 {rcx}
New debug range: first
							Live regs: (unchanged) 00000002 {rcx}
							GC regs: (unchanged) 00000002 {rcx}
							Byref regs: (unchanged) 00000000 {}

L_M40142_BB01:
Mapped BB01 to G_M40142_IG02
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}

Scope info: begin block BB01, IL range [000..???)
Generating: N003 (  1,  1) [000003] -----------                    t3 =    LCL_VAR   ref    V00 arg0         u:1 rcx REG rcx $80
                                                                        /--*  t3     ref    
Generating: N005 (  2,  2) [000005] -c---------                    t5 = *  LEA(b+8)  byref  REG NA
                                                                        /--*  t5     byref  
Generating: N007 (  4,  4) [000006] -c-X-------                    t6 = *  IND       int    REG NA <l:$240, c:$241>
Generating: N009 (  1,  1) [000008] -c---------                    t8 =    CNS_INT   int    8 REG NA $43
                                                                        /--*  t6     int    
                                                                        +--*  t8     int    
Generating: N011 (  6,  6) [000038] J--X---N---                         *  LT        void   REG NA <l:$245, c:$244>
IN0001:        cmp      dword ptr [rcx+08H], 8
Generating: N013 (  8,  8) [000049] ---X-------                         *  JTRUE     void   REG NA $201
IN0002:        jl       L_M40142_BB03
Scope info: ignoring block end

Variable Live Range History Dump for BB01
V00 arg0: rcx [(G_M40142_IG02,ins#0,ofs#0), ...]

=============== Generating BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04} flags=0x00000000.20000020: i LIR 
BB02 IN (1)={V00    } + ByrefExposed + GcHeap
     OUT(1)={    V03}

Recording Var Locations at start of BB02
  V00(rcx)
Liveness not changing: 0000000000000001 {V00}
							Live regs: 00000000 {} => 00000002 {rcx}
							GC regs: 00000000 {} => 00000002 {rcx}
							Byref regs: (unchanged) 00000000 {}

L_M40142_BB02:
Adding label due to BB weight difference: BBJ_COND BB01 with weight 100 different from BB02 with weight 25

G_M40142_IG02:        ; offs=000000H, funclet=00, bbWeight=1   , byref
Mapped BB02 to G_M40142_IG03
Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}

Scope info: begin block BB02, IL range [???..???)
Scope info: ignoring block beginning
Generating: N017 (  1,  1) [000009] ------?----                    t9 =    LCL_VAR   ref    V00 arg0         u:1 rcx (last use) REG rcx $80
                                                                        /--*  t9     ref    
Generating: N019 (  2,  2) [000025] -c----?----                   t25 = *  LEA(b+12) byref  REG NA
                                                                        /--*  t25    byref  
Generating: N021 (  4,  4) [000028] n----O?----                   t28 = *  IND       simd16 REG mm0 <l:$300, c:$301>
							V00 in reg rcx is becoming dead  [000009]
							Live regs: 00000002 {rcx} => 00000000 {}
							Live vars: {V00} => {}
							GC regs: 00000002 {rcx} => 00000000 {}
IN0003:        vmovupd  xmm0, xmmword ptr [rcx+0CH]
Generating: N023 (  3,  2) [000046] -c----?----                   t46 =    CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000> REG NA $340
                                                                        /--*  t28    simd16 
                                                                        +--*  t46    simd16 
Generating: N025 (  8,  7) [000030] -----O?----                   t30 = *  HWINTRINSIC simd16 ulong Or REG mm0 <l:$303, c:$302>
Increasing data section alignment from 4 to 16 for type simd16
IN0004:        vpor     xmm0, xmm0, xmmword ptr [reloc @RWD00]
Generating: N027 (  3,  2) [000047] -c----?----                   t47 =    CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f> REG NA $341
                                                                        /--*  t30    simd16 
                                                                        +--*  t47    simd16 
Generating: N029 ( 12, 10) [000032] -----O?N---                   t32 = *  HWINTRINSIC simd16 ulong Xor REG mm0 <l:$305, c:$304>
IN0005:        vpxor    xmm0, xmm0, xmmword ptr [reloc @RWD16]
                                                                        /--*  t32    simd16 
Generating: N031 (???,???) [000061] DA---O-----                         *  STORE_LCL_VAR simd16 V04 rat0          mm0 REG mm0
							V04 in reg mm0 is becoming live  [000061]
							Live regs: 00000000 {} => 00000000 {xmm0}
							Live vars: {} => {V04}
Generating: N033 (???,???) [000062] -----------                   t62 =    LCL_VAR   simd16 V04 rat0          mm0 REG mm0
Generating: N035 (???,???) [000063] -----------                   t63 =    LCL_VAR   simd16 V04 rat0          mm0 (last use) REG mm0
                                                                        /--*  t62    simd16 
                                                                        +--*  t63    simd16 
Generating: N037 ( 14, 13) [000035] -----O?----                         *  HWINTRINSIC void   ulong PTEST REG NA <l:$383, c:$382>
							V04 in reg mm0 is becoming dead  [000063]
							Live regs: 00000000 {xmm0} => 00000000 {}
							Live vars: {V04} => {}
IN0006:        vptest   xmm0, xmm0
Generating: N039 (???,???) [000064] -----------                   t64 =    SETCC     int    cond=UEQ REG rax
IN0007:        sete     al
IN0008:        movzx    rax, al
                                                                        /--*  t64    int    
Generating: N041 ( 14, 13) [000051] DA---O-----                         *  STORE_LCL_VAR int    V03 tmp2         d:3 rax REG rax
							V03 in reg rax is becoming live  [000051]
							Live regs: 00000000 {} => 00000001 {rax}
							Live vars: {} => {V03}
Scope info: ignoring block end
IN0009:        jmp      L_M40142_BB04

Variable Live Range History Dump for BB02
V00 arg0: rcx [(G_M40142_IG02,ins#0,ofs#0), (G_M40142_IG03,ins#0,ofs#0)]

=============== Generating BB03 [???..???), preds={BB01} succs={BB04} flags=0x00000000.20010020: i label LIR 
BB03 IN (0)={   }
     OUT(1)={V03}

Recording Var Locations at start of BB03
  <none>

Change life 0000000000000002 {V03} -> 0000000000000000 {}
							V03 in reg rax is becoming dead  [------]
							Live regs: (unchanged) 00000000 {}
							Live regs: (unchanged) 00000000 {}
							GC regs: (unchanged) 00000000 {}
							Byref regs: (unchanged) 00000000 {}

L_M40142_BB03:

G_M40142_IG03:        ; offs=00000AH, funclet=00, bbWeight=0.25, byref
Mapped BB03 to G_M40142_IG04
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}

Scope info: begin block BB03, IL range [???..???)
Scope info: ignoring block beginning
Generating: N045 (  1,  1) [000036] ------?----                   t36 =    CNS_INT   int    0 REG rax $40
IN000a:        xor      eax, eax
                                                                        /--*  t36    int    
Generating: N047 (  1,  3) [000053] DA---------                         *  STORE_LCL_VAR int    V03 tmp2         d:2 rax REG rax
							V03 in reg rax is becoming live  [000053]
							Live regs: 00000000 {} => 00000001 {rax}
							Live vars: {} => {V03}
Scope info: ignoring block end

Variable Live Range History Dump for BB03
..None..

=============== Generating BB04 [???..00D) (return), preds={BB02,BB03} succs={} flags=0x00000000.20010020: i label LIR 
BB04 IN (1)={V03}
     OUT(0)={   }

Recording Var Locations at start of BB04
  V03(rax)
Liveness not changing: 0000000000000002 {V03}
							Live regs: 00000000 {} => 00000001 {rax}
							GC regs: (unchanged) 00000000 {}
							Byref regs: (unchanged) 00000000 {}

L_M40142_BB04:

G_M40142_IG04:        ; offs=000032H, funclet=00, bbWeight=0.25, byref
Mapped BB04 to G_M40142_IG05
Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}

G_M40142_IG05:        ; offs=000034H, funclet=00, bbWeight=1   , byref
*************** After placeholder IG creation
G_M40142_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M40142_IG02:        ; offs=000000H, size=000AH, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M40142_IG03:        ; offs=00000AH, size=0028H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB02 [0004], byref
G_M40142_IG04:        ; offs=000032H, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB03 [0003], byref
G_M40142_IG05:        ; offs=000034H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB04 [0001], byref
G_M40142_IG06:        ; epilog placeholder, next placeholder=<END>, BB04 [0001], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}

Variable Live Range History Dump for BB04
..None..
Liveness not changing: 0000000000000000 {}

# compCycleEstimate =     26, compSizeEstimate =    28 Program:IsHttps(System.String):bool
; Final local variable assignments
;
;  V00 arg0         [V00,T00] (  4,  3.25)     ref  ->  rcx         class-hnd single-def
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [rsp+00H]   "OutgoingArgSpace"
;* V02 tmp1         [V02    ] (  0,  0   )     ref  ->  zero-ref    single-def "spilling varStr"
;  V03 tmp2         [V03,T01] (  3,  3   )     int  ->  rax         "spilling unroll qmark"
;  V04 rat0         [V04,T02] (  3,  1.50)  simd16  ->  mm0         "ReplaceWithLclVar is creating a new local variable"
;
; Lcl frame size = 0
*************** Before prolog / epilog generation
G_M40142_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M40142_IG02:        ; offs=000000H, size=000AH, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M40142_IG03:        ; offs=00000AH, size=0028H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB02 [0004], byref
G_M40142_IG04:        ; offs=000032H, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB03 [0003], byref
G_M40142_IG05:        ; offs=000034H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB04 [0001], byref
G_M40142_IG06:        ; epilog placeholder, next placeholder=<END>, BB04 [0001], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Recording Var Locations at start of BB01
  V00(rcx)
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M40142_IG01,ins#0,ofs#0) label

__prolog:
New debug range: first
IN000c:        vzeroupper 
*************** In genFnPrologCalleeRegArgs() for int regs
*************** In genEnregisterIncomingStackArgs()

G_M40142_IG01:        ; offs=000000H, funclet=00, bbWeight=1   , byref, nogc
*************** In genFnEpilog()

__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN000d:        ret

G_M40142_IG06:        ; offs=000037H, funclet=00, bbWeight=1   , epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M40142_IG01:        ; func=00, offs=000000H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M40142_IG02:        ; offs=000003H, size=000AH, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M40142_IG03:        ; offs=00000DH, size=0028H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB02 [0004], byref
G_M40142_IG04:        ; offs=000035H, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB03 [0003], byref
G_M40142_IG05:        ; offs=000037H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB04 [0001], byref
G_M40142_IG06:        ; offs=00003AH, size=0001H, epilog, nogc, extend
*************** In emitRemoveJumpToNextInst()
Emitter Jump List:
IG02 IN0002  jl[6] -> IG04
IG03 IN0009 jmp[5] -> IG05 ; removal candidate
  total jump count: 2
IG03 IN0009 does not jump to the next instruction group, keeping.
emitRemoveJumpToNextInst removed no unconditional jumps
*************** In emitJumpDistBind()
Emitter Jump List:
IG02 IN0002  jl[6] -> IG04
IG03 IN0009 jmp[5] -> IG05 ; removal candidate
  total jump count: 2
Binding: IN0002: 000000 jl       L_M40142_BB03
Binding L_M40142_BB03 to G_M40142_IG04
Estimate of fwd jump [D1FFAB1E/002]: 0007 -> 0035 = 002C
Shrinking jump [D1FFAB1E/002]
Adjusted offset of BB03 from 000D to 0009
Binding: IN0009: 000000 jmp      L_M40142_BB04
Binding L_M40142_BB04 to G_M40142_IG05
Estimate of fwd jump [D1FFAB1E/009]: 002C -> 0033 = 0005
Shrinking jump [D1FFAB1E/009]
Adjusted offset of BB04 from 0035 to 002E
Adjusted offset of BB05 from 0037 to 0030
Adjusted offset of BB06 from 003A to 0033
Total shrinkage =   7, min extra jump size = 4294967295

*************** Finishing PHASE Generate code

*************** Starting PHASE Emit code

Hot  code size = 0x34 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x4)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)

***************************************************************************
Instructions as they come out of the scheduler

G_M40142_IG01:        ; func=00, offs=000000H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN000c: 000000 vzeroupper 
						;; size=3 bbWeight=1    PerfScore 1.00
G_M40142_IG02:        ; func=00, offs=000003H, size=0006H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB01 [0000], byref, isz
       ; gcrRegs +[rcx]
IN0001: 000003 cmp      dword ptr [rcx+08H], 8
IN0002: 000007 jl       SHORT G_M40142_IG04
						;; size=6 bbWeight=1    PerfScore 4.00
G_M40142_IG03:        ; func=00, offs=000009H, size=0025H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB02 [0004], byref, isz
IN0003: 000009 vmovupd  xmm0, xmmword ptr [rcx+0CH] (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
Increasing size adj 0 by 1 => 1
recordRelocation: 00000000D1FFAB1E (rw: 00000000D1FFAB1E) => 00000000D1FFAB1E, type 16 (IMAGE_REL_BASED_DISP32), delta 0
IN0004: 00000E vpor     xmm0, xmm0, xmmword ptr [reloc @RWD00] (ECS:9, ACS:8)
Instruction predicted size = 9, actual = 8
Increasing size adj 1 by 1 => 2
recordRelocation: 00000000D1FFAB1E (rw: 00000000D1FFAB1E) => 00000000D1FFAB1E, type 16 (IMAGE_REL_BASED_DISP32), delta 0
IN0005: 000016 vpxor    xmm0, xmm0, xmmword ptr [reloc @RWD16] (ECS:9, ACS:8)
Instruction predicted size = 9, actual = 8
Increasing size adj 2 by 1 => 3
IN0006: 00001E vptest   xmm0, xmm0
IN0007: 000023 sete     al
IN0008: 000026 movzx    rax, al
IN0009: 000029 jmp      SHORT G_M40142_IG05
						;; size=34 bbWeight=0.25 PerfScore 3.56
G_M40142_IG04:        ; func=00, offs=00002EH, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB03 [0003], byref
Block predicted offs = 0000002E, actual = 0000002B -> size adj = 3
       ; gcrRegs -[rcx]
IN000a: 00002B xor      eax, eax
						;; size=2 bbWeight=0.25 PerfScore 0.06
G_M40142_IG05:        ; func=00, offs=000030H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB04 [0001], byref
Block predicted offs = 00000030, actual = 0000002D -> size adj = 3
IN000b: 00002D movzx    rax, al
						;; size=3 bbWeight=1    PerfScore 0.25
G_M40142_IG06:        ; func=00, offs=000033H, size=0001H, epilog, nogc, extend
Block predicted offs = 00000033, actual = 00000030 -> size adj = 3
IN000d: 000030 ret      
						;; size=1 bbWeight=1    PerfScore 1.00
Emitting data sections: 32 total bytes
  section   0, size 16, RWD 0:	20 00 20 00 20 00 20 00 20 00 00 00 00 00 00 00 
  section   1, size 16, RWD16:	68 00 74 00 74 00 70 00 73 00 3a 00 2f 00 2f 00 
Allocated method code size =   52 , actual size =   49, unused size =    3

; Total bytes of code 49, prolog size 3, PerfScore 15.08, instruction count 13, allocated bytes for code 52 (MethodHash=9eee6331) for method Program:IsHttps(System.String):bool
; ============================================================

*************** After end code gen, before unwindEmit()
G_M40142_IG01:        ; func=00, offs=000000H, size=0003H, bbWeight=1    PerfScore 1.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG

IN000c: 000000 vzeroupper

G_M40142_IG02:        ; offs=000003H, size=0006H, bbWeight=1    PerfScore 4.00, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB01 [0000], byref, isz

IN0001: 000003 cmp      dword ptr [rcx+08H], 8
IN0002: 000007 jl       SHORT G_M40142_IG04

G_M40142_IG03:        ; offs=000009H, size=0022H, bbWeight=0.25 PerfScore 3.56, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, BB02 [0004], byref, isz

IN0003: 000009 vmovupd  xmm0, xmmword ptr [rcx+0CH]
IN0004: 00000E vpor     xmm0, xmm0, xmmword ptr [reloc @RWD00]
IN0005: 000016 vpxor    xmm0, xmm0, xmmword ptr [reloc @RWD16]
IN0006: 00001E vptest   xmm0, xmm0
IN0007: 000023 sete     al
IN0008: 000026 movzx    rax, al
IN0009: 000029 jmp      SHORT G_M40142_IG05

G_M40142_IG04:        ; offs=00002BH, size=0002H, bbWeight=0.25 PerfScore 0.06, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB03 [0003], byref

IN000a: 00002B xor      eax, eax

G_M40142_IG05:        ; offs=00002DH, size=0003H, bbWeight=1    PerfScore 0.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB04 [0001], byref

IN000b: 00002D movzx    rax, al

G_M40142_IG06:        ; offs=000030H, size=0001H, bbWeight=1    PerfScore 1.00, epilog, nogc, extend

IN000d: 000030 ret

*************** Finishing PHASE Emit code

*************** Starting PHASE Emit GC+EH tables
Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0xd1ffab1e (not in unwind data)
  Version           : 1
  Flags             : 0x00
  SizeOfProlog      : 0x00
  CountOfUnwindCodes: 0
  FrameRegister     : none (0)
  FrameOffset       : N/A (no FrameRegister) (Value=0)
  UnwindCodes       :
allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x31, unwindSize=0x4, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 2
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs EPILOG : 0x00000030 ( STACK_EMPTY )

*************** In genSetScopeInfo()
VarLocInfo count is 2
; Variable debug info: 1 live ranges, 1 vars for method Program:IsHttps(System.String):bool
  0(   UNKNOWN) : From 00000000h to 00000009h, in rcx
VARIABLE LIVE RANGES:
V00 arg0: rcx [3, 9)
*************** In gcInfoBlockHdrSave()
Set code length to 49.
Set ReturnKind to Scalar.
Set Outgoing stack arg area size to 0.
Defining 0 call sites:

*************** Finishing PHASE Emit GC+EH tables
Method code size: 49

Allocations for Program:IsHttps(System.String):bool (MethodHash=9eee6331)
count:        620, size:      70845, max =       3072
allocateMemory:     131072, nraUsed:      73520

Alloc'd bytes by kind:
                  kind |       size |     pct
  ---------------------+------------+--------
         AssertionProp |       6676 |   9.42%
               ASTNode |       7968 |  11.25%
              InstDesc |       3308 |   4.67%
              ImpStack |        384 |   0.54%
            BasicBlock |       1976 |   2.79%
              CallArgs |          0 |   0.00%
              FlowList |        296 |   0.42%
     TreeStatementList |          0 |   0.00%
               SiScope |          0 |   0.00%
       DominatorMemory |        240 |   0.34%
                  LSRA |       4908 |   6.93%
         LSRA_Interval |        720 |   1.02%
      LSRA_RefPosition |       1664 |   2.35%
          Reachability |        136 |   0.19%
                   SSA |        528 |   0.75%
           ValueNumber |      14765 |  20.84%
              LvaTable |       2084 |   2.94%
            UnwindInfo |          0 |   0.00%
                hashBv |         40 |   0.06%
                bitset |        200 |   0.28%
          FixedBitVect |         16 |   0.02%
               Generic |       1062 |   1.50%
   LocalAddressVisitor |        384 |   0.54%
         FieldSeqStore |          0 |   0.00%
          MemorySsaMap |         40 |   0.06%
          MemoryPhiArg |          0 |   0.00%
                   CSE |       1384 |   1.95%
                    GC |       1312 |   1.85%
       CorTailCallInfo |          0 |   0.00%
              Inlining |        416 |   0.59%
            ArrayStack |        128 |   0.18%
             DebugInfo |        136 |   0.19%
             DebugOnly |      17817 |  25.15%
               Codegen |        848 |   1.20%
               LoopOpt |         96 |   0.14%
             LoopClone |          0 |   0.00%
             LoopHoist |          0 |   0.00%
               Unknown |        121 |   0.17%
            RangeCheck |          0 |   0.00%
              CopyProp |        776 |   1.10%
           SideEffects |          0 |   0.00%
       ObjectAllocator |          0 |   0.00%
    VariableLiveRanges |        328 |   0.46%
           ClassLayout |          0 |   0.00%
       TailMergeThrows |          0 |   0.00%
             EarlyProp |          0 |   0.00%
              ZeroInit |         88 |   0.12%
                   Pgo |          0 |   0.00%

****** DONE compiling Program:IsHttps(System.String):bool

Texto alterado

Abrir arquivo

lvaSetClass: setting class for V00 to (00000000D1FFAB1E) System.String 
Arg #0    passed in register(s) rcx

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import
Trees after Pre-import

------------ BB01 [000..00D) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation
*************** In impImport() for Program:IsHttps(System.String):bool

impImportBlockPending for BB01

lvaGrabTemp returning 2 (V02 tmp1) called for spilling varStr.
Notify VM instruction set (SSE2) must be supported.
Notify VM instruction set (Vector256) must be supported.

lvaGrabTemp returning 3 (V03 tmp2) called for spilling unroll qmark.

STMT00001 ( ??? ... ??? )
               [000043] -A-X-------                         *  ASG       int   
               [000042] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-------                         \--*  QMARK     bool  
               [000038] ---X-------    if                      +--*  GE        int   
               [000006] ---X-------                            |  +--*  IND       int   
               [000005] -----------                            |  |  \--*  ADD       byref 
               [000003] -----------                            |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000004] -----------                            |  |     \--*  CNS_INT   long   8
               [000008] -----------                            |  \--*  CNS_INT   int    8
               [000037] ---X-------    if                      \--*  COLON     int   
               [000036] ----------- else                          +--*  CNS_INT   int    0
               [000035] ---X------- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-------                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-------                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-------                                  |  |  +--*  IND       simd16
               [000025] -----------                                  |  |  |  \--*  ADD       byref 
               [000009] -----------                                  |  |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000023] -----------                                  |  |  |     \--*  CNS_INT   long   12
               [000018] -----------                                  |  |  \--*  HWINTRINSIC simd16 ulong Create
               [000016] -----------                                  |  |     +--*  CNS_INT   long   0x20002000200020
               [000017] -----------                                  |  |     \--*  CNS_INT   long   32
               [000012] -----------                                  |  \--*  HWINTRINSIC simd16 ulong Create
               [000010] -----------                                  |     +--*  CNS_INT   long   0x70007400740068
               [000011] -----------                                  |     \--*  CNS_INT   long   0x2f002f003a0073
               [000022] -----------                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

... Successfully unrolled to:
               [000044] -----------                         *  LCL_VAR   int    V03 tmp2

[ 1]  12 (0x00c) ret

STMT00002 ( ??? ... ??? )
               [000045] -----------                         *  RETURN    int   
               [000044] -----------                         \--*  LCL_VAR   int    V03 tmp2

*************** Finishing PHASE Importation
Trees after Importation

------------ BB01 [000..00D) (return), preds={} succs={}

***** BB01
STMT00001 ( ??? ... ??? )
               [000043] -A-X-------                         *  ASG       int   
               [000042] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-------                         \--*  QMARK     bool  
               [000038] ---X-------    if                      +--*  GE        int   
               [000006] ---X-------                            |  +--*  IND       int   
               [000005] -----------                            |  |  \--*  ADD       byref 
               [000003] -----------                            |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000004] -----------                            |  |     \--*  CNS_INT   long   8
               [000008] -----------                            |  \--*  CNS_INT   int    8
               [000037] ---X-------    if                      \--*  COLON     int   
               [000036] ----------- else                          +--*  CNS_INT   int    0
               [000035] ---X------- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-------                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-------                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-------                                  |  |  +--*  IND       simd16
               [000025] -----------                                  |  |  |  \--*  ADD       byref 
               [000009] -----------                                  |  |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000023] -----------                                  |  |  |     \--*  CNS_INT   long   12
               [000018] -----------                                  |  |  \--*  HWINTRINSIC simd16 ulong Create
               [000016] -----------                                  |  |     +--*  CNS_INT   long   0x20002000200020
               [000017] -----------                                  |  |     \--*  CNS_INT   long   32
               [000012] -----------                                  |  \--*  HWINTRINSIC simd16 ulong Create
               [000010] -----------                                  |     +--*  CNS_INT   long   0x70007400740068
               [000011] -----------                                  |     \--*  CNS_INT   long   0x2f002f003a0073
               [000022] -----------                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Expand patchpoints

-- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Indirect call transform

-- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import [no changes]

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Init [no changes]

*************** Starting PHASE Morph - Inlining
*************** In fgDebugCheckBBlist
**************** Inline Tree

*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining

------------ BB01 [000..00D) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Allocate Objects
no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

***************  Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks [no changes]

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally
No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Compute preds

Renumbering the basic blocks for fgComputePred

*************** Before renumbering the basic blocks

***************  Exception Handling table is empty

*************** After renumbering the basic blocks
=============== No blocks renumbered!

*************** Finishing PHASE Compute preds
Trees after Compute preds

------------ BB01 [000..00D) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Merge throw blocks

*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.

*************** Finishing PHASE Merge throw blocks [no changes]

*************** Starting PHASE Update flow graph early pass

*************** Finishing PHASE Update flow graph early pass [no changes]

*************** Starting PHASE Morph - Promote Structs

*************** Finishing PHASE Morph - Promote Structs [no changes]

LocalAddressVisitor visiting statement:
STMT00001 ( ??? ... ??? )
               [000043] -A-X-------                         *  ASG       int   
               [000042] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-------                         \--*  QMARK     bool  
               [000038] ---X-------    if                      +--*  GE        int   
               [000006] ---X-------                            |  +--*  IND       int   
               [000005] -----------                            |  |  \--*  ADD       byref 
               [000003] -----------                            |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000004] -----------                            |  |     \--*  CNS_INT   long   8
               [000008] -----------                            |  \--*  CNS_INT   int    8
               [000037] ---X-------    if                      \--*  COLON     int   
               [000036] ----------- else                          +--*  CNS_INT   int    0
               [000035] ---X------- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-------                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-------                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-------                                  |  |  +--*  IND       simd16
               [000025] -----------                                  |  |  |  \--*  ADD       byref 
               [000009] -----------                                  |  |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000023] -----------                                  |  |  |     \--*  CNS_INT   long   12
               [000018] -----------                                  |  |  \--*  HWINTRINSIC simd16 ulong Create
               [000016] -----------                                  |  |     +--*  CNS_INT   long   0x20002000200020
               [000017] -----------                                  |  |     \--*  CNS_INT   long   32
               [000012] -----------                                  |  \--*  HWINTRINSIC simd16 ulong Create
               [000010] -----------                                  |     +--*  CNS_INT   long   0x70007400740068
               [000011] -----------                                  |     \--*  CNS_INT   long   0x2f002f003a0073
               [000022] -----------                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

*************** Finishing PHASE Morph - Structs/AddrExp [no changes]

*************** Starting PHASE Forward Substitution

===> BB01
    [000041]:  not asg (single-use lcl)
    [000043]:  tree to sub is qmark, catch arg, or lcl heap

*************** Finishing PHASE Forward Substitution [no changes]

*************** Starting PHASE Morph - ByRefs

*************** Finishing PHASE Morph - ByRefs [no changes]

*************** Starting PHASE Morph - Global

*************** In fgMorphBlocks()

Morphing BB01 of 'Program:IsHttps(System.String):bool'

fgMorphTree BB01, STMT00001 (before)
               [000043] -A-X-------                         *  ASG       int   
               [000042] D------N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-------                         \--*  QMARK     bool  
               [000038] ---X-------    if                      +--*  GE        int   
               [000006] ---X-------                            |  +--*  IND       int   
               [000005] -----------                            |  |  \--*  ADD       byref 
               [000003] -----------                            |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000004] -----------                            |  |     \--*  CNS_INT   long   8
               [000008] -----------                            |  \--*  CNS_INT   int    8
               [000037] ---X-------    if                      \--*  COLON     int   
               [000036] ----------- else                          +--*  CNS_INT   int    0
               [000035] ---X------- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-------                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-------                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-------                                  |  |  +--*  IND       simd16
               [000025] -----------                                  |  |  |  \--*  ADD       byref 
               [000009] -----------                                  |  |  |     +--*  LCL_VAR   ref    V02 tmp1         
               [000023] -----------                                  |  |  |     \--*  CNS_INT   long   12
               [000018] -----------                                  |  |  \--*  HWINTRINSIC simd16 ulong Create
               [000016] -----------                                  |  |     +--*  CNS_INT   long   0x20002000200020
               [000017] -----------                                  |  |     \--*  CNS_INT   long   32
               [000012] -----------                                  |  \--*  HWINTRINSIC simd16 ulong Create
               [000010] -----------                                  |     +--*  CNS_INT   long   0x70007400740068
               [000011] -----------                                  |     \--*  CNS_INT   long   0x2f002f003a0073
               [000022] -----------                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

Assertion prop in BB01:
Copy     Assertion: V02 == V00, index = #01
               [000009] -----------                         *  LCL_VAR   ref    V00 arg0         
GenTreeNode creates assertion:
               [000043] -A-X-+-----                         *  ASG       int   
In BB01 New Local Subrange Assertion: V03 in [0..255], index = #03

fgMorphTree BB01, STMT00001 (after)
               [000043] -A-X-+-----                         *  ASG       int   
               [000042] D----+-N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-+-----                         \--*  QMARK     bool  
               [000038] J--X-+-N---    if                      +--*  GE        int   
               [000006] ---X-+-----                            |  +--*  IND       int   
               [000005] -----+-----                            |  |  \--*  ADD       byref 
               [000003] -----+-----                            |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000004] -----+-----                            |  |     \--*  CNS_INT   long   8
               [000008] -----+-----                            |  \--*  CNS_INT   int    8
               [000037] ---X-+?----    if                      \--*  COLON     int   
               [000036] -----+?---- else                          +--*  CNS_INT   int    0
               [000035] ---X-+?---- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-+?----                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-+?----                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-+?----                                  |  |  +--*  IND       simd16
               [000025] -----+?----                                  |  |  |  \--*  ADD       byref 
               [000009] -----+?----                                  |  |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000023] -----+?----                                  |  |  |     \--*  CNS_INT   long   12
               [000046] -----+?----                                  |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
               [000047] -----+?----                                  |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
               [000022] -----+?----                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

Subrange prop for index #03 in BB01:
               [000048] -----------                         *  CAST      int <- bool <- int

*************** In fgMarkDemotedImplicitByRefArgs()

Expanding top-level qmark in BB01 (before)

------------ BB01 [000..00D) (return), preds={} succs={}

***** BB01
STMT00001 ( ??? ... ??? )
               [000043] -A-X-+-----                         *  ASG       int   
               [000042] D----+-N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-+-----                         \--*  QMARK     bool  
               [000038] J--X-+-N---    if                      +--*  GE        int   
               [000006] ---X-+-----                            |  +--*  IND       int   
               [000005] -----+-----                            |  |  \--*  ADD       byref 
               [000003] -----+-----                            |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000004] -----+-----                            |  |     \--*  CNS_INT   long   8
               [000008] -----+-----                            |  \--*  CNS_INT   int    8
               [000037] ---X-+?----    if                      \--*  COLON     int   
               [000036] -----+?---- else                          +--*  CNS_INT   int    0
               [000035] ---X-+?---- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-+?----                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-+?----                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-+?----                                  |  |  +--*  IND       simd16
               [000025] -----+?----                                  |  |  |  \--*  ADD       byref 
               [000009] -----+?----                                  |  |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000023] -----+?----                                  |  |  |     \--*  CNS_INT   long   12
               [000046] -----+?----                                  |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
               [000047] -----+?----                                  |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
               [000022] -----+?----                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>

***** BB01
STMT00002 ( ??? ... ??? )
               [000045] -----+-----                         *  RETURN    int   
               [000044] -----+-----                         \--*  LCL_VAR   int    V03 tmp2

removing useless STMT00001 ( ??? ... ??? )
               [000043] -A-X-+-----                         *  ASG       int   
               [000042] D----+-N---                         +--*  LCL_VAR   int    V03 tmp2         
               [000039] ---X-+-----                         \--*  QMARK     bool  
               [000038] J--X-+-N---    if                      +--*  LT        int   
               [000006] ---X-+-----                            |  +--*  IND       int   
               [000005] -----+-----                            |  |  \--*  ADD       byref 
               [000003] -----+-----                            |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000004] -----+-----                            |  |     \--*  CNS_INT   long   8
               [000008] -----+-----                            |  \--*  CNS_INT   int    8
               [000037] ---X-+?----    if                      \--*  COLON     int   
               [000036] -----+?---- else                          +--*  CNS_INT   int    0
               [000035] ---X-+?---- then                          \--*  HWINTRINSIC bool   ulong op_Equality
               [000032] ---X-+?----                                  +--*  HWINTRINSIC simd16 ulong Xor
               [000030] ---X-+?----                                  |  +--*  HWINTRINSIC simd16 ulong Or
               [000028] ---X-+?----                                  |  |  +--*  IND       simd16
               [000025] -----+?----                                  |  |  |  \--*  ADD       byref 
               [000009] -----+?----                                  |  |  |     +--*  LCL_VAR   ref    V00 arg0         
               [000023] -----+?----                                  |  |  |     \--*  CNS_INT   long   12
               [000046] -----+?----                                  |  |  \--*  CNS_VEC   simd16<0x00200020, 0x00200020, 0x00000020, 0x00000000>
               [000047] -----+?----                                  |  \--*  CNS_VEC   simd16<0x00740068, 0x00700074, 0x003a0073, 0x002f002f>
               [000022] -----+?----                                  \--*  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>
 from BB01

Expanding top-level qmark in BB01 (after)

------------ BB01 [000..???), preds={} succs={BB03}

------------ BB03 [???..???) -> BB04 (cond), preds={BB01} succs={BB05,BB04}

------------ BB05 [???..???) -> BB02 (always), preds={BB03} succs={BB02}

------------ BB04 [???..???), preds={BB03} succs={BB02}

------------ BB02 [???..00D) (return), preds={BB04,BB05} succs={}

***** BB02
STMT00002 ( ??? ... ??? )
               [000045] -----+-----                         *  RETURN    int   
               [000044] -----+-----                         \--*  LCL_VAR   int    V03 tmp2

-------------------------------------------------------------------------------------------------------------------

*************** Before renumbering the basic blocks

***************  Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB05 to BB03
Renumber BB02 to BB05

*************** After renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)                                     i 
BB02 [0002]  1       BB01                  1       [???..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB02                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB02                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

New BlockSet epoch 2, # of blocks (including unused BB00): 6, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Global
Trees after Morph - Global

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)                                     i 
BB02 [0002]  1       BB01                  1       [???..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB02                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB02                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???), preds={} succs={BB02}

------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}

------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}

------------ BB04 [???..???), preds={BB02} succs={BB05}

------------ BB05 [???..00D) (return), preds={BB03,BB04} succs={}

***** BB05
STMT00002 ( ??? ... ??? )
               [000045] -----+-----                         *  RETURN    int   
               [000044] -----+-----                         \--*  LCL_VAR   int    V03 tmp2

*************** Starting PHASE GS Cookie
No GS security needed

*************** Finishing PHASE GS Cookie [no changes]

*************** Starting PHASE Compute edge weights (1, false)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)                                     i 
BB02 [0002]  1       BB01                  1       [???..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB02                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB02                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

-- no profile data, so using default called count
 -- not optimizing or no profile data, so not computing edge weights

*************** Finishing PHASE Compute edge weights (1, false) [no changes]

*************** Starting PHASE Create EH funclets

*************** Finishing PHASE Create EH funclets [no changes]

*************** Starting PHASE Invert loops

*************** Finishing PHASE Invert loops [no changes]

*************** Starting PHASE Optimize control flow

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)                                     i 
BB02 [0002]  1       BB01                  1       [???..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB02                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB02                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

Considering uncond to cond BB01 -> BB02

After updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB01                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
*************** In fgDebugCheckBBlist

*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB01                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize control flow
Trees after Optimize control flow

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB01                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB04 (cond), preds={} succs={BB03,BB04}

------------ BB03 [???..???) -> BB05 (always), preds={BB01} succs={BB05}

------------ BB04 [???..???), preds={BB01} succs={BB05}

------------ BB05 [???..00D) (return), preds={BB03,BB04} succs={}

*************** Starting PHASE Compute blocks reachability
Return blocks: BB05

Renumbering the basic blocks for fgComputeReachability pass #1

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB04 ( cond )                     i 
BB03 [0004]  1       BB01                  0.50    [???..???)-> BB05 (always)                     i 
BB04 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB05 [0001]  2       BB03,BB04             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB04 to BB03
Renumber BB05 to BB04

*************** After renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.50    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

New BlockSet epoch 3, # of blocks (including unused BB00): 5, bitset array size: 1 (short)
Enter blocks: BB01

Inside fgBuildDomTree

After computing the Dominance Tree:
BB01 : BB04 BB03 BB02

After numbering the dominator tree:
BB01: pre=01, post=04
BB02: pre=04, post=03
BB03: pre=03, post=02
BB04: pre=02, post=01

*************** Finishing PHASE Compute blocks reachability
Trees after Compute blocks reachability

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.50    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.50    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00002 ( ??? ... ??? )
               [000045] -----+-----                         *  RETURN    int   
               [000044] -----+-----                         \--*  LCL_VAR   int    V03 tmp2

*************** Starting PHASE Set block weights

*************** Finishing PHASE Set block weights
Trees after Set block weights

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

*************** Starting PHASE Find loops
*************** In optFindLoops()
*************** In optMarkLoopHeads()
0 loop heads marked

*************** Finishing PHASE Find loops
Trees after Find loops

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Clone loops

*************** In optCloneLoops()
  No loops to clone

*************** Finishing PHASE Clone loops [no changes]

*************** Starting PHASE Unroll loops

*************** Finishing PHASE Unroll loops [no changes]

*************** Starting PHASE Clear loop info

*************** Finishing PHASE Clear loop info [no changes]

*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function

*************** Finishing PHASE Morph array ops [no changes]

*************** Starting PHASE Mark local vars

*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** marking local variables in block BB04 (weight=1   )
STMT00002 ( ??? ... ??? )
               [000045] -----+-----                         *  RETURN    int   
               [000044] -----+-----                         \--*  LCL_VAR   int    V03 tmp2         
New refCnts for V03: refCnt =  3, refCntWtd = 3

*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt =  4, refCntWtd = 3.25
New refCnts for V00: refCnt =  5, refCntWtd = 4.25

*************** Finishing PHASE Mark local vars [no changes]

*************** Starting PHASE Opt add copies

*************** In optAddCopies()

*************** Finishing PHASE Opt add copies [no changes]

*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()

*************** Finishing PHASE Find oper order
Trees after Find oper order

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00002 ( ??? ... ??? )
     (  2,  2) [000045] -----------                         *  RETURN    int   
     (  1,  1) [000044] -----------                         \--*  LCL_VAR   int    V03 tmp2

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has   12 tree nodes

*************** Finishing PHASE Set block order
Trees after Set block order

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00002 ( ??? ... ??? )
N002 (  2,  2) [000045] -----------                         *  RETURN    int   
N001 (  1,  1) [000044] -----------                         \--*  LCL_VAR   int    V03 tmp2

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 5.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]

Inside fgBuildDomTree

After computing the Dominance Tree:
BB01 : BB04 BB03 BB02

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00    } + ByrefExposed + GcHeap
     DEF(1)={    V02}

BB02 USE(1)={V00    } + ByrefExposed + GcHeap
     DEF(1)={    V03}

BB03 USE(0)={   }
     DEF(1)={V03}

BB04 USE(1)={V03}
     DEF(0)={   }

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(1)={V00} + ByrefExposed + GcHeap

BB02 IN (1)={V00    } + ByrefExposed + GcHeap
     OUT(1)={    V03}

BB03 IN (0)={   }
     OUT(1)={V03}

BB04 IN (1)={V03}
     OUT(0)={   }

top level assign
removing stmt with no side effects

*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00003 ( ??? ... ??? )
N007 (  8,  8) [000049] ---X-------                         *  JTRUE     void  
N006 (  6,  6) [000038] J--X---N---                         \--*  LT        int   
N004 (  4,  4) [000006] ---X-------                            +--*  IND       int   
N003 (  2,  2) [000005] -------N---                            |  \--*  ADD       byref 
N001 (  1,  1) [000003] -----------                            |     +--*  LCL_VAR   ref    V00 arg0         u:1
N002 (  1,  1) [000004] -----------                            |     \--*  CNS_INT   long   8
N005 (  1,  1) [000008] -----------                            \--*  CNS_INT   int    8

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00002 ( ??? ... ??? )
N002 (  2,  2) [000045] -----------                         *  RETURN    int   
N001 (  1,  1) [000044] -----------                         \--*  LCL_VAR   int    V03 tmp2         u:1 (last use)

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method

*************** Finishing PHASE Early Value Propagation [no changes]

*************** Starting PHASE Do value numbering

***** BB04, STMT00002(before)
N002 (  2,  2) [000045] -----------                         *  RETURN    int   
N001 (  1,  1) [000044] -----------                         \--*  LCL_VAR   int    V03 tmp2         u:1 (last use)

N001 [000044]   LCL_VAR   V03 tmp2         u:1 (last use) => $181 {PhiDef($3, $1, $248)}
N002 [000045]   RETURN    => $VN.Void

***** BB04, STMT00002(after)
N002 (  2,  2) [000045] -----------                         *  RETURN    int    $VN.Void
N001 (  1,  1) [000044] -----------                         \--*  LCL_VAR   int    V03 tmp2         u:1 (last use) $181

finish(BB04).

*************** Finishing PHASE Do value numbering
Trees after Do value numbering

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..???)-> BB03 ( cond )                     i 
BB02 [0004]  1       BB01                  0.25    [???..???)-> BB04 (always)                     i 
BB03 [0003]  1       BB01                  0.25    [???..???)                                     i 
BB04 [0001]  2       BB02,BB03             1       [???..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..???) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [???..???) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [???..???), preds={BB01} succs={BB04}

------------ BB04 [???..00D) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00002 ( ??? ... ??? )
N002 (  2,  2) [000045] -----------                         *  RETURN    int    $VN.Void
N001 (  1,  1) [000044] -----------                         \--*  LCL_VAR   int    V03 tmp2         u:1 (last use) $181