FormatBigInteger

Criado O diff nunca expira
278 remoções
532 linhas
283 adições
538 linhas
; Assembly listing for method System.Numerics.BigNumber:FormatBigInteger(bool,System.Numerics.BigInteger,System.String,System.ReadOnlySpan`1[System.Char],System.Globalization.NumberFormatInfo,System.Span`1[System.Char],byref,byref):System.String
; Assembly listing for method System.Numerics.BigNumber:FormatBigInteger(bool,System.Numerics.BigInteger,System.String,System.ReadOnlySpan`1[System.Char],System.Globalization.NumberFormatInfo,System.Span`1[System.Char],byref,byref):System.String
; Emitting BLENDED_CODE for X64 CPU with SSE2 - Windows
; Emitting BLENDED_CODE for X64 CPU with SSE2 - Windows
; ReadyToRun compilation
; ReadyToRun compilation
; optimized code
; optimized code
; rbp based frame
; rbp based frame
; fully interruptible
; fully interruptible
; discarded IBC profile data due to mismatch in ILSize
; discarded IBC profile data due to mismatch in ILSize
; Final local variable assignments
; Final local variable assignments
;
;
; V00 arg0 [V00,T33] ( 6, 4 ) bool -> rdi
; V00 arg0 [V00,T29] ( 6, 4 ) bool -> rdi
; V01 arg1 [V01,T29] ( 4, 8 ) byref -> rdx ld-addr-op
; V01 arg1 [V01,T25] ( 4, 8 ) byref -> rdx ld-addr-op
; V02 arg2 [V02,T35] ( 5, 3.50) ref -> rbx class-hnd
; V02 arg2 [V02,T31] ( 5, 3.50) ref -> rbx class-hnd
; V03 arg3 [V03,T28] ( 6, 9 ) byref -> rsi
; V03 arg3 [V03,T24] ( 6, 9 ) byref -> rsi
; V04 arg4 [V04,T44] ( 6, 3 ) ref -> [rbp+160H] class-hnd
; V04 arg4 [V04,T40] ( 6, 3 ) ref -> [rbp+150H] class-hnd
; V05 arg5 [V05,T43] ( 4, 4 ) byref -> r12
; V05 arg5 [V05,T39] ( 4, 4 ) byref -> r12
; V06 arg6 [V06,T41] ( 8, 4 ) byref -> r14
; V06 arg6 [V06,T37] ( 8, 4 ) byref -> r14
; V07 arg7 [V07,T42] ( 8, 4 ) byref -> r15
; V07 arg7 [V07,T38] ( 8, 4 ) byref -> [rbp+168H]
; V08 loc0 [V08 ] ( 12, 17 ) int -> [rbp+F0H] do-not-enreg[X] addr-exposed ld-addr-op
; V08 loc0 [V08 ] ( 12, 17 ) int -> [rbp+E0H] do-not-enreg[X] addr-exposed ld-addr-op
; V09 loc1 [V09,T30] ( 14, 8 ) ushort -> [rbp+ECH]
; V09 loc1 [V09,T26] ( 14, 8 ) ushort -> [rbp+DCH]
; V10 loc2 [V10,T60] ( 3, 1.50) int -> rbx
; V10 loc2 [V10,T56] ( 3, 1.50) int -> rbx
; V11 loc3 [V11,T63] ( 2, 1 ) int -> rcx
; V11 loc3 [V11,T59] ( 2, 1 ) int -> rcx
; V12 loc4 [V12,T09] ( 11, 49.50) ref -> [rbp+28H] class-hnd exact
; V12 loc4 [V12,T06] ( 11, 49.50) ref -> [rbp+28H] class-hnd exact
; V13 loc5 [V13,T15] ( 9, 27.50) int -> [rbp+E8H]
; V13 loc5 [V13,T13] ( 9, 27.50) int -> [rbp+D8H]
; V14 loc6 [V14,T36] ( 10, 5 ) int -> rbx
; V14 loc6 [V14,T32] ( 10, 5 ) int -> rbx
; V15 loc7 [V15,T61] ( 3, 1.50) bool -> [rbp+E4H]
; V15 loc7 [V15,T57] ( 3, 1.50) bool -> [rbp+D4H]
; V16 loc8 [V16,T64] ( 2, 1 ) int -> rax
; V16 loc8 [V16,T60] ( 2, 1 ) int -> rdx
; V17 loc9 [V17,T11] ( 13, 38.50) ref -> [rbp+20H] class-hnd exact
; V17 loc9 [V17,T09] ( 13, 38.50) ref -> [rbp+20H] class-hnd exact
; V18 loc10 [V18,T06] ( 23, 75.50) int -> [rbp+E0H]
; V18 loc10 [V18,T03] ( 23, 75.50) int -> [rbp+D0H]
; V19 loc11 [V19,T40] ( 2, 4.50) int -> rcx
; V19 loc11 [V19,T36] ( 2, 4.50) int -> r11
; V20 loc12 [V20,T65] ( 2, 1 ) int -> r13
; V20 loc12 [V20,T61] ( 2, 1 ) int -> r13
;* V21 loc13 [V21 ] ( 0, 0 ) ref -> zero-ref class-hnd
;* V21 loc13 [V21 ] ( 0, 0 ) ref -> zero-ref class-hnd
; V22 loc14 [V22,T19] ( 6, 16.50) int -> rbx
; V22 loc14 [V22,T17] ( 6, 16.50) int -> rbx
; V23 loc15 [V23,T08] ( 12, 52 ) int -> r11
; V23 loc15 [V23,T07] ( 10, 48 ) int -> r11
; V24 loc16 [V24,T05] ( 6, 82 ) int -> r10
; V24 loc16 [V24,T02] ( 6, 82 ) int -> r8
; V25 loc17 [V25,T02] ( 6, 96 ) long -> r11
; V25 loc17 [V25,T04] ( 4, 64 ) long -> r11
;* V26 loc18 [V26 ] ( 0, 0 ) ref -> zero-ref class-hnd
;* V26 loc18 [V26 ] ( 0, 0 ) ref -> zero-ref class-hnd
;* V27 loc19 [V27 ] ( 0, 0 ) ref -> zero-ref class-hnd
;* V27 loc19 [V27 ] ( 0, 0 ) ref -> zero-ref class-hnd
;* V28 loc20 [V28 ] ( 0, 0 ) ref -> zero-ref class-hnd
;* V28 loc20 [V28 ] ( 0, 0 ) ref -> zero-ref class-hnd
; V29 loc21 [V29,T18] ( 6, 20.50) int -> rcx
; V29 loc21 [V29,T16] ( 6, 20.50) int -> rdx
; V30 loc22 [V30,T12] ( 5, 36 ) int -> r10
; V30 loc22 [V30,T10] ( 5, 36 ) int -> r9
; V31 loc23 [V31,T01] ( 4,100 ) int -> [rbp+DCH]
; V31 loc23 [V31,T01] ( 4,100 ) int -> r11
; V32 loc24 [V32,T16] ( 7, 21 ) int -> r8
; V32 loc24 [V32,T14] ( 7, 21 ) int -> r11
; V33 loc25 [V33,T66] ( 2, 1 ) bool -> [rbp+D8H]
; V33 loc25 [V33,T62] ( 2, 1 ) bool -> [rbp+CCH]
;* V34 loc26 [V34 ] ( 0, 0 ) int -> zero-ref
;* V34 loc26 [V34 ] ( 0, 0 ) int -> zero-ref
; V35 loc27 [V35,T67] ( 2, 1 ) int -> rbx
; V35 loc27 [V35,T63] ( 2, 1 ) int -> rbx
; V36 loc28 [V36 ] ( 6, 3 ) struct (32) [rbp+B8H] do-not-enreg[XSFB] must-init addr-exposed ld-addr-op
; V36 loc28 [V36 ] ( 6, 3 ) struct (32) [rbp+A8H] do-not-enreg[XSFB] must-init addr-exposed ld-addr-op
; V37 loc29 [V37,T68] ( 2, 1 ) struct (16) [rbp+A8H] do-not-enreg[SB] must-init
; V37 loc29 [V37,T64] ( 2, 1 ) struct (16) [rbp+98H] do-not-enreg[SB] must-init
; V38 loc30 [V38,T38] ( 3, 5 ) ref -> rax class-hnd
; V38 loc30 [V38,T34] ( 3, 5 ) ref -> rax class-hnd
; V39 loc31 [V39,T17] ( 7, 21 ) int -> r10
; V39 loc31 [V39,T15] ( 7, 21 ) int -> r10
; V40 loc32 [V40 ] ( 2, 1 ) struct (16) [rbp+98H] do-not-enreg[XSB] must-init addr-exposed ld-addr-op
; V40 loc32 [V40 ] ( 2, 1 ) struct (16) [rbp+88H] do-not-enreg[XSB] must-init addr-exposed ld-addr-op
; V41 OutArgs [V41 ] ( 1, 1 ) lclBlk (64) [rsp+00H] "OutgoingArgSpace"
; V41 OutArgs [V41 ] ( 1, 1 ) lclBlk (64) [rsp+00H] "OutgoingArgSpace"
; V42 tmp1 [V42,T22] ( 2, 16 ) int -> rbx "dup spill"
; V42 tmp1 [V42,T20] ( 2, 16 ) int -> rbx "dup spill"
; V43 tmp2 [V43,T20] ( 4, 16 ) int -> rcx "impSpillLclRefs"
; V43 tmp2 [V43,T18] ( 4, 16 ) int -> rcx "impSpillLclRefs"
; V44 tmp3 [V44,T21] ( 4, 16 ) int -> rax "impSpillLclRefs"
; V44 tmp3 [V44,T19] ( 4, 16 ) int -> r8 "impSpillLclRefs"
; V45 tmp4 [V45,T62] ( 3, 1.50) int -> r11
; V45 tmp4 [V45,T58] ( 3, 1.50) int -> r11
; V46 tmp5 [V46,T00] ( 2,128 ) int -> rdx "dup spill"
; V46 tmp5 [V46,T00] ( 2,128 ) int -> r11 "dup spill"
; V47 tmp6 [V47,T14] ( 2, 32 ) int -> rax "dup spill"
; V47 tmp6 [V47,T12] ( 2, 32 ) int -> rcx "dup spill"
; V48 tmp7 [V48,T23] ( 2, 16 ) int -> rax "dup spill"
; V48 tmp7 [V48,T21] ( 2, 16 ) int -> rcx "dup spill"
; V49 tmp8 [V49 ] ( 3, 3 ) struct (16) [rbp+88H] do-not-enreg[XSB] must-init addr-exposed "NewObj constructor temp"
; V49 tmp8 [V49 ] ( 3, 3 ) struct (16) [rbp+78H] do-not-enreg[XSB] must-init addr-exposed "NewObj constructor temp"
; V50 tmp9 [V50,T24] ( 2, 16 ) int -> rcx "dup spill"
; V50 tmp9 [V50,T22] ( 2, 16 ) int -> rcx "dup spill"
; V51 tmp10 [V51,T25] ( 2, 16 ) int -> rdx "Strict ordering of exceptions for Array store"
; V51 tmp10 [V51,T23] ( 2, 16 ) int -> rdx "Strict ordering of exceptions for Array store"
; V52 tmp11 [V52,T31] ( 2, 8 ) int -> rax "dup spill"
; V52 tmp11 [V52,T27] ( 2, 8 ) int -> rcx "dup spill"
; V53 tmp12 [V53 ] ( 3, 3 ) struct (16) [rbp+78H] do-not-enreg[XSB] must-init addr-exposed "NewObj constructor temp"
; V53 tmp12 [V53 ] ( 3, 3 ) struct (16) [rbp+68H] do-not-enreg[XSB] must-init addr-exposed "NewObj constructor temp"
; V54 tmp13 [V54,T73] ( 2, 0 ) ref -> rsi class-hnd "impSpillSpecialSideEff"
; V54 tmp13 [V54,T69] ( 2, 0 ) ref -> rsi class-hnd "impSpillSpecialSideEff"
; V55 tmp14 [V55,T69] ( 3, 0 ) ref -> rdi class-hnd exact "NewObj constructor temp"
; V55 tmp14 [V55,T65] ( 3, 0 ) ref -> rdi class-hnd exact "NewObj constructor temp"
; V56 tmp15 [V56,T74] ( 2, 0 ) ref -> rsi class-hnd "impSpillSpecialSideEff"
; V56 tmp15 [V56,T70] ( 2, 0 ) ref -> rsi class-hnd "impSpillSpecialSideEff"
; V57 tmp16 [V57,T70] ( 3, 0 ) ref -> rdi class-hnd exact "NewObj constructor temp"
; V57 tmp16 [V57,T66] ( 3, 0 ) ref -> rdi class-hnd exact "NewObj constructor temp"
; V58 tmp17 [V58,T75] ( 2, 0 ) ref -> rsi class-hnd "impSpillSpecialSideEff"
; V58 tmp17 [V58,T71] ( 2, 0 ) ref -> rsi class-hnd "impSpillSpecialSideEff"
; V59 tmp18 [V59,T71] ( 3, 0 ) ref -> rdi class-hnd exact "NewObj constructor temp"
; V59 tmp18 [V59,T67] ( 3, 0 ) ref -> rdi class-hnd exact "NewObj constructor temp"
; V60 tmp19 [V60,T76] ( 2, 0 ) ref -> rsi class-hnd "impSpillSpecialSideEff"
; V60 tmp19 [V60,T72] ( 2, 0 ) ref -> rsi class-hnd "impSpillSpecialSideEff"
; V61 tmp20 [V61,T72] ( 3, 0 ) ref -> rdi class-hnd exact "NewObj constructor temp"
; V61 tmp20 [V61,T68] ( 3, 0 ) ref -> rdi class-hnd exact "NewObj constructor temp"
; V62 tmp21 [V62,T45] ( 3, 3 ) ref -> rax class-hnd exact "Single-def Box Helper"
; V62 tmp21 [V62,T41] ( 3, 3 ) ref -> rax class-hnd exact "Single-def Box Helper"
; V63 tmp22 [V63,T59] ( 3, 1.50) ref -> rbx
; V63 tmp22 [V63,T55] ( 3, 1.50) ref -> rbx
; V64 tmp23 [V64,T07] ( 2, 64 ) int -> r13 "Inlining Arg"
; V64 tmp23 [V64,T05] ( 2, 64 ) int -> r13 "Inlining Arg"
;* V65 tmp24 [V65 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SB] "Inlining Arg"
;* V65 tmp24 [V65 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SB] "Inlining Arg"
; V66 tmp25 [V66,T37] ( 5, 5 ) ref -> rax "Single return block return value"
; V66 tmp25 [V66,T33] ( 5, 5 ) ref -> rax "Single return block return value"
; V67 tmp26 [V67,T32] ( 6, 6.50) ref -> [rbp+18H] V69._bits(offs=0x00) P-INDEP "field V01._bits (fldOffset=0x0)"
; V67 tmp26 [V67,T28] ( 6, 6.50) ref -> [rbp+18H] V69._bits(offs=0x00) P-INDEP "field V01._bits (fldOffset=0x0)"
; V68 tmp27 [V68 ] ( 7, 4 ) int -> [rbp+74H] do-not-enreg[X] addr-exposed V69._sign(offs=0x08) P-INDEP "field V01._sign (fldOffset=0x8)"
; V68 tmp27 [V68 ] ( 7, 4 ) int -> [rbp+64H] do-not-enreg[X] addr-exposed V69._sign(offs=0x08) P-INDEP "field V01._sign (fldOffset=0x8)"
;* V69 tmp28 [V69 ] ( 0, 0 ) struct (16) zero-ref "Promoted implicit byref"
;* V69 tmp28 [V69 ] ( 0, 0 ) struct (16) zero-ref "Promoted implicit byref"
; V70 tmp29 [V70 ] ( 6, 8 ) struct (16) [rbp+60H] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument"
; V70 tmp29 [V70 ] ( 6, 8 ) struct (16) [rbp+50H] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument"
; V71 tmp30 [V71 ] ( 2, 2 ) struct (16) [rbp+50H] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument"
; V71 tmp30 [V71 ] ( 2, 2 ) struct (16) [rbp+40H] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument"
; V72 tmp31 [V72,T46] ( 3, 3 ) byref -> rdx stack-byref "BlockOp address local"
; V72 tmp31 [V72,T42] ( 3, 3 ) byref -> rdx stack-byref "BlockOp address local"
; V73 tmp32 [V73 ] ( 8, 8 ) struct (16) [rbp+40H] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument"
; V73 tmp32 [V73 ] ( 8, 8 ) struct (16) [rbp+30H] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument"
; V74 tmp33 [V74,T53] ( 2, 2 ) int -> rcx "argument with side effect"
; V74 tmp33 [V74,T49] ( 2, 2 ) int -> rcx "argument with side effect"
; V75 tmp34 [V75,T54] ( 2, 2 ) int -> r8 "argument with side effect"
; V75 tmp34 [V75,T50] ( 2, 2 ) int -> r8 "argument with side effect"
; V76 tmp35 [V76,T55] ( 2, 2 ) int -> r9 "argument with side effect"
; V76 tmp35 [V76,T51] ( 2, 2 ) int -> r9 "argument with side effect"
; V77 tmp36 [V77,T49] ( 2, 2 ) ref -> r13 "argument with side effect"
; V77 tmp36 [V77,T45] ( 2, 2 ) ref -> r13 "argument with side effect"
; V78 tmp37 [V78,T50] ( 2, 2 ) byref -> r14 "argument with side effect"
; V78 tmp37 [V78,T46] ( 2, 2 ) byref -> r14 "argument with side effect"
; V79 tmp38 [V79,T77] ( 2, 0 ) ref -> rdx "argument with side effect"
; V79 tmp38 [V79,T73] ( 2, 0 ) ref -> rdx "argument with side effect"
; V80 tmp39 [V80,T78] ( 2, 0 ) ref -> rdx "argument with side effect"
; V80 tmp39 [V80,T74] ( 2, 0 ) ref -> rdx "argument with side effect"
; V81 tmp40 [V81,T79] ( 2, 0 ) ref -> rdx "argument with side effect"
; V81 tmp40 [V81,T75] ( 2, 0 ) ref -> rdx "argument with side effect"
; V82 tmp41 [V82,T80] ( 2, 0 ) ref -> rdx "argument with side effect"
; V82 tmp41 [V82,T76] ( 2, 0 ) ref -> rdx "argument with side effect"
; V83 tmp42 [V83,T56] ( 2, 2 ) long -> rcx "argument with side effect"
; V83 tmp42 [V83,T52] ( 2, 2 ) long -> rcx "argument with side effect"
; V84 tmp43 [V84,T57] ( 2, 2 ) int -> r8 "argument with side effect"
; V84 tmp43 [V84,T53] ( 2, 2 ) int -> r8 "argument with side effect"
; V85 tmp44 [V85,T58] ( 2, 2 ) int -> r9 "argument with side effect"
; V85 tmp44 [V85,T54] ( 2, 2 ) int -> r9 "argument with side effect"
; V86 tmp45 [V86,T51] ( 2, 2 ) byref -> rcx "argument with side effect"
; V86 tmp45 [V86,T47] ( 2, 2 ) byref -> rcx "argument with side effect"
; V87 tmp46 [V87,T52] ( 2, 2 ) byref -> rcx "argument with side effect"
; V87 tmp46 [V87,T48] ( 2, 2 ) byref -> rcx "argument with side effect"
; V88 GsCookie [V88 ] ( 1, 1 ) long -> [rbp+10H] do-not-enreg[X] addr-exposed "GSSecurityCookie"
; V88 GsCookie [V88 ] ( 1, 1 ) long -> [rbp+10H] do-not-enreg[X] addr-exposed "GSSecurityCookie"
; V89 PSPSym [V89 ] ( 1, 1 ) long -> [rbp+00H] do-not-enreg[X] addr-exposed "PSPSym"
; V89 PSPSym [V89 ] ( 1, 1 ) long -> [rbp+00H] do-not-enreg[X] addr-exposed "PSPSym"
; V90 cse0 [V90,T13] ( 9, 33 ) int -> [rbp+3CH] "CSE - aggressive"
; V90 cse0 [V90,T11] ( 9, 33 ) int -> r9 "CSE - aggressive"
; V91 cse1 [V91,T34] ( 5, 6 ) int -> r8 "CSE - moderate"
; V91 cse1 [V91,T30] ( 5, 6 ) int -> r8 "CSE - moderate"
; V92 cse2 [V92,T39] ( 3, 5 ) int -> rsi "CSE - moderate"
; V92 cse2 [V92,T35] ( 3, 5 ) int -> rsi "CSE - moderate"
; V93 cse3 [V93,T48] ( 4, 2 ) int -> r10 "CSE - conservative"
; V93 cse3 [V93,T44] ( 4, 2 ) int -> r9 "CSE - conservative"
; V94 cse4 [V94,T10] ( 3, 48 ) long -> [rbp+30H] "CSE - aggressive"
; V94 cse4 [V94,T08] ( 3, 48 ) long -> r10 "CSE - aggressive"
; V95 rat0 [V95,T47] ( 3, 3 ) int -> rdx "ReplaceWithLclVar is creating a new local variable"
; V95 rat0 [V95,T43] ( 3, 3 ) int -> rdx "ReplaceWithLclVar is creating a new local variable"
; V96 rat1 [V96,T03] ( 3, 96 ) long -> rdx "ReplaceWithLclVar is creating a new local variable"
; V97 rat2 [V97,T04] ( 3, 96 ) long -> rdx "ReplaceWithLclVar is creating a new local variable"
; V98 rat3 [V98,T26] ( 3, 12 ) int -> rdx "ReplaceWithLclVar is creating a new local variable"
; V99 rat4 [V99,T27] ( 3, 12 ) int -> rdx "ReplaceWithLclVar is creating a new local variable"
;
;
; Lcl frame size = 312
; Lcl frame size = 296


G_M52061_IG01: ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M52061_IG01: ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
push rbp
push rbp
push r15
push r15
push r14
push r14
push r13
push r13
push r12
push r12
push rdi
push rdi
push rsi
push rsi
push rbx
push rbx
sub rsp, 312
sub rsp, 296
lea rbp, [rsp+40H]
lea rbp, [rsp+40H]
xorps xmm4, xmm4
xorps xmm4, xmm4
mov rax, -144
mov rax, -144
movaps xmmword ptr [rbp+rax+C0H], xmm4
movaps xmmword ptr [rbp+rax+D0H], xmm4
movaps xmmword ptr [rbp+rax+D0H], xmm4
movaps xmmword ptr [rbp+rax+E0H], xmm4
movaps xmmword ptr [rbp+rax+E0H], xmm4
movaps xmmword ptr [rbp+rax+F0H], xmm4
add rax, 48
add rax, 48
jne SHORT -5 instr
jne SHORT -5 instr
mov qword ptr [rbp+D0H], rax
mov qword ptr [rbp+C0H], rax
mov qword ptr [rbp], rsp
mov qword ptr [rbp], rsp
mov rax, qword ptr [(reloc)]
mov rax, qword ptr [(reloc)]
mov qword ptr [rbp+10H], rax
mov qword ptr [rbp+10H], rax
mov edi, ecx
mov edi, ecx
mov rbx, r8
mov rbx, r8
; gcrRegs +[rbx]
; gcrRegs +[rbx]
mov rsi, r9
mov rsi, r9
; byrRegs +[rsi]
; byrRegs +[rsi]
mov r13, gword ptr [rbp+160H]
mov r13, gword ptr [rbp+150H]
; gcrRegs +[r13]
; gcrRegs +[r13]
mov r12, bword ptr [rbp+168H]
mov r12, bword ptr [rbp+158H]
; byrRegs +[r12]
; byrRegs +[r12]
mov r14, bword ptr [rbp+170H]
mov r14, bword ptr [rbp+160H]
; byrRegs +[r14]
; byrRegs +[r14]
mov r15, bword ptr [rbp+178H]
mov r15, bword ptr [rbp+168H]
; byrRegs +[r15]
; byrRegs +[r15]
;; bbWeight=1 PerfScore 29.33
;; bbWeight=1 PerfScore 29.33
G_M52061_IG02: ; gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D044 {rdx rsi r12 r14 r15}, byref
G_M52061_IG02: ; gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D044 {rdx rsi r12 r14 r15}, byref
; byrRegs +[rdx]
; byrRegs +[rdx]
mov rax, gword ptr [rdx]
mov rax, gword ptr [rdx]
; gcrRegs +[rax]
; gcrRegs +[rax]
mov gword ptr [rbp+18H], rax
mov gword ptr [rbp+18H], rax
; GC ptr vars +{V67}
; GC ptr vars +{V67}
mov ecx, dword ptr [rdx+8]
mov ecx, dword ptr [rdx+8]
mov dword ptr [rbp+74H], ecx
mov dword ptr [rbp+64H], ecx
;; bbWeight=1 PerfScore 6.00
;; bbWeight=1 PerfScore 6.00
G_M52061_IG03: ; gcVars=0000000000000000 {V67}, gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref
G_M52061_IG03: ; gcVars=0000000010000000 {V67}, gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref
; gcrRegs -[rax]
; gcrRegs -[rax]
; byrRegs -[rdx]
; byrRegs -[rdx]
xor ecx, ecx
xor ecx, ecx
mov dword ptr [rbp+F0H], ecx
mov dword ptr [rbp+E0H], ecx
;; bbWeight=1 PerfScore 1.25
;; bbWeight=1 PerfScore 1.25
G_M52061_IG04: ; , nogc, extend
G_M52061_IG04: ; , nogc, extend
movups xmm0, xmmword ptr [rsi]
movups xmm0, xmmword ptr [rsi]
movups xmmword ptr [rbp+60H], xmm0
movups xmmword ptr [rbp+50H], xmm0
;; bbWeight=1 PerfScore 6.00
;; bbWeight=1 PerfScore 6.00
G_M52061_IG05: ; , isz, extend
G_M52061_IG05: ; , isz, extend
lea rcx, bword ptr [rbp+60H]
lea rcx, bword ptr [rbp+50H]
; byrRegs +[rcx]
; byrRegs +[rcx]
lea rdx, [rbp+F0H]
lea rdx, [rbp+E0H]
call [System.Numerics.BigNumber:ParseFormatSpecifier()]
call [System.Numerics.BigNumber:ParseFormatSpecifier()]
; byrRegs -[rcx]
; byrRegs -[rcx]
; gcr arg pop 0
; gcr arg pop 0
movzx rax, ax
movzx rax, ax
mov r8d, eax
mov r8d, eax
cmp r8d, 120
cmp r8d, 120
je SHORT G_M52061_IG07
je SHORT G_M52061_IG07
;; bbWeight=1 PerfScore 5.75
;; bbWeight=1 PerfScore 5.75
G_M52061_IG06: ; gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
G_M52061_IG06: ; gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
cmp r8d, 88
cmp r8d, 88
jne SHORT G_M52061_IG10
jne SHORT G_M52061_IG10
;; bbWeight=0.50 PerfScore 0.62
;; bbWeight=0.50 PerfScore 0.63
G_M52061_IG07: ; gcrefRegs=00002000 {r13}, byrefRegs=0000D000 {r12 r14 r15}, byref
G_M52061_IG07: ; gcrefRegs=00002000 {r13}, byrefRegs=0000D000 {r12 r14 r15}, byref
; gcrRegs -[rbx]
; gcrRegs -[rbx]
; byrRegs -[rsi]
; byrRegs -[rsi]
movzx rcx, dil
movzx rcx, dil
lea rdx, bword ptr [rbp+50H]
lea rdx, bword ptr [rbp+40H]
; byrRegs +[rdx]
; byrRegs +[rdx]
mov rdi, gword ptr [rbp+18H]
mov rdi, gword ptr [rbp+18H]
; gcrRegs +[rdi]
; gcrRegs +[rdi]
mov gword ptr [rdx], rdi
mov gword ptr [rdx], rdi
mov r9d, dword ptr [rbp+74H]
mov r9d, dword ptr [rbp+64H]
mov dword ptr [rdx+8], r9d
mov dword ptr [rdx+8], r9d
mov r9d, dword ptr [rbp+F0H]
mov r9d, dword ptr [rbp+E0H]
;; bbWeight=0.50 PerfScore 2.88
;; bbWeight=0.50 PerfScore 2.88
G_M52061_IG08: ; , nogc, extend
G_M52061_IG08: ; , nogc, extend
movups xmm0, xmmword ptr [r12]
movups xmm0, xmmword ptr [r12]
movups xmmword ptr [rbp+40H], xmm0
movups xmmword ptr [rbp+30H], xmm0
;; bbWeight=0.50 PerfScore 3.00
;; bbWeight=0.50 PerfScore 3.00
G_M52061_IG09: ; , extend
G_M52061_IG09: ; , extend
mov bword ptr [rsp+30H], r14
mov bword ptr [rsp+30H], r14
; byr arg write
; byr arg write
mov bword ptr [rsp+38H], r15
mov bword ptr [rsp+38H], r15
; byr arg write
; byr arg write
lea rdx, bword ptr [rbp+50H]
lea rdx, bword ptr [rbp+40H]
mov gword ptr [rsp+20H], r13
mov gword ptr [rsp+20H], r13
; gcr arg write
; gcr arg write
lea rax, bword ptr [rbp+40H]
lea rax, bword ptr [rbp+30H]
; byrRegs +[rax]
; byrRegs +[rax]
mov bword ptr [rsp+28H], rax
mov bword ptr [rsp+28H], rax
; byr arg write
; byr arg write
; GC ptr vars -{V67}
; GC ptr vars -{V67}
call [System.Numerics.BigNumber:FormatBigIntegerToHex()]
call [System.Numerics.BigNumber:FormatBigIntegerToHex()]
; gcrRegs -[rdi r13] +[rax]
; gcrRegs -[rdi r13] +[rax]
; byrRegs -[rax rdx r12 r14-r15]
; byrRegs -[rax rdx r12 r14-r15]
; gcr arg pop 0
; gcr arg pop 0
jmp G_M52061_IG75
jmp G_M52061_IG75
;; bbWeight=0.50 PerfScore 5.00
;; bbWeight=0.50 PerfScore 5.00
G_M52061_IG10: ; gcVars=0000000000000000 {V67}, gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref, isz
G_M52061_IG10: ; gcVars=0000000010000000 {V67}, gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref, isz
; gcrRegs -[rax] +[rbx r13]
; gcrRegs -[rax] +[rbx r13]
; byrRegs +[rsi r12 r14-r15]
; byrRegs +[rsi r12 r14-r15]
; GC ptr vars +{V32 V67}
; GC ptr vars +{V67}
mov rdx, gword ptr [rbp+18H]
mov rdx, gword ptr [rbp+18H]
; gcrRegs +[rdx]
; gcrRegs +[rdx]
test rdx, rdx
test rdx, rdx
jne G_M52061_IG19
jne G_M52061_IG19
cmp r8d, 103
cmp r8d, 103
je SHORT G_M52061_IG11
je SHORT G_M52061_IG11
cmp r8d, 71
cmp r8d, 71
je SHORT G_M52061_IG11
je SHORT G_M52061_IG11
cmp r8d, 114
cmp r8d, 114
je SHORT G_M52061_IG11
je SHORT G_M52061_IG11
cmp r8d, 82
cmp r8d, 82
jne SHORT G_M52061_IG14
jne SHORT G_M52061_IG14
;; bbWeight=0.50 PerfScore 3.62
;; bbWeight=0.50 PerfScore 3.63
G_M52061_IG11: ; gcVars=0000000000000000 {}, gcrefRegs=00002000 {r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref, isz
G_M52061_IG11: ; gcVars=0000000000000000 {}, gcrefRegs=00002000 {r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref, isz
; gcrRegs -[rdx rbx]
; gcrRegs -[rdx rbx]
; GC ptr vars -{V32 V67}
; GC ptr vars -{V67}
cmp dword ptr [rbp+F0H], 0
cmp dword ptr [rbp+E0H], 0
jg SHORT G_M52061_IG12
jg SHORT G_M52061_IG12
mov rax, qword ptr [(reloc)]
mov rax, qword ptr [(reloc)]
mov rbx, gword ptr [rax]
mov rbx, gword ptr [rax]
; gcrRegs +[rbx]
; gcrRegs +[rbx]
jmp SHORT G_M52061_IG13
jmp SHORT G_M52061_IG13
;; bbWeight=0.50 PerfScore 4.00
;; bbWeight=0.50 PerfScore 4.00
G_M52061_IG12: ; gcrefRegs=00002000 {r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
G_M52061_IG12: ; gcrefRegs=00002000 {r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
; gcrRegs -[rbx]
; gcrRegs -[rbx]
call [CORINFO_HELP_READYTORUN_NEW]
call [CORINFO_HELP_READYTORUN_NEW]
; gcrRegs +[rax]
; gcrRegs +[rax]
; gcr arg pop 0
; gcr arg pop 0
mov edx, dword ptr [rbp+F0H]
mov edx, dword ptr [rbp+E0H]
mov dword ptr [rax+8], edx
mov dword ptr [rax+8], edx
mov rdx, rax
mov rdx, rax
; gcrRegs +[rdx]
; gcrRegs +[rdx]
mov rcx, qword ptr [(reloc)]
mov rcx, qword ptr [(reloc)]
mov rcx, gword ptr [rcx]
mov rcx, gword ptr [rcx]
; gcrRegs +[rcx]
; gcrRegs +[rcx]
call [System.String:Format()]
call [System.String:Format()]
; gcrRegs -[rcx rdx]
; gcrRegs -[rcx rdx]
; gcr arg pop 0
; gcr arg pop 0
mov rbx, rax
mov rbx, rax
; gcrRegs +[rbx]
; gcrRegs +[rbx]
;; bbWeight=0.50 PerfScore 6.25
;; bbWeight=0.50 PerfScore 6.25
G_M52061_IG13: ; gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
G_M52061_IG13: ; gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
; gcrRegs -[rax]
; gcrRegs -[rax]
mov rcx, rsi
mov rcx, rsi
; byrRegs +[rcx]
; byrRegs +[rcx]
mov rdx, rbx
mov rdx, rbx
; gcrRegs +[rdx]
; gcrRegs +[rdx]
call [System.String:op_Implicit()]
call [System.String:op_Implicit()]
; gcrRegs -[rdx]
; gcrRegs -[rdx]
; byrRegs -[rcx]
; byrRegs -[rcx]
; gcr arg pop 0
; gcr arg pop 0
;; bbWeight=0.50 PerfScore 1.75
;; bbWeight=0.50 PerfScore 1.75
G_M52061_IG14: ; gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
G_M52061_IG14: ; gcrefRegs=00002008 {rbx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
test dil, dil
test dil, dil
je SHORT G_M52061_IG18
je SHORT G_M52061_IG18
;; bbWeight=0.50 PerfScore 0.62
;; bbWeight=0.50 PerfScore 0.63
G_M52061_IG15: ; , nogc, extend
G_M52061_IG15: ; , nogc, extend
movups xmm0, xmmword ptr [r12]
movups xmm0, xmmword ptr [r12]
movups xmmword ptr [rbp+40H], xmm0
movups xmmword ptr [rbp+30H], xmm0
;; bbWeight=0.50 PerfScore 3.00
;; bbWeight=0.50 PerfScore 3.00
G_M52061_IG16: ; , nogc, extend
G_M52061_IG16: ; , nogc, extend
movups xmm0, xmmword ptr [rsi]
movups xmm0, xmmword ptr [rsi]
movups xmmword ptr [rbp+60H], xmm0
movups xmmword ptr [rbp+50H], xmm0
;; bbWeight=0.50 PerfScore 3.00
;; bbWeight=0.50 PerfScore 3.00
G_M52061_IG17: ; , extend
G_M52061_IG17: ; , extend
mov gword ptr [rsp+20H], r13
mov gword ptr [rsp+20H], r13
; gcr arg write
; gcr arg write
lea rdx, bword ptr [rbp+40H]
lea rdx, bword ptr [rbp+30H]
; byrRegs +[rdx]
; byrRegs +[rdx]
mov r8, r14
mov r8, r14
; byrRegs +[r8]
; byrRegs +[r8]
lea r9, bword ptr [rbp+60H]
lea r9, bword ptr [rbp+50H]
; byrRegs +[r9]
; byrRegs +[r9]
lea rcx, bword ptr [rbp+74H]
lea rcx, bword ptr [rbp+64H]
; byrRegs +[rcx]
; byrRegs +[rcx]
call [System.Int32:TryFormat()]
call [System.Int32:TryFormat()]
; gcrRegs -[rbx r13]
; gcrRegs -[rbx r13]
; byrRegs -[rcx rdx rsi r8-r9 r12 r14]
; byrRegs -[rcx rdx rsi r8-r9 r12 r14]
; gcr arg pop 0
; gcr arg pop 0
mov byte ptr [r15], al
mov byte ptr [r15], al
jmp G_M52061_IG72
jmp G_M52061_IG72
;; bbWeight=0.50 PerfScore 4.38
;; bbWeight=0.50 PerfScore 4.38
G_M52061_IG18: ; gcrefRegs=00002008 {rbx r13}, byrefRegs=0000C000 {r14 r15}, byref
G_M52061_IG18: ; gcrefRegs=00002008 {rbx r13}, byrefRegs=0000C000 {r14 r15}, byref
; gcrRegs +[rbx r13]
; gcrRegs +[rbx r13]
; byrRegs +[r14]
; byrRegs +[r14]
xor ecx, ecx
xor ecx, ecx
mov dword ptr [r14], ecx
mov dword ptr [r14], ecx
mov byte ptr [r15], 0
mov byte ptr [r15], 0
lea rcx, bword ptr [rbp+74H]
lea rcx, bword ptr [rbp+64H]
; byrRegs +[rcx]
; byrRegs +[rcx]
mov rdx, rbx
mov rdx, rbx
; gcrRegs +[rdx]
; gcrRegs +[rdx]
mov r8, r13
mov r8, r13
; gcrRegs +[r8]
; gcrRegs +[r8]
call [System.Int32:ToString()]
call [System.Int32:ToString()]
; gcrRegs -[rdx rbx r8 r13] +[rax]
; gcrRegs -[rdx rbx r8 r13] +[rax]
; byrRegs -[rcx r14-r15]
; byrRegs -[rcx r14-r15]
; gcr arg pop 0
; gcr arg pop 0
jmp G_M52061_IG75
jmp G_M52061_IG75
;; bbWeight=0.50 PerfScore 4.12
;; bbWeight=0.50 PerfScore 4.13
G_M52061_IG19: ; gcrefRegs=00002004 {rdx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
G_M52061_IG19: ; gcrefRegs=00002004 {rdx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
; gcrRegs -[rax] +[rdx r13]
; gcrRegs -[rax] +[rdx r13]
; byrRegs +[rsi r12 r14-r15]
; byrRegs +[rsi r12 r14-r15]
mov gword ptr [rbp+18H], rdx
mov gword ptr [rbp+18H], rdx
; GC ptr vars +{V67}
; GC ptr vars +{V67}
mov ebx, dword ptr [rdx+8]
mov ebx, dword ptr [rdx+8]
;; bbWeight=0.50 PerfScore 1.50
;; bbWeight=0.50 PerfScore 1.50
G_M52061_IG20: ; gcVars=0000000000000000 {V67}, gcrefRegs=00002000 {r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref, isz
G_M52061_IG20: ; gcVars=0000000010000000 {V67}, gcrefRegs=00002000 {r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref, isz
; gcrRegs -[rdx]
; gcrRegs -[rdx]
imul ecx, ebx, 10
imul ecx, ebx, 10
jo SHORT G_M52061_IG21
jo SHORT G_M52061_IG21
mov r9d, 0xD1FFAB1E
mov r9d, 0xD1FFAB1E
mov eax, r9d
mov eax, r9d
imul edx:eax, ecx
imul edx:eax, ecx
mov ecx, edx
mov ecx, edx
shr ecx, 31
shr ecx, 31
sar edx, 1
sar edx, 1
add ecx, edx
add ecx, edx
add ecx, 2
add ecx, 2
jo SHORT G_M52061_IG21
jo SHORT G_M52061_IG21
jmp SHORT G_M52061_IG22
jmp SHORT G_M52061_IG22
;; bbWeight=0.50 PerfScore 5.88
;; bbWeight=0.50 PerfScore 5.88
G_M52061_IG21: ; gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M52061_IG21: ; gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
; gcrRegs -[r13]
; gcrRegs -[r13]
; byrRegs -[rsi r12 r14-r15]
; byrRegs -[rsi r12 r14-r15]
; GC ptr vars -{V67}
; GC ptr vars -{V67}
call [CORINFO_HELP_OVERFLOW]
call [CORINFO_HELP_OVERFLOW]
; gcr arg pop 0
; gcr arg pop 0
int3
int3
;; bbWeight=0 PerfScore 0.00
;; bbWeight=0 PerfScore 0.00
G_M52061_IG22: ; gcVars=0000000000000000 {V67}, gcrefRegs=00002000 {r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref
G_M52061_IG22: ; gcVars=0000000010000000 {V67}, gcrefRegs=00002000 {r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref
; gcrRegs +[r13]
; gcrRegs +[r13]
; byrRegs +[rsi r12 r14-r15]
; byrRegs +[rsi r12 r14-r15]
; GC ptr vars +{V32 V67}
; GC ptr vars +{V67}
mov dword ptr [rbp+ECH], r8d
mov dword ptr [rbp+DCH], r8d
movsxd rcx, ecx
movsxd rcx, ecx
call [CORINFO_HELP_READYTORUN_NEWARR_1]
call [CORINFO_HELP_READYTORUN_NEWARR_1]
; gcrRegs +[rax]
; gcrRegs +[rax]
; gcr arg pop 0
; gcr arg pop 0
mov r8, rax
; gcrRegs +[r8]
xor ecx, ecx
xor ecx, ecx
jmp G_M52061_IG27
jmp G_M52061_IG27
;; bbWeight=0.50 PerfScore 3.38
;; bbWeight=0.50 PerfScore 3.25
G_M52061_IG23: ; gcrefRegs=00002100 {r8 r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
G_M52061_IG23: ; gcrefRegs=00002001 {rax r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
; gcrRegs -[rax]
mov rdx, gword ptr [rbp+18H]
mov r9, gword ptr [rbp+18H]
; gcrRegs +[rdx]
; gcrRegs +[r9]
cmp ebx, dword ptr [rdx+8]
cmp ebx, dword ptr [r9+8]
jae G_M52061_IG78
jae G_M52061_IG78
movsxd rax, ebx
movsxd r11, ebx
mov r11d, dword ptr [r9+4*rax+16]
mov r11d, dword ptr [rdx+4*r11+16]
xor r10d, r10d
xor r8d, r8d
test ecx, ecx
test ecx, ecx
jle G_M52061_IG26
jle G_M52061_IG26
mov eax, dword ptr [r8+8]
mov r9d, dword ptr [rax+8]
mov gword ptr [rbp+160H], r13
mov gword ptr [rbp+18H], rdx
;; bbWeight=2 PerfScore 21.50
mov gword ptr [rbp+150H], r13
G_M52061_IG24: ; gcVars=0000000000000000 {}, gcrefRegs=00000300 {r8 r9}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref
;; bbWeight=2 PerfScore 23.50
; gcrRegs -[r13]
G_M52061_IG24: ; gcrefRegs=00000001 {rax}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
; GC ptr vars -{V32 V67}
; gcrRegs -[rdx r13]
mov dword ptr [rbp+3CH], eax
cmp r8d, r9d
cmp r10d, eax
jae G_M52061_IG78
jae G_M52061_IG78
movsxd rdx, r10d
movsxd r10, r8d
mov qword ptr [rbp+30H], rdx
mov gword ptr [rbp+28H], rax
mov r13d, dword ptr [r8+4*rdx+16]
; GC ptr vars +{V12}
mov r13d, dword ptr [rax+4*r10+16]
shl r13, 32
shl r13, 32
mov r11d, r11d
mov r11d, r11d
or r11, r13
or r11, r13
mov r13, 0xD1FFAB1E
mov r13, 0xD1FFAB1E
mov rax, r11
mov rax, r11
; gcrRegs -[rax]
shr rax, 9
mul rdx:rax, r13
mul rdx:rax, r13
mov rax, r11
shr rdx, 11
sub rax, rdx
imul rax, rdx, 0xD1FFAB1E
shr rax, 1
add rax, rdx
shr rax, 29
imul rax, rax, 0xD1FFAB1E
mov rdx, r11
mov rdx, r11
sub rdx, rax
sub rdx, rax
mov eax, edx
mov eax, edx
mov r13, qword ptr [rbp+30H]
mov r13, gword ptr [rbp+28H]
mov dword ptr [r8+4*r13+16], eax
; gcrRegs +[r13]
mov dword ptr [r13+4*r10+16], eax
mov rdx, 0xD1FFAB1E
mov rdx, 0xD1FFAB1E
mov rax, r11
mov rax, r11
shr rax, 9
mul rdx:rax, rdx
mul rdx:rax, rdx
sub r11, rdx
shr rdx, 11
shr r11, 1
add rdx, r11
shr rdx, 29
mov r11d, edx
mov r11d, edx
inc r10d
inc r8d
cmp r10d, ecx
cmp r8d, ecx
mov eax, dword ptr [rbp+3CH]
mov rax, r13
jl G_M52061_IG24
; gcrRegs +[rax]
jl SHORT G_M52061_IG24
;; bbWeight=16 PerfScore 428.00
;; bbWeight=16 PerfScore 428.00
G_M52061_IG25: ; gcrefRegs=00000300 {r8 r9}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
G_M52061_IG25: ; gcrefRegs=00000001 {rax}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
mov r13, gword ptr [rbp+160H]
; gcrRegs -[r13]
; GC ptr vars -{V12}
mov rdx, gword ptr [rbp+18H]
; gcrRegs +[rdx]
mov r13, gword ptr [rbp+150H]
; gcrRegs +[r13]
; gcrRegs +[r13]
;; bbWeight=8 PerfScore 8.00
;; bbWeight=8 PerfScore 16.00
G_M52061_IG26: ; gcrefRegs=00002300 {r8 r9 r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
G_M52061_IG26: ; gcVars=0000000000000000 {}, gcrefRegs=00002005 {rax rdx r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref, isz
; GC ptr vars -{V67}
test r11d, r11d
test r11d, r11d
mov gword ptr [rbp+18H], r9
mov gword ptr [rbp+18H], rdx
; GC ptr vars +{V67}
; GC ptr vars +{V67}
je G_M52061_IG27
je SHORT G_M52061_IG27
lea eax, [rcx+1]
lea r8d, [rcx+1]
mov dword ptr [rbp+E8H], eax
mov r9d, r11d
mov edx, 0xD1FFAB1E
shr r9d, 9
mov eax, r11d
imul r9, r9, 0xD1FFAB1E
mul edx:eax, edx
shr r9, 39
mov eax, r11d
imul r9d, r9d, 0xD1FFAB1E
sub eax, edx
mov r10d, r11d
shr eax, 1
sub r10d, r9d
add eax, edx
mov r9d, dword ptr [rax+8]
shr eax, 29
cmp ecx, r9d
imul eax, eax, 0xD1FFAB1E
mov edx, r11d
sub edx, eax
mov r10d, dword ptr [r8+8]
cmp ecx, r10d
jae G_M52061_IG78
jae G_M52061_IG78
movsxd rax, ecx
movsxd rcx, ecx
mov dword ptr [r8+4*rax+16], edx
mov dword ptr [rax+4*rcx+16], r10d
mov edx, 0xD1FFAB1E
shr r11d, 9
mov eax, r11d
imul r11, r11, 0xD1FFAB1E
mul edx:eax, edx
shr r11, 39
sub r11d, edx
shr r11d, 1
add r11d, edx
shr r11d, 29
test r11d, r11d
test r11d, r11d
mov ecx, dword ptr [rbp+E8H]
mov ecx, r8d
je SHORT G_M52061_IG27
je SHORT G_M52061_IG27
mov eax, ecx
mov r8d, ecx
lea ecx, [rax+1]
lea ecx, [r8+1]
cmp eax, r10d
cmp r8d, r9d
jae G_M52061_IG78
jae G_M52061_IG78
movsxd rax, eax
movsxd r8, r8d
mov gword ptr [rbp+28H], r8
mov gword ptr [rbp+28H], rax
; GC ptr vars +{V12}
; GC ptr vars +{V12}
mov dword ptr [r8+4*rax+16], r11d
mov dword ptr [rax+4*r8+16], r11d
mov r8, gword ptr [rbp+28H]
mov rax, gword ptr [rbp+28H]
;; bbWeight=2 PerfScore 59.00
;; bbWeight=2 PerfScore 57.50
G_M52061_IG27: ; gcVars=0000000000000000 {V67}, gcrefRegs=00002100 {r8 r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref
G_M52061_IG27: ; gcVars=0000000010000000 {V67}, gcrefRegs=00002001 {rax r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref
; gcrRegs -[r9]
; gcrRegs -[rdx]
; GC ptr vars -{V12}
; GC ptr vars -{V12}
dec ebx
dec ebx
test ebx, ebx
test ebx, ebx
jge G_M52061_IG23
jge G_M52061_IG23
;; bbWeight=4 PerfScore 6.00
;; bbWeight=4 PerfScore 6.00
G_M52061_IG28: ; gcVars=0000000000000000 {}, gcrefRegs=00002100 {r8 r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref, isz
G_M52061_IG28: ; gcVars=0000000000000000 {}, gcrefRegs=00002001 {rax r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, gcvars, byref, isz
; GC ptr vars -{V67}
; GC ptr vars -{V67}
mov dword ptr [rbp+E8H], ecx
mov dword ptr [rbp+D8H], ecx
imul ebx, ecx, 9
imul ebx, ecx, 9
jo SHORT G_M52061_IG29
jo SHORT G_M52061_IG29
jmp SHORT G_M52061_IG30
jmp SHORT G_M52061_IG30
;; bbWeight=0.50 PerfScore 3.00
;; bbWeight=0.50 PerfScore 3.00
G_M52061_IG29: ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M52061_IG29: ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
; gcrRegs -[r8 r13]
; gcrRegs -[rax r13]
; byrRegs -[rsi r12 r14-r15]
; byrRegs -[rsi r12 r14-r15]
call [CORINFO_HELP_OVERFLOW]
call [CORINFO_HELP_OVERFLOW]
; gcr arg pop 0
; gcr arg pop 0
int3
int3
;; bbWeight=0 PerfScore 0.00
;; bbWeight=0 PerfScore 0.00
G_M52061_IG30: ; gcrefRegs=00002100 {r8 r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
G_M52061_IG30: ; gcrefRegs=00002001 {rax r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
; gcrRegs +[r8 r13]
; gcrRegs +[rax r13]
; byrRegs +[rsi r12 r14-r15]
; byrRegs +[rsi r12 r14-r15]
mov eax, dword ptr [rbp+ECH]
mov r8d, dword ptr [rbp+DCH]
cmp eax, 103
cmp r8d, 103
je SHORT G_M52061_IG31
je SHORT G_M52061_IG31
cmp eax, 71
cmp r8d, 71
je SHORT G_M52061_IG31
je SHORT G_M52061_IG31
cmp eax, 100
cmp r8d, 100
je SHORT G_M52061_IG31
je SHORT G_M52061_IG31
cmp eax, 68
cmp r8d, 68
je SHORT G_M52061_IG31
je SHORT G_M52061_IG31
cmp eax, 114
cmp r8d, 114
je SHORT G_M52061_IG31
je SHORT G_M52061_IG31
cmp eax, 82
cmp r8d, 82
sete r11b
sete r11b
movzx r11, r11b
movzx r11, r11b
jmp SHORT G_M52061_IG32
jmp SHORT G_M52061_IG32
;; bbWeight=0.50 PerfScore 5.38
;; bbWeight=0.50 PerfScore 5.38
G_M52061_IG31: ; gcrefRegs=00002100 {r8 r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
G_M52061_IG31: ; gcrefRegs=00002001 {rax r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref
mov r11d, 1
mov r11d, 1
;; bbWeight=0.50 PerfScore 0.12
;; bbWeight=0.50 PerfScore 0.13
G_M52061_IG32: ; gcrefRegs=00002100 {r8 r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
G_M52061_IG32: ; gcrefRegs=00002001 {rax r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
movzx rdx, r11b
movzx r10, r11b
mov dword ptr [rbp+E4H], edx
mov dword ptr [rbp+D4H], r10d
test edx, edx
test r10d, r10d
je SHORT G_M52061_IG36
je SHORT G_M52061_IG36
cmp dword ptr [rbp+F0H], 0
cmp dword ptr [rbp+E0H], 0
jle SHORT G_M52061_IG33
jle SHORT G_M52061_IG33
cmp dword ptr [rbp+F0H], ebx
cmp dword ptr [rbp+E0H], ebx
jle SHORT G_M52061_IG33
jle SHORT G_M52061_IG33
mov ebx, dword ptr [rbp+F0H]
mov ebx, dword ptr [rbp+E0H]
;; bbWeight=0.50 PerfScore 3.75
;; bbWeight=0.50 PerfScore 3.75
G_M52061_IG33: ; gcrefRegs=00002100 {r8 r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
G_M52061_IG33: ; gcrefRegs=00002001 {rax r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
cmp dword ptr [rbp+74H], 0
cmp dword ptr [rbp+64H], 0
jge SHORT G_M52061_IG36
jge SHORT G_M52061_IG36
;; bbWeight=0.50 PerfScore 1.00
;; bbWeight=0.50 PerfScore 1.00
G_M52061_IG34: ; gcrefRegs=00002100 {r8 r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
G_M52061_IG34: ; gcrefRegs=00002001 {rax r13}, byrefRegs=0000D040 {rsi r12 r14 r15}, byref, isz
mov gword ptr [rbp+28H], r8
mov gword ptr [rbp+28H], rax
; GC ptr vars +{V12}
; GC ptr vars +{V12}
mov gword ptr [rbp+160H], r13
mov gword ptr [rbp+150H], r13
mov rcx, r13
mov rcx, r13
; gcrRegs +[rcx]
; gcrRegs +[rcx]
lea r11, [(reloc
lea r11, [(reloc)]
cmp dword ptr [rcx], ecx
call [hackishModuleName:hackishMethodName():System.String:this]
; gcrRegs -[rcx r13]
; gcr arg pop 0
add ebx, dword ptr [rax+8]
jo SHORT G_M52061_IG35
mov rax, gword ptr [rbp+28H]
mov r13, gword ptr [rbp+150H]
; gcrRegs +[r13]
jmp SHORT G_M52061_IG36
;; bbWeight=0.50 PerfScore 7.38
G_M52061_IG35: ; gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
; gcrRegs -[rax r13]
; byrRegs -[rsi r12 r14-r15]
; GC ptr vars -{V12}
call [CORINFO_HELP_OVERFLOW]
; gcr arg pop 0
int3
;; bbW