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11 eliminaciones
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160 líneas
; Assembly listing for method Number:TryUInt32ToDecStr(int,int,Span`1,byref):bool
; Assembly listing for method Number:TryUInt32ToDecStr(int,int,Span`1,byref):bool
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; Emitting BLENDED_CODE for generic ARM64 CPU - Windows
; optimized code
; optimized code
; fp based frame
; fp based frame
; fully interruptible
; fully interruptible
; No PGO data
; No PGO data
; 0 inlinees with PGO data; 4 single block inlinees; 2 inlinees without PGO data
; 0 inlinees with PGO data; 4 single block inlinees; 2 inlinees without PGO data
; invoked as altjit
; invoked as altjit
; Final local variable assignments
; Final local variable assignments
;
;
; V00 arg0 [V00,T00] ( 9, 20 ) int -> [fp+1CH]
; V00 arg0 [V00,T00] ( 9, 20 ) int -> [fp+1CH]
; V01 arg1 [V01,T07] ( 6, 4.50) int -> [fp+18H] single-def
; V01 arg1 [V01,T07] ( 6, 4.50) int -> [fp+18H] single-def
;* V02 arg2 [V02 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def
;* V02 arg2 [V02 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def
; V03 arg3 [V03,T08] ( 4, 3 ) byref -> x4 single-def
; V03 arg3 [V03,T08] ( 4, 3 ) byref -> x4 single-def
; V04 loc0 [V04,T11] ( 4, 3 ) int -> x6
; V04 loc0 [V04,T11] ( 4, 3 ) int -> x6
;* V05 loc1 [V05 ] ( 0, 0 ) long -> zero-ref
;* V05 loc1 [V05 ] ( 0, 0 ) long -> zero-ref
; V06 loc2 [V06 ] ( 2, 1 ) byref -> [fp+10H] must-init pinned
; V06 loc2 [V06 ] ( 2, 1 ) byref -> [fp+10H] must-init pinned
; V07 loc3 [V07,T02] ( 5, 13 ) long -> x2
; V07 loc3 [V07,T02] ( 5, 13 ) long -> x2
;* V08 loc4 [V08 ] ( 0, 0 ) int -> zero-ref
;* V08 loc4 [V08 ] ( 0, 0 ) int -> zero-ref
;# V09 OutArgs [V09 ] ( 1, 1 ) lclBlk ( 0) [sp+00H] "OutgoingArgSpace"
;# V09 OutArgs [V09 ] ( 1, 1 ) lclBlk ( 0) [sp+00H] "OutgoingArgSpace"
;* V10 tmp1 [V10 ] ( 0, 0 ) struct ( 8) zero-ref "dup spill"
;* V10 tmp1 [V10 ] ( 0, 0 ) struct ( 8) zero-ref "dup spill"
; V11 tmp2 [V11,T01] ( 2, 16 ) long -> x2 "dup spill"
; V11 tmp2 [V11,T01] ( 2, 16 ) long -> x2 "dup spill"
; V12 tmp3 [V12,T06] ( 12, 7 ) int -> x6 "Inline stloc first use temp"
; V12 tmp3 [V12,T06] ( 12, 7 ) int -> x6 "Inline stloc first use temp"
; V13 tmp4 [V13,T04] ( 7, 10 ) int -> x5 "Inlining Arg"
; V13 tmp4 [V13,T04] ( 7, 10 ) int -> x5 "Inlining Arg"
; V14 tmp5 [V14,T12] ( 3, 2 ) int -> x6 "Inline return value spill temp"
; V14 tmp5 [V14,T12] ( 3, 2 ) int -> x6 "Inline return value spill temp"
;* V15 tmp6 [V15 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inlining Arg"
;* V15 tmp6 [V15 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inlining Arg"
; V16 tmp7 [V16,T03] ( 3, 12 ) int -> x1 "Inline stloc first use temp"
; V16 tmp7 [V16,T03] ( 3, 12 ) int -> x1 "Inline stloc first use temp"
;* V17 tmp8 [V17 ] ( 0, 0 ) struct ( 8) zero-ref "NewObj constructor temp"
;* V17 tmp8 [V17 ] ( 0, 0 ) struct ( 8) zero-ref "NewObj constructor temp"
;* V18 tmp9 [V18 ] ( 0, 0 ) int -> zero-ref "Inlining Arg"
;* V18 tmp9 [V18 ] ( 0, 0 ) int -> zero-ref "Inlining Arg"
; V19 tmp10 [V19,T09] ( 3, 2 ) byref -> x2 single-def V02._pointer(offs=0x00) P-INDEP "field V02._pointer (fldOffset=0x0)"
; V19 tmp10 [V19,T09] ( 3, 2 ) byref -> x2 single-def V02._pointer(offs=0x00) P-INDEP "field V02._pointer (fldOffset=0x0)"
; V20 tmp11 [V20,T10] ( 2, 2 ) int -> x3 single-def V02._length(offs=0x08) P-INDEP "field V02._length (fldOffset=0x8)"
; V20 tmp11 [V20,T10] ( 2, 2 ) int -> x3 single-def V02._length(offs=0x08) P-INDEP "field V02._length (fldOffset=0x8)"
;* V21 tmp12 [V21 ] ( 0, 0 ) int -> zero-ref V10.Item1(offs=0x00) P-INDEP "field V10.Item1 (fldOffset=0x0)"
;* V21 tmp12 [V21 ] ( 0, 0 ) int -> zero-ref V10.Item1(offs=0x00) P-INDEP "field V10.Item1 (fldOffset=0x0)"
;* V22 tmp13 [V22 ] ( 0, 0 ) int -> zero-ref V10.Item2(offs=0x04) P-INDEP "field V10.Item2 (fldOffset=0x4)"
;* V22 tmp13 [V22 ] ( 0, 0 ) int -> zero-ref V10.Item2(offs=0x04) P-INDEP "field V10.Item2 (fldOffset=0x4)"
;* V23 tmp14 [V23,T14] ( 0, 0 ) byref -> zero-ref single-def V15._pointer(offs=0x00) P-INDEP "field V15._pointer (fldOffset=0x0)"
;* V23 tmp14 [V23,T14] ( 0, 0 ) byref -> zero-ref single-def V15._pointer(offs=0x00) P-INDEP "field V15._pointer (fldOffset=0x0)"
;* V24 tmp15 [V24 ] ( 0, 0 ) int -> zero-ref V15._length(offs=0x08) P-INDEP "field V15._length (fldOffset=0x8)"
;* V24 tmp15 [V24 ] ( 0, 0 ) int -> zero-ref V15._length(offs=0x08) P-INDEP "field V15._length (fldOffset=0x8)"
;* V25 tmp16 [V25 ] ( 0, 0 ) int -> zero-ref V17.Item1(offs=0x00) P-INDEP "field V17.Item1 (fldOffset=0x0)"
;* V25 tmp16 [V25 ] ( 0, 0 ) int -> zero-ref V17.Item1(offs=0x00) P-INDEP "field V17.Item1 (fldOffset=0x0)"
; V26 tmp17 [V26,T05] ( 2, 8 ) int -> x3 V17.Item2(offs=0x04) P-INDEP "field V17.Item2 (fldOffset=0x4)"
; V26 tmp17 [V26,T05] ( 2, 8 ) int -> x3 V17.Item2(offs=0x04) P-INDEP "field V17.Item2 (fldOffset=0x4)"
; V27 tmp18 [V27,T13] ( 2, 2 ) long -> x2 "Cast away GC"
; V27 tmp18 [V27,T13] ( 2, 2 ) long -> x2 "Cast away GC"
;
;
; Lcl frame size = 16
; Lcl frame size = 16


G_M40505_IG01:
G_M40505_IG01:
stp fp, lr, [sp,#-32]!
stp fp, lr, [sp,#-32]!
mov fp, sp
mov fp, sp
str xzr, [fp,#16] // [V06 loc2]
str xzr, [fp,#16] // [V06 loc2]
;; bbWeight=1 PerfScore 2.50
;; bbWeight=1 PerfScore 2.50
G_M40505_IG02:
G_M40505_IG02:
mov w5, w0
mov w5, w0
mov w6, #1
mov w6, #1
movz w7, #0xd1ffab1e
movz w7, #0xd1ffab1e
movk w7, #1 LSL #16
movk w7, #1 LSL #16
cmp w5, w7
cmp w5, w7
blo G_M40505_IG04
blo G_M40505_IG04
;; bbWeight=1 PerfScore 3.50
;; bbWeight=1 PerfScore 3.50
G_M40505_IG03:
G_M40505_IG03:
movz x5, #0xd1ffab1e
movz x5, #0xd1ffab1e
movk x5, #0xd1ffab1e LSL #16
movk x5, #0xd1ffab1e LSL #16
movk x5, #0xd1ffab1e LSL #32
movk x5, #0xd1ffab1e LSL #32
mov w6, w0
mov w6, w0
umulh x5, x6, x5
umulh x5, x6, x5
mov w6, #6
mov w6, #6
;; bbWeight=0.50 PerfScore 3.75
;; bbWeight=0.50 PerfScore 3.75
G_M40505_IG04:
G_M40505_IG04:
cmp w5, #10
cmp w5, #10
blo G_M40505_IG09
blo G_M40505_IG09
;; bbWeight=1 PerfScore 1.50
;; bbWeight=1 PerfScore 1.50
G_M40505_IG05:
G_M40505_IG05:
cmp w5, #100
cmp w5, #100
bhs G_M40505_IG06
bhs G_M40505_IG06
add w6, w6, #1
add w6, w6, #1
b G_M40505_IG09
b G_M40505_IG09
;; bbWeight=0.50 PerfScore 1.50
;; bbWeight=0.50 PerfScore 1.50
G_M40505_IG06:
G_M40505_IG06:
cmp w5, #0xd1ffab1e
cmp w5, #0xd1ffab1e
bhs G_M40505_IG07
bhs G_M40505_IG07
add w6, w6, #2
add w6, w6, #2
b G_M40505_IG09
b G_M40505_IG09
;; bbWeight=0.50 PerfScore 1.50
;; bbWeight=0.50 PerfScore 1.50
G_M40505_IG07:
G_M40505_IG07:
mov w7, #0xd1ffab1e
mov w7, #0xd1ffab1e
cmp w5, w7
cmp w5, w7
bhs G_M40505_IG08
bhs G_M40505_IG08
add w6, w6, #3
add w6, w6, #3
b G_M40505_IG09
b G_M40505_IG09
;; bbWeight=0.50 PerfScore 1.75
;; bbWeight=0.50 PerfScore 1.75
G_M40505_IG08:
G_M40505_IG08:
add w6, w6, #4
add w6, w6, #4
;; bbWeight=0.50 PerfScore 0.25
;; bbWeight=0.50 PerfScore 0.25
G_M40505_IG09:
G_M40505_IG09:
cmp w1, w6
cmp w1, w6
bge G_M40505_IG11
bge G_M40505_IG11
;; bbWeight=1 PerfScore 1.50
;; bbWeight=1 PerfScore 1.50
G_M40505_IG10:
G_M40505_IG10:
b G_M40505_IG12
b G_M40505_IG12
;; bbWeight=0.50 PerfScore 0.50
;; bbWeight=0.50 PerfScore 0.50
G_M40505_IG11:
G_M40505_IG11:
mov w6, w1
mov w6, w1
;; bbWeight=0.50 PerfScore 0.25
;; bbWeight=0.50 PerfScore 0.25
G_M40505_IG12:
G_M40505_IG12:
cmp w6, w3
cmp w6, w3
ble G_M40505_IG15
ble G_M40505_IG15
;; bbWeight=1 PerfScore 1.50
;; bbWeight=1 PerfScore 1.50
G_M40505_IG13:
G_M40505_IG13:
str wzr, [x4]
str wzr, [x4]
mov w0, #0
mov w0, #0
;; bbWeight=0.50 PerfScore 0.75
;; bbWeight=0.50 PerfScore 0.75
G_M40505_IG14:
G_M40505_IG14:
ldp fp, lr, [sp],#32
ldp fp, lr, [sp],#32
ret lr
ret lr
;; bbWeight=0.50 PerfScore 1.00
;; bbWeight=0.50 PerfScore 1.00
G_M40505_IG15:
G_M40505_IG15:
str w6, [x4]
str w6, [x4]
str x2, [fp,#16] // [V06 loc2]
str x2, [fp,#16] // [V06 loc2]
sxtw x3, w6
sxtw x3, w6
lsl x3, x3, #1
lsl x3, x3, #1
add x2, x2, x3
add x2, x2, x3
str w1, [fp,#24] // [V01 arg1]
str w1, [fp,#24] // [V01 arg1]
cmp w1, #1
cmp w1, #1
bgt G_M40505_IG18
bgt G_M40505_IG18
;; bbWeight=0.50 PerfScore 3.25
;; bbWeight=0.50 PerfScore 3.25
G_M40505_IG16:
G_M40505_IG16:
movz x1, #0xd1ffab1e
movz w1, #0xd1ffab1e
movk x1, #0xd1ffab1e LSL #16
movk w1, #0xd1ffab1e LSL #16
mov w3, w0
umull x1, w0, w1
mul x1, x3, x1
lsr x1, x1, #35
lsr x1, x1, #35
mov x3, #5
mov x3, #5
mul w3, w1, w3
mul w3, w1, w3
lsl w3, w3, #1
lsl w3, w3, #1
sub w3, w0, w3
sub w3, w0, w3
mov w0, w1
mov w0, w1
sub x2, x2, #2
sub x2, x2, #2
add w1, w3, #48
add w1, w3, #48
strh w1, [x2]
strh w1, [x2]
cbnz w0, G_M40505_IG16
cbnz w0, G_M40505_IG16
;; bbWeight=4 PerfScore 48.00
;; bbWeight=4 PerfScore 46.00
G_M40505_IG17:
G_M40505_IG17:
b G_M40505_IG19
b G_M40505_IG19
;; bbWeight=0.50 PerfScore 0.50
;; bbWeight=0.50 PerfScore 0.50
G_M40505_IG18:
G_M40505_IG18:
str w0, [fp,#28] // [V00 arg0]
str w0, [fp,#28] // [V00 arg0]
mov x0, x2
mov x0, x2
ldr w1, [fp,#28] // [V00 arg0]
ldr w1, [fp,#28] // [V00 arg0]
ldr w2, [fp,#24] // [V01 arg1]
ldr w2, [fp,#24] // [V01 arg1]
bl Number:UInt32ToDecChars(long,int,int):long
bl Number:UInt32ToDecChars(long,int,int):long
;; bbWeight=0.50 PerfScore 3.25
;; bbWeight=0.50 PerfScore 3.25
G_M40505_IG19:
G_M40505_IG19:
str xzr, [fp,#16] // [V06 loc2]
str xzr, [fp,#16] // [V06 loc2]
mov w0, #1
mov w0, #1
;; bbWeight=0.50 PerfScore 0.75
;; bbWeight=0.50 PerfScore 0.75
G_M40505_IG20:
G_M40505_IG20:
ldp fp, lr, [sp],#32
ldp fp, lr, [sp],#32
ret lr
ret lr
;; bbWeight=0.50 PerfScore 1.00
;; bbWeight=0.50 PerfScore 1.00
G_M40505_IG21:
G_M40505_IG21:
bl CORINFO_HELP_THROWDIVZERO
bl CORINFO_HELP_THROWDIVZERO
bkpt
bkpt
;; bbWeight=0 PerfScore 0.00
;; bbWeight=0 PerfScore 0.00


; Total bytes of code 300, prolog size 12, PerfScore 108.50, instruction count 75, allocated bytes for code 300 (MethodHash=d74a61c6) for method Number:TryUInt32ToDecStr(int,int,Span`1,byref):bool
; Total bytes of code 296, prolog size 12, PerfScore 106.10, instruction count 74, allocated bytes for code 296 (MethodHash=d74a61c6) for method Number:TryUInt32ToDecStr(int,int,Span`1,byref):bool
; ============================================================
; ============================================================
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