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// Design
// Design
// D flip-flop
// D flip-flop
module dff (clk, reset,
module dff (clk, reset,
d, q, q2, qb);
d, q, q2, qb);
input clk;
input clk;
input reset;
input reset;
input d;
input d;
output q, q2;
output q, q2;
output qb;
output qb;


reg q, q2;
reg q, q2;


assign qb = ~q;
assign qb = ~q;


always @(posedge clk or posedge reset)
always @(posedge clk or posedge reset)
begin
begin
if (reset) begin
if (reset) begin
// Asynchronous reset when reset goes high
// Asynchronous reset when reset goes high
q <= 1'b0;
q <= 1'b0;
end else begin
// Assign D to Q on positive clock edge
q <= d;
end
end
always @(posedge clk or posedge reset)
begin
if (reset) begin
// Asynchronous reset when reset goes high
q2 <= 1'b0;
q2 <= 1'b0;
end else begin
end else begin
// Assign D to Q on positive clock edge
// Assign D to Q on positive clock edge
q <= d;
q2 <= d;
q2 <= d;
end
end
end
end
endmodule
endmodule
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