テキスト比較

2 つのテキストファイルの違いを見つける

リアルタイムdiff

統一diff

行を折りたたむ

変更をハイライト

シンタックスハイライト

ツール

Diffchecker Desktop The most secure way to run Diffchecker. Get the Diffchecker Desktop app: your diffs never leave your computer!Get Desktop

Untitled Diff

Created 4 years agoDiff never expires

行
合計
削除

単語
合計
削除

この機能を引き続き使用するには、アップグレードしてください Diffchecker Pro 価格を見る

120 行

行
合計
追加

単語
合計
追加

この機能を引き続き使用するには、アップグレードしてください Diffchecker Pro 価格を見る

117 行

; Assembly listing for method System.Net.SocketAddress:CopyAddressSizeIntoBuffer():this

; Emitting BLENDED_CODE for generic ARM64 CPU - Unix

; optimized code

; fp based frame

; partially interruptible

; No matching PGO data

; 0 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data

; Final local variable assignments

;

; V00 this [V00,T01] ( 5, 5 ) ref -> x0 this class-hnd single-def

;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [sp+00H] "OutgoingArgSpace"

; V02 tmp1 [V02,T02] ( 3, 6 ) ref -> x2 class-hnd single-def "impAppendStmt"

; V03 tmp2 [V03,T12] ( 2, 4 ) int -> x3 "impAppendStmt"

; V03 tmp2 [V03,T10] ( 2, 4 ) int -> x3 "impAppendStmt"

; V04 tmp3 [V04,T03] ( 3, 6 ) int -> x3 "Strict ordering of exceptions for Array store"

; V05 tmp4 [V05,T13] ( 2, 4 ) int -> x4 "Strict ordering of exceptions for Array store"

; V05 tmp4 [V05,T11] ( 2, 4 ) int -> x4 "Strict ordering of exceptions for Array store"

; V06 tmp5 [V06,T09] ( 2, 4 ) ref -> x2 class-hnd single-def "impAppendStmt"

;* V06 tmp5 [V06,T18] ( 0, 0 ) ref -> zero-ref class-hnd single-def "impAppendStmt"

; V07 tmp6 [V07,T14] ( 2, 4 ) int -> x3 "impAppendStmt"

; V07 tmp6 [V07,T12] ( 2, 4 ) int -> x3 "impAppendStmt"

; V08 tmp7 [V08,T04] ( 3, 6 ) int -> x3 "Strict ordering of exceptions for Array store"

; V09 tmp8 [V09,T15] ( 2, 4 ) int -> x4 "Strict ordering of exceptions for Array store"

; V09 tmp8 [V09,T13] ( 2, 4 ) int -> x4 "Strict ordering of exceptions for Array store"

; V10 tmp9 [V10,T10] ( 2, 4 ) ref -> x2 class-hnd single-def "impAppendStmt"

;* V10 tmp9 [V10,T19] ( 0, 0 ) ref -> zero-ref class-hnd single-def "impAppendStmt"

; V11 tmp10 [V11,T16] ( 2, 4 ) int -> x3 "impAppendStmt"

; V11 tmp10 [V11,T14] ( 2, 4 ) int -> x3 "impAppendStmt"

; V12 tmp11 [V12,T05] ( 3, 6 ) int -> x3 "Strict ordering of exceptions for Array store"

; V13 tmp12 [V13,T17] ( 2, 4 ) int -> x4 "Strict ordering of exceptions for Array store"

; V13 tmp12 [V13,T15] ( 2, 4 ) int -> x4 "Strict ordering of exceptions for Array store"

; V14 tmp13 [V14,T11] ( 2, 4 ) ref -> x2 class-hnd single-def "impAppendStmt"

;* V14 tmp13 [V14,T20] ( 0, 0 ) ref -> zero-ref class-hnd single-def "impAppendStmt"

; V15 tmp14 [V15,T18] ( 2, 4 ) int -> x1 "impAppendStmt"

; V15 tmp14 [V15,T16] ( 2, 4 ) int -> x1 "impAppendStmt"

; V16 tmp15 [V16,T06] ( 3, 6 ) int -> x1 "Strict ordering of exceptions for Array store"

; V17 tmp16 [V17,T19] ( 2, 4 ) int -> x0 "Strict ordering of exceptions for Array store"

; V17 tmp16 [V17,T17] ( 2, 4 ) int -> x0 "Strict ordering of exceptions for Array store"

; V18 cse0 [V18,T00] ( 9, 9 ) ref -> x1 "CSE - aggressive"

; V18 cse0 [V18,T00] ( 6, 6 ) ref -> x1 "CSE - aggressive"

; V19 cse1 [V19,T08] ( 4, 4 ) int -> x0 "CSE - moderate"

; V19 cse1 [V19,T09] ( 4, 4 ) int -> x0 "CSE - moderate"

; V20 cse2 [V20,T07] ( 5, 5 ) int -> x5 "CSE - aggressive"

; V20 cse2 [V20,T08] ( 5, 5 ) int -> x5 "CSE - aggressive"

; V21 cse3 [V21,T07] ( 5, 5 ) byref -> x2 "CSE - aggressive"

;

; Lcl frame size = 0

G_M12190_IG01: ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG

stp fp, lr, [sp,#-16]!

mov fp, sp

;; bbWeight=1 PerfScore 1.50

G_M12190_IG02: ; gcrefRegs=0001 {x0}, byrefRegs=0000 {}, byref, isz

; gcrRegs +[x0]

ldr x1, [x0,#8]

; gcrRegs +[x1]

mov x2, x1

; gcrRegs +[x2]

ldr w3, [x1,#8]

sub w3, w3, #8

ldrb w4, [x0,#16]

ldr w5, [x2,#8]

cmp w3, w5

bhs G_M12190_IG04

add x2, x2, #16

; gcrRegs -[x2]

; byrRegs +[x2]

mov w3, w3

add x3, x3, #16

strb w4, [x2, x3]

mov x2, x1

ldr w3, [x1,#8]

sub w3, w3, #7

ldr w0, [x0,#16]

; gcrRegs -[x0]

asr w4, w0, #8

uxtb w4, w4

cmp w3, w5

bhs G_M12190_IG04

mov w3, w3

add x3, x3, #16

strb w4, [x2, x3]

mov x2, x1

ldr w3, [x1,#8]

sub w3, w3, #6

asr w4, w0, #16

uxtb w4, w4

cmp w3, w5

bhs G_M12190_IG04

mov w3, w3

add x3, x3, #16

strb w4, [x2, x3]

mov x2, x1

ldr w1, [x1,#8]

; gcrRegs -[x1]

sub w1, w1, #5

asr w0, w0, #24

uxtb w0, w0

cmp w1, w5

bhs G_M12190_IG04

mov w1, w1

add x1, x1, #16

strb w0, [x2, x1]

;; bbWeight=1 PerfScore 46.50

;; bbWeight=1 PerfScore 43.50

G_M12190_IG03: ; , epilog, nogc, extend

ldp fp, lr, [sp],#16

ret lr

;; bbWeight=1 PerfScore 2.00

G_M12190_IG04: ; gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, gcvars, byref

; gcrRegs -[x2]

; byrRegs -[x2]

bl CORINFO_HELP_RNGCHKFAIL

brk #0

;; bbWeight=0 PerfScore 0.00

; Total bytes of code 192, prolog size 8, PerfScore 69.20, instruction count 48, allocated bytes for code 192 (MethodHash=67ccd061) for method System.Net.SocketAddress:CopyAddressSizeIntoBuffer():this

; Total bytes of code 168, prolog size 8, PerfScore 63.80, instruction count 42, allocated bytes for code 168 (MethodHash=67ccd061) for method System.Net.SocketAddress:CopyAddressSizeIntoBuffer():this

; ============================================================

Unwind Info:

>> Start offset : 0x000000 (not in unwind data)

>> End offset : 0xd1ffab1e (not in unwind data)

Code Words : 1

Epilog Count : 1

E bit : 0

X bit : 0

Vers : 0

Function Length : 48 (0x00030) Actual length = 192 (0x0000c0)

Function Length : 42 (0x0002a) Actual length = 168 (0x0000a8)

---- Epilog scopes ----

---- Scope 0

Epilog Start Offset : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

Epilog Start Index : 1 (0x01)

---- Unwind codes ----

E1 set_fp; mov fp, sp

---- Epilog start at index 1 ----

81 save_fplr_x #1 (0x01); stp fp, lr, [sp, #-16]!

E4 end

保存された差分

原文

ファイルを開く

; Assembly listing for method System.Net.SocketAddress:CopyAddressSizeIntoBuffer():this
; Emitting BLENDED_CODE for generic ARM64 CPU - Unix
; optimized code
; fp based frame
; partially interruptible
; No matching PGO data
; 0 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data
; Final local variable assignments
;
;  V00 this         [V00,T01] (  5,  5   )     ref  ->   x0         this class-hnd single-def
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+00H]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T02] (  3,  6   )     ref  ->   x2         class-hnd single-def "impAppendStmt"
;  V03 tmp2         [V03,T12] (  2,  4   )     int  ->   x3         "impAppendStmt"
;  V04 tmp3         [V04,T03] (  3,  6   )     int  ->   x3         "Strict ordering of exceptions for Array store"
;  V05 tmp4         [V05,T13] (  2,  4   )     int  ->   x4         "Strict ordering of exceptions for Array store"
;  V06 tmp5         [V06,T09] (  2,  4   )     ref  ->   x2         class-hnd single-def "impAppendStmt"
;  V07 tmp6         [V07,T14] (  2,  4   )     int  ->   x3         "impAppendStmt"
;  V08 tmp7         [V08,T04] (  3,  6   )     int  ->   x3         "Strict ordering of exceptions for Array store"
;  V09 tmp8         [V09,T15] (  2,  4   )     int  ->   x4         "Strict ordering of exceptions for Array store"
;  V10 tmp9         [V10,T10] (  2,  4   )     ref  ->   x2         class-hnd single-def "impAppendStmt"
;  V11 tmp10        [V11,T16] (  2,  4   )     int  ->   x3         "impAppendStmt"
;  V12 tmp11        [V12,T05] (  3,  6   )     int  ->   x3         "Strict ordering of exceptions for Array store"
;  V13 tmp12        [V13,T17] (  2,  4   )     int  ->   x4         "Strict ordering of exceptions for Array store"
;  V14 tmp13        [V14,T11] (  2,  4   )     ref  ->   x2         class-hnd single-def "impAppendStmt"
;  V15 tmp14        [V15,T18] (  2,  4   )     int  ->   x1         "impAppendStmt"
;  V16 tmp15        [V16,T06] (  3,  6   )     int  ->   x1         "Strict ordering of exceptions for Array store"
;  V17 tmp16        [V17,T19] (  2,  4   )     int  ->   x0         "Strict ordering of exceptions for Array store"
;  V18 cse0         [V18,T00] (  9,  9   )     ref  ->   x1         "CSE - aggressive"
;  V19 cse1         [V19,T08] (  4,  4   )     int  ->   x0         "CSE - moderate"
;  V20 cse2         [V20,T07] (  5,  5   )     int  ->   x5         "CSE - aggressive"
;
; Lcl frame size = 0

G_M12190_IG01:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
            stp     fp, lr, [sp,#-16]!
            mov     fp, sp
						;; bbWeight=1    PerfScore 1.50
G_M12190_IG02:        ; gcrefRegs=0001 {x0}, byrefRegs=0000 {}, byref, isz
            ; gcrRegs +[x0]
            ldr     x1, [x0,#8]
            ; gcrRegs +[x1]
            mov     x2, x1
            ; gcrRegs +[x2]
            ldr     w3, [x1,#8]
            sub     w3, w3, #8
            ldrb    w4, [x0,#16]
            ldr     w5, [x2,#8]
            cmp     w3, w5
            bhs     G_M12190_IG04
            mov     w3, w3
            add     x3, x3, #16
            strb    w4, [x2, x3]
            mov     x2, x1
            ldr     w3, [x1,#8]
            sub     w3, w3, #7
            ldr     w0, [x0,#16]
            ; gcrRegs -[x0]
            asr     w4, w0, #8
            uxtb    w4, w4
            cmp     w3, w5
            bhs     G_M12190_IG04
            mov     w3, w3
            add     x3, x3, #16
            strb    w4, [x2, x3]
            mov     x2, x1
            ldr     w3, [x1,#8]
            sub     w3, w3, #6
            asr     w4, w0, #16
            uxtb    w4, w4
            cmp     w3, w5
            bhs     G_M12190_IG04
            mov     w3, w3
            add     x3, x3, #16
            strb    w4, [x2, x3]
            mov     x2, x1
            ldr     w1, [x1,#8]
            ; gcrRegs -[x1]
            sub     w1, w1, #5
            asr     w0, w0, #24
            uxtb    w0, w0
            cmp     w1, w5
            bhs     G_M12190_IG04
            mov     w1, w1
            add     x1, x1, #16
            strb    w0, [x2, x1]
						;; bbWeight=1    PerfScore 46.50
G_M12190_IG03:        ; , epilog, nogc, extend
            ldp     fp, lr, [sp],#16
            ret     lr
						;; bbWeight=1    PerfScore 2.00
G_M12190_IG04:        ; gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, gcvars, byref
            ; gcrRegs -[x2]
            bl      CORINFO_HELP_RNGCHKFAIL
            brk     #0
						;; bbWeight=0    PerfScore 0.00

Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0xd1ffab1e (not in unwind data)
  Code Words        : 1
  Epilog Count      : 1
  E bit             : 0
  X bit             : 0
  Vers              : 0
  Function Length   : 48 (0x00030) Actual length = 192 (0x0000c0)
  ---- Epilog scopes ----
  ---- Scope 0
  Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)
  Epilog Start Index         : 1 (0x01)
  ---- Unwind codes ----
    E1          set_fp; mov fp, sp
    ---- Epilog start at index 1 ----
    81          save_fplr_x #1 (0x01); stp fp, lr, [sp, #-16]!
    E4          end
    E4          end

変更されたテキスト

ファイルを開く

; Assembly listing for method System.Net.SocketAddress:CopyAddressSizeIntoBuffer():this
; Emitting BLENDED_CODE for generic ARM64 CPU - Unix
; optimized code
; fp based frame
; partially interruptible
; No matching PGO data
; 0 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data
; Final local variable assignments
;
;  V00 this         [V00,T01] (  5,  5   )     ref  ->   x0         this class-hnd single-def
;# V01 OutArgs      [V01    ] (  1,  1   )  lclBlk ( 0) [sp+00H]   "OutgoingArgSpace"
;  V02 tmp1         [V02,T02] (  3,  6   )     ref  ->   x2         class-hnd single-def "impAppendStmt"
;  V03 tmp2         [V03,T10] (  2,  4   )     int  ->   x3         "impAppendStmt"
;  V04 tmp3         [V04,T03] (  3,  6   )     int  ->   x3         "Strict ordering of exceptions for Array store"
;  V05 tmp4         [V05,T11] (  2,  4   )     int  ->   x4         "Strict ordering of exceptions for Array store"
;* V06 tmp5         [V06,T18] (  0,  0   )     ref  ->  zero-ref    class-hnd single-def "impAppendStmt"
;  V07 tmp6         [V07,T12] (  2,  4   )     int  ->   x3         "impAppendStmt"
;  V08 tmp7         [V08,T04] (  3,  6   )     int  ->   x3         "Strict ordering of exceptions for Array store"
;  V09 tmp8         [V09,T13] (  2,  4   )     int  ->   x4         "Strict ordering of exceptions for Array store"
;* V10 tmp9         [V10,T19] (  0,  0   )     ref  ->  zero-ref    class-hnd single-def "impAppendStmt"
;  V11 tmp10        [V11,T14] (  2,  4   )     int  ->   x3         "impAppendStmt"
;  V12 tmp11        [V12,T05] (  3,  6   )     int  ->   x3         "Strict ordering of exceptions for Array store"
;  V13 tmp12        [V13,T15] (  2,  4   )     int  ->   x4         "Strict ordering of exceptions for Array store"
;* V14 tmp13        [V14,T20] (  0,  0   )     ref  ->  zero-ref    class-hnd single-def "impAppendStmt"
;  V15 tmp14        [V15,T16] (  2,  4   )     int  ->   x1         "impAppendStmt"
;  V16 tmp15        [V16,T06] (  3,  6   )     int  ->   x1         "Strict ordering of exceptions for Array store"
;  V17 tmp16        [V17,T17] (  2,  4   )     int  ->   x0         "Strict ordering of exceptions for Array store"
;  V18 cse0         [V18,T00] (  6,  6   )     ref  ->   x1         "CSE - aggressive"
;  V19 cse1         [V19,T09] (  4,  4   )     int  ->   x0         "CSE - moderate"
;  V20 cse2         [V20,T08] (  5,  5   )     int  ->   x5         "CSE - aggressive"
;  V21 cse3         [V21,T07] (  5,  5   )   byref  ->   x2         "CSE - aggressive"
;
; Lcl frame size = 0

G_M12190_IG01:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
            stp     fp, lr, [sp,#-16]!
            mov     fp, sp
						;; bbWeight=1    PerfScore 1.50
G_M12190_IG02:        ; gcrefRegs=0001 {x0}, byrefRegs=0000 {}, byref, isz
            ; gcrRegs +[x0]
            ldr     x1, [x0,#8]
            ; gcrRegs +[x1]
            mov     x2, x1
            ; gcrRegs +[x2]
            ldr     w3, [x1,#8]
            sub     w3, w3, #8
            ldrb    w4, [x0,#16]
            ldr     w5, [x2,#8]
            cmp     w3, w5
            bhs     G_M12190_IG04
            add     x2, x2, #16
            ; gcrRegs -[x2]
            ; byrRegs +[x2]
            mov     w3, w3
            strb    w4, [x2, x3]
            ldr     w3, [x1,#8]
            sub     w3, w3, #7
            ldr     w0, [x0,#16]
            ; gcrRegs -[x0]
            asr     w4, w0, #8
            uxtb    w4, w4
            cmp     w3, w5
            bhs     G_M12190_IG04
            mov     w3, w3
            strb    w4, [x2, x3]
            ldr     w3, [x1,#8]
            sub     w3, w3, #6
            asr     w4, w0, #16
            uxtb    w4, w4
            cmp     w3, w5
            bhs     G_M12190_IG04
            mov     w3, w3
            strb    w4, [x2, x3]
            ldr     w1, [x1,#8]
            ; gcrRegs -[x1]
            sub     w1, w1, #5
            asr     w0, w0, #24
            uxtb    w0, w0
            cmp     w1, w5
            bhs     G_M12190_IG04
            mov     w1, w1
            strb    w0, [x2, x1]
						;; bbWeight=1    PerfScore 43.50
G_M12190_IG03:        ; , epilog, nogc, extend
            ldp     fp, lr, [sp],#16
            ret     lr
						;; bbWeight=1    PerfScore 2.00
G_M12190_IG04:        ; gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, gcvars, byref
            ; byrRegs -[x2]
            bl      CORINFO_HELP_RNGCHKFAIL
            brk     #0
						;; bbWeight=0    PerfScore 0.00

Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0xd1ffab1e (not in unwind data)
  Code Words        : 1
  Epilog Count      : 1
  E bit             : 0
  X bit             : 0
  Vers              : 0
  Function Length   : 42 (0x0002a) Actual length = 168 (0x0000a8)
  ---- Epilog scopes ----
  ---- Scope 0
  Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)
  Epilog Start Index         : 1 (0x01)
  ---- Unwind codes ----
    E1          set_fp; mov fp, sp
    ---- Epilog start at index 1 ----
    81          save_fplr_x #1 (0x01); stp fp, lr, [sp, #-16]!
    E4          end
    E4          end