ARM64
建立於 差異永不過期
; ...ToArray()
; ...ToArray()
G_M000_IG01: ;; offset=0000H
G_M000_IG01: ;; offset=0000H
stp fp, lr, [sp, #-0x20]!
stp fp, lr, [sp, #-0x40]!
str x19, [sp, #0x18]
str x19, [sp, #0x38]
mov fp, sp
mov fp, sp
G_M000_IG02: ;; offset=000CH
G_M000_IG02: ;; offset=000CH
ldp w19, w1, [x0, #0x08]
ldp w19, w1, [x0, #0x08]
sub w1, w1, w19
sub w1, w1, w19
sxtw x1, w1
sxtw x1, w1
movz x0, #0x34E0
movz x0, #0x34E0
movk x0, #0x55E LSL #16
movk x0, #0x7AE LSL #16
movk x0, #1 LSL #32
movk x0, #1 LSL #32
bl CORINFO_HELP_NEWARR_1_VC
bl CORINFO_HELP_NEWARR_1_VC
add x1, x0, #16
add x1, x0, #16
ldr w2, [x0, #0x08]
ldr w2, [x0, #0x08]
cmp w2, #8
blt G_M000_IG06
G_M000_IG03: ;; offset=0038H
dup v16.4s, w19
ldr q17, [@RWD00]
add v17.4s, v16.4s, v17.4s
ldr q18, [@RWD16]
add v16.4s, v16.4s, v18.4s
ldr q18, [@RWD32]
mov v19.16b, v18.16b
align [4 bytes for IG04]
align [4 bytes]
align [4 bytes]
align [0 bytes]
G_M000_IG04: ;; offset=0060H
stp q17, q16, [x1]
add v17.4s, v17.4s, v19.4s
add v16.4s, v16.4s, v18.4s
add x1, x1, #32
sub w2, w2, #8
cmp w2, #8
bge G_M000_IG04
G_M000_IG05: ;; offset=007CH
str q17, [fp, #0x18] //
str q16, [fp, #0x28] //
ldr w19, [fp, #0x18] //
G_M000_IG06: ;; offset=0088H
mov w3, wzr
mov w3, wzr
cmp w2, #0
cmp w2, #0
ble G_M000_IG04
ble G_M000_IG08
align [4 bytes for IG03]
align [4 bytes for IG07]
align [0 bytes]
align [4 bytes]
align [0 bytes]
align [4 bytes]
align [0 bytes]
align [0 bytes]
G_M000_IG03: ;; offset=0040H
G_M000_IG07: ;; offset=00A0H
add w4, w19, #1
str w19, [x1, w3, UXTW #2]
str w19, [x1, w3, UXTW #2]
add w3, w3, #1
add w3, w3, #1
add w19, w19, #1
cmp w3, w2
cmp w3, w2
blt G_M000_IG03
mov w19, w4
blt G_M000_IG07
G_M000_IG04: ;; offset=0054H
G_M000_IG08: ;; offset=00B8H
ldr x19, [sp, #0x18]
ldr x19, [sp, #0x38]
ldp fp, lr, [sp], #0x20
ldp fp, lr, [sp], #0x40
ret lr
ret lr
; Total bytes of code 96
RWD00 dq 0000000100000000h, 0000000300000002h
RWD16 dq 0000000500000004h, 0000000700000006h
RWD32 dq 0000000800000008h, 0000000800000008h
; Total bytes of code 196