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; Assembly listing for method JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorIndices__Sve_GatherVectorSByteSignExtend_Indices_ulong_long:RunBasicScenario_FalseMask():this (Tier0-MinOpts)

; Emitting BLENDED_CODE for generic ARM64 - Windows

; Tier-0 switched MinOpts code

; fp based frame

; partially interruptible

; method switched to min-opts

; Final local variable assignments

;

; V00 this [V00 ] ( 1, 1 ) ref -> [fp+0x58] do-not-enreg[] this class-hnd <JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorIndices__Sve_GatherVectorSByteSignExtend_Indices_ulong_long>

; V00 this [V00 ] ( 1, 1 ) ref -> [fp+0x68] do-not-enreg[] this class-hnd <JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorIndices__Sve_GatherVectorSByteSignExtend_Indices_ulong_long>

; V01 loc0 [V01 ] ( 1, 1 ) simd16 -> [fp+0x40] HFA(simd16) do-not-enreg[S] must-init <System.Numerics.Vector`1[ulong]>

; V01 loc0 [V01 ] ( 1, 1 ) simd16 -> [fp+0x50] HFA(simd16) do-not-enreg[S] must-init <System.Numerics.Vector`1[ulong]>

;# V02 OutArgs [V02 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"

; V03 tmp1 [V03 ] ( 1, 1 ) long -> [fp+0x38] do-not-enreg[] "non-inline candidate call"

; V03 tmp1 [V03 ] ( 1, 1 ) long -> [fp+0x48] do-not-enreg[] "non-inline candidate call"

; V04 tmp2 [V04 ] ( 1, 1 ) long -> [fp+0x30] do-not-enreg[] "non-inline candidate call"

; V04 tmp2 [V04 ] ( 1, 1 ) long -> [fp+0x40] do-not-enreg[] "non-inline candidate call"

; V05 tmp3 [V05 ] ( 1, 1 ) long -> [fp+0x28] do-not-enreg[] "non-inline candidate call"

; V05 tmp3 [V05 ] ( 1, 1 ) long -> [fp+0x38] do-not-enreg[] "non-inline candidate call"

; V06 tmp4 [V06 ] ( 1, 1 ) long -> [fp+0x20] do-not-enreg[] "non-inline candidate call"

; V06 tmp4 [V06 ] ( 1, 1 ) long -> [fp+0x30] do-not-enreg[] "non-inline candidate call"

; V07 tmp5 [V07 ] ( 1, 1 ) long -> [fp+0x18] do-not-enreg[] "argument with side effect"

; V07 tmp5 [V07 ] ( 1, 1 ) long -> [fp+0x28] do-not-enreg[] "argument with side effect"

; TEMP_01 long -> [fp+0x10]

; TEMP_02 mask -> [fp+0x20]

; TEMP_01 long -> [fp+0x18]

;

; Lcl frame size = 80

; Lcl frame size = 96

G_M38347_IG01: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG

stp fp, lr, [sp, #-0x60]!

stp fp, lr, [sp, #-0x70]!

mov fp, sp

str xzr, [fp, #0x40] // [V01 loc0]

str xzr, [fp, #0x50] // [V01 loc0]

str xzr, [fp, #0x48] // [V01 loc0+0x08]

str xzr, [fp, #0x58] // [V01 loc0+0x08]

str x0, [fp, #0x58] // [V00 this]

str x0, [fp, #0x68] // [V00 this]

;; size=20 bbWeight=1 PerfScore 4.50

G_M38347_IG02: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref

movz x0, #0xD1FFAB1E

movk x0, #0xD1FFAB1E LSL #16

movk x0, #0xD1FFAB1E LSL #32

movz x1, #0xD1FFAB1E // code for <unknown method>

movk x1, #0xD1FFAB1E LSL #16

movk x1, #0xD1FFAB1E LSL #32

ldr x1, [x1]

blr x1

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

; gcrRegs +[x0]

ldrsb wzr, [x0]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

add x0, x0, #88

; gcrRegs -[x0]

; byrRegs +[x0]

movz x1, #0xD1FFAB1E // code for <unknown method>

movk x1, #0xD1FFAB1E LSL #16

movk x1, #0xD1FFAB1E LSL #32

ldr x1, [x1]

blr x1

; byrRegs -[x0]

str x0, [fp, #0x38] // [V03 tmp1]

str x0, [fp, #0x48] // [V03 tmp1]

pfalse p0.b

mov z16.d, p0/z, #1

ptrue p0.d

cmpne p0.d, p0/z, z16.d, #0

ldr x0, [fp, #0x38] // [V03 tmp1]

add xip1, fp, #32

str x0, [fp, #0x10] // [TEMP_01]

str p0, [xip1]

ldr x1, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x48] // [V03 tmp1]

str x0, [fp, #0x18] // [TEMP_01]

ldr x1, [fp, #0x68] // [V00 this]

; gcrRegs +[x1]

ldrsb wzr, [x1]

ldr x1, [fp, #0x58] // [V00 this]

ldr x1, [fp, #0x68] // [V00 this]

add x0, x1, #88

; byrRegs +[x0]

movz x1, #0xD1FFAB1E // code for <unknown method>

; gcrRegs -[x1]

movk x1, #0xD1FFAB1E LSL #16

movk x1, #0xD1FFAB1E LSL #32

ldr x1, [x1]

blr x1

; byrRegs -[x0]

ldr q16, [x0]

ldr x0, [fp, #0x10] // [TEMP_01]

add xip1, fp, #32

ldr p0, [xip1]

ldr x0, [fp, #0x18] // [TEMP_01]

ld1sb { z16.d }, p0/z, [x0, z16.d]

str q16, [fp, #0x40] // [V01 loc0]

str q16, [fp, #0x50] // [V01 loc0]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

; gcrRegs +[x0]

ldrsb wzr, [x0]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

add x0, x0, #88

; gcrRegs -[x0]

; byrRegs +[x0]

movz x1, #0xD1FFAB1E // code for <unknown method>

movk x1, #0xD1FFAB1E LSL #16

movk x1, #0xD1FFAB1E LSL #32

ldr x1, [x1]

blr x1

; byrRegs -[x0]

ldr q16, [fp, #0x40] // [V01 loc0]

ldr q16, [fp, #0x50] // [V01 loc0]

str q16, [x0]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

; gcrRegs +[x0]

ldrsb wzr, [x0]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

add x0, x0, #88

; gcrRegs -[x0]

; byrRegs +[x0]

movz x1, #0xD1FFAB1E // code for <unknown method>

movk x1, #0xD1FFAB1E LSL #16

movk x1, #0xD1FFAB1E LSL #32

ldr x1, [x1]

blr x1

; byrRegs -[x0]

str x0, [fp, #0x30] // [V04 tmp2]

str x0, [fp, #0x40] // [V04 tmp2]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

; gcrRegs +[x0]

ldrsb wzr, [x0]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

add x0, x0, #88

; gcrRegs -[x0]

; byrRegs +[x0]

movz x1, #0xD1FFAB1E // code for <unknown method>

movk x1, #0xD1FFAB1E LSL #16

movk x1, #0xD1FFAB1E LSL #32

ldr x1, [x1]

blr x1

; byrRegs -[x0]

str x0, [fp, #0x28] // [V05 tmp3]

str x0, [fp, #0x38] // [V05 tmp3]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

; gcrRegs +[x0]

ldrsb wzr, [x0]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

add x0, x0, #88

; gcrRegs -[x0]

; byrRegs +[x0]

movz x1, #0xD1FFAB1E // code for <unknown method>

movk x1, #0xD1FFAB1E LSL #16

movk x1, #0xD1FFAB1E LSL #32

ldr x1, [x1]

blr x1

; byrRegs -[x0]

str x0, [fp, #0x20] // [V06 tmp4]

str x0, [fp, #0x30] // [V06 tmp4]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

; gcrRegs +[x0]

ldrsb wzr, [x0]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

add x0, x0, #88

; gcrRegs -[x0]

; byrRegs +[x0]

movz x1, #0xD1FFAB1E // code for <unknown method>

movk x1, #0xD1FFAB1E LSL #16

movk x1, #0xD1FFAB1E LSL #32

ldr x1, [x1]

blr x1

; byrRegs -[x0]

str x0, [fp, #0x18] // [V07 tmp5]

str x0, [fp, #0x28] // [V07 tmp5]

ldr x4, [fp, #0x18] // [V07 tmp5]

ldr x4, [fp, #0x28] // [V07 tmp5]

ldr x1, [fp, #0x30] // [V04 tmp2]

ldr x1, [fp, #0x40] // [V04 tmp2]

ldr x2, [fp, #0x28] // [V05 tmp3]

ldr x2, [fp, #0x38] // [V05 tmp3]

ldr x3, [fp, #0x20] // [V06 tmp4]

ldr x3, [fp, #0x30] // [V06 tmp4]

ldr x0, [fp, #0x58] // [V00 this]

ldr x0, [fp, #0x68] // [V00 this]

; gcrRegs +[x0]

movz x5, #0xD1FFAB1E

movk x5, #0xD1FFAB1E LSL #16

movk x5, #0xD1FFAB1E LSL #32

movz x6, #0xD1FFAB1E // code for <unknown method>

movk x6, #0xD1FFAB1E LSL #16

movk x6, #0xD1FFAB1E LSL #32

ldr x6, [x6]

blr x6

; gcrRegs -[x0]

;; size=404 bbWeight=1 PerfScore 149.00

;; size=420 bbWeight=1 PerfScore 157.00

G_M38347_IG03: ; bbWeight=1, epilog, nogc, extend

ldp fp, lr, [sp], #0x60

ldp fp, lr, [sp], #0x70

ret lr

;; size=8 bbWeight=1 PerfScore 2.00

; Total bytes of code 432, prolog size 16, PerfScore 155.50, instruction count 108, allocated bytes for code 432 (MethodHash=2fef6a34) for method JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorIndices__Sve_GatherVectorSByteSignExtend_Indices_ulong_long:RunBasicScenario_FalseMask():this (Tier0-MinOpts)

; Total bytes of code 448, prolog size 16, PerfScore 163.50, instruction count 112, allocated bytes for code 448 (MethodHash=2fef6a34) for method JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorIndices__Sve_GatherVectorSByteSignExtend_Indices_ulong_long:RunBasicScenario_FalseMask():this (Tier0-MinOpts)

; ============================================================

Unwind Info:

>> Start offset : 0x000000 (not in unwind data)

>> End offset : 0xd1ffab1e (not in unwind data)

Code Words : 1

Epilog Count : 1

E bit : 0

X bit : 0

Vers : 0

Function Length : 108 (0x0006c) Actual length = 432 (0x0001b0)

Function Length : 112 (0x00070) Actual length = 448 (0x0001c0)

---- Epilog scopes ----

---- Scope 0

Epilog Start Offset : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

Epilog Start Index : 1 (0x01)

---- Unwind codes ----

E1 set_fp; mov fp, sp

---- Epilog start at index 1 ----

8B save_fplr_x #11 (0x0B); stp fp, lr, [sp, #-96]!

8D save_fplr_x #13 (0x0D); stp fp, lr, [sp, #-112]!

E4 end

已保存差異

原始文本

開啟檔案

; Assembly listing for method JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorIndices__Sve_GatherVectorSByteSignExtend_Indices_ulong_long:RunBasicScenario_FalseMask():this (Tier0-MinOpts)
; Emitting BLENDED_CODE for generic ARM64 - Windows
; Tier-0 switched MinOpts code
; fp based frame
; partially interruptible
; method switched to min-opts
; Final local variable assignments
;
;  V00 this         [V00    ] (  1,  1   )     ref  ->  [fp+0x58]  do-not-enreg[] this class-hnd <JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorIndices__Sve_GatherVectorSByteSignExtend_Indices_ulong_long>
;  V01 loc0         [V01    ] (  1,  1   )  simd16  ->  [fp+0x40]  HFA(simd16)  do-not-enreg[S] must-init <System.Numerics.Vector`1[ulong]>
;# V02 OutArgs      [V02    ] (  1,  1   )  struct ( 0) [sp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V03 tmp1         [V03    ] (  1,  1   )    long  ->  [fp+0x38]  do-not-enreg[] "non-inline candidate call"
;  V04 tmp2         [V04    ] (  1,  1   )    long  ->  [fp+0x30]  do-not-enreg[] "non-inline candidate call"
;  V05 tmp3         [V05    ] (  1,  1   )    long  ->  [fp+0x28]  do-not-enreg[] "non-inline candidate call"
;  V06 tmp4         [V06    ] (  1,  1   )    long  ->  [fp+0x20]  do-not-enreg[] "non-inline candidate call"
;  V07 tmp5         [V07    ] (  1,  1   )    long  ->  [fp+0x18]  do-not-enreg[] "argument with side effect"
;  TEMP_01                                    long  ->  [fp+0x10]
;
; Lcl frame size = 80

G_M38347_IG01:        ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
            stp     fp, lr, [sp, #-0x60]!
            mov     fp, sp
            str     xzr, [fp, #0x40]	// [V01 loc0]
            str     xzr, [fp, #0x48]	// [V01 loc0+0x08]
            str     x0, [fp, #0x58]	// [V00 this]
						;; size=20 bbWeight=1 PerfScore 4.50
G_M38347_IG02:        ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
            movz    x0, #0xD1FFAB1E
            movk    x0, #0xD1FFAB1E LSL #16
            movk    x0, #0xD1FFAB1E LSL #32
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ldr     x0, [fp, #0x58]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x58]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            str     x0, [fp, #0x38]	// [V03 tmp1]
            pfalse  p0.b
            mov     z16.d, p0/z, #1
            ptrue   p0.d
            cmpne   p0.d, p0/z, z16.d, #0
            ldr     x0, [fp, #0x38]	// [V03 tmp1]
            str     x0, [fp, #0x10]	// [TEMP_01]
            ldr     x1, [fp, #0x58]	// [V00 this]
            ; gcrRegs +[x1]
            ldrsb   wzr, [x1]
            ldr     x1, [fp, #0x58]	// [V00 this]
            add     x0, x1, #88
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            ; gcrRegs -[x1]
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            ldr     q16, [x0]
            ldr     x0, [fp, #0x10]	// [TEMP_01]
            ld1sb   { z16.d }, p0/z, [x0, z16.d]
            str     q16, [fp, #0x40]	// [V01 loc0]
            ldr     x0, [fp, #0x58]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x58]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            ldr     q16, [fp, #0x40]	// [V01 loc0]
            str     q16, [x0]
            ldr     x0, [fp, #0x58]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x58]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            str     x0, [fp, #0x30]	// [V04 tmp2]
            ldr     x0, [fp, #0x58]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x58]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            str     x0, [fp, #0x28]	// [V05 tmp3]
            ldr     x0, [fp, #0x58]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x58]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            str     x0, [fp, #0x20]	// [V06 tmp4]
            ldr     x0, [fp, #0x58]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x58]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            str     x0, [fp, #0x18]	// [V07 tmp5]
            ldr     x4, [fp, #0x18]	// [V07 tmp5]
            ldr     x1, [fp, #0x30]	// [V04 tmp2]
            ldr     x2, [fp, #0x28]	// [V05 tmp3]
            ldr     x3, [fp, #0x20]	// [V06 tmp4]
            ldr     x0, [fp, #0x58]	// [V00 this]
            ; gcrRegs +[x0]
            movz    x5, #0xD1FFAB1E
            movk    x5, #0xD1FFAB1E LSL #16
            movk    x5, #0xD1FFAB1E LSL #32
            movz    x6, #0xD1FFAB1E      // code for <unknown method>
            movk    x6, #0xD1FFAB1E LSL #16
            movk    x6, #0xD1FFAB1E LSL #32
            ldr     x6, [x6]
            blr     x6
            ; gcrRegs -[x0]
						;; size=404 bbWeight=1 PerfScore 149.00
G_M38347_IG03:        ; bbWeight=1, epilog, nogc, extend
            ldp     fp, lr, [sp], #0x60
            ret     lr
						;; size=8 bbWeight=1 PerfScore 2.00

Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0xd1ffab1e (not in unwind data)
  Code Words        : 1
  Epilog Count      : 1
  E bit             : 0
  X bit             : 0
  Vers              : 0
  Function Length   : 108 (0x0006c) Actual length = 432 (0x0001b0)
  ---- Epilog scopes ----
  ---- Scope 0
  Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)
  Epilog Start Index         : 1 (0x01)
  ---- Unwind codes ----
    E1          set_fp; mov fp, sp
    ---- Epilog start at index 1 ----
    8B          save_fplr_x #11 (0x0B); stp fp, lr, [sp, #-96]!
    E4          end
    E4          end

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; Assembly listing for method JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorIndices__Sve_GatherVectorSByteSignExtend_Indices_ulong_long:RunBasicScenario_FalseMask():this (Tier0-MinOpts)
; Emitting BLENDED_CODE for generic ARM64 - Windows
; Tier-0 switched MinOpts code
; fp based frame
; partially interruptible
; method switched to min-opts
; Final local variable assignments
;
;  V00 this         [V00    ] (  1,  1   )     ref  ->  [fp+0x68]  do-not-enreg[] this class-hnd <JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorIndices__Sve_GatherVectorSByteSignExtend_Indices_ulong_long>
;  V01 loc0         [V01    ] (  1,  1   )  simd16  ->  [fp+0x50]  HFA(simd16)  do-not-enreg[S] must-init <System.Numerics.Vector`1[ulong]>
;# V02 OutArgs      [V02    ] (  1,  1   )  struct ( 0) [sp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V03 tmp1         [V03    ] (  1,  1   )    long  ->  [fp+0x48]  do-not-enreg[] "non-inline candidate call"
;  V04 tmp2         [V04    ] (  1,  1   )    long  ->  [fp+0x40]  do-not-enreg[] "non-inline candidate call"
;  V05 tmp3         [V05    ] (  1,  1   )    long  ->  [fp+0x38]  do-not-enreg[] "non-inline candidate call"
;  V06 tmp4         [V06    ] (  1,  1   )    long  ->  [fp+0x30]  do-not-enreg[] "non-inline candidate call"
;  V07 tmp5         [V07    ] (  1,  1   )    long  ->  [fp+0x28]  do-not-enreg[] "argument with side effect"
;  TEMP_02                                    mask  ->  [fp+0x20]
;  TEMP_01                                    long  ->  [fp+0x18]
;
; Lcl frame size = 96

G_M38347_IG01:        ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
            stp     fp, lr, [sp, #-0x70]!
            mov     fp, sp
            str     xzr, [fp, #0x50]	// [V01 loc0]
            str     xzr, [fp, #0x58]	// [V01 loc0+0x08]
            str     x0, [fp, #0x68]	// [V00 this]
						;; size=20 bbWeight=1 PerfScore 4.50
G_M38347_IG02:        ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
            movz    x0, #0xD1FFAB1E
            movk    x0, #0xD1FFAB1E LSL #16
            movk    x0, #0xD1FFAB1E LSL #32
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ldr     x0, [fp, #0x68]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x68]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            str     x0, [fp, #0x48]	// [V03 tmp1]
            pfalse  p0.b
            mov     z16.d, p0/z, #1
            ptrue   p0.d
            cmpne   p0.d, p0/z, z16.d, #0
            add     xip1, fp, #32
            str     p0, [xip1]
            ldr     x0, [fp, #0x48]	// [V03 tmp1]
            str     x0, [fp, #0x18]	// [TEMP_01]
            ldr     x1, [fp, #0x68]	// [V00 this]
            ; gcrRegs +[x1]
            ldrsb   wzr, [x1]
            ldr     x1, [fp, #0x68]	// [V00 this]
            add     x0, x1, #88
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            ; gcrRegs -[x1]
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            ldr     q16, [x0]
            add     xip1, fp, #32
            ldr     p0, [xip1]
            ldr     x0, [fp, #0x18]	// [TEMP_01]
            ld1sb   { z16.d }, p0/z, [x0, z16.d]
            str     q16, [fp, #0x50]	// [V01 loc0]
            ldr     x0, [fp, #0x68]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x68]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            ldr     q16, [fp, #0x50]	// [V01 loc0]
            str     q16, [x0]
            ldr     x0, [fp, #0x68]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x68]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            str     x0, [fp, #0x40]	// [V04 tmp2]
            ldr     x0, [fp, #0x68]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x68]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            str     x0, [fp, #0x38]	// [V05 tmp3]
            ldr     x0, [fp, #0x68]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x68]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            str     x0, [fp, #0x30]	// [V06 tmp4]
            ldr     x0, [fp, #0x68]	// [V00 this]
            ; gcrRegs +[x0]
            ldrsb   wzr, [x0]
            ldr     x0, [fp, #0x68]	// [V00 this]
            add     x0, x0, #88
            ; gcrRegs -[x0]
            ; byrRegs +[x0]
            movz    x1, #0xD1FFAB1E      // code for <unknown method>
            movk    x1, #0xD1FFAB1E LSL #16
            movk    x1, #0xD1FFAB1E LSL #32
            ldr     x1, [x1]
            blr     x1
            ; byrRegs -[x0]
            str     x0, [fp, #0x28]	// [V07 tmp5]
            ldr     x4, [fp, #0x28]	// [V07 tmp5]
            ldr     x1, [fp, #0x40]	// [V04 tmp2]
            ldr     x2, [fp, #0x38]	// [V05 tmp3]
            ldr     x3, [fp, #0x30]	// [V06 tmp4]
            ldr     x0, [fp, #0x68]	// [V00 this]
            ; gcrRegs +[x0]
            movz    x5, #0xD1FFAB1E
            movk    x5, #0xD1FFAB1E LSL #16
            movk    x5, #0xD1FFAB1E LSL #32
            movz    x6, #0xD1FFAB1E      // code for <unknown method>
            movk    x6, #0xD1FFAB1E LSL #16
            movk    x6, #0xD1FFAB1E LSL #32
            ldr     x6, [x6]
            blr     x6
            ; gcrRegs -[x0]
						;; size=420 bbWeight=1 PerfScore 157.00
G_M38347_IG03:        ; bbWeight=1, epilog, nogc, extend
            ldp     fp, lr, [sp], #0x70
            ret     lr
						;; size=8 bbWeight=1 PerfScore 2.00

Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0xd1ffab1e (not in unwind data)
  Code Words        : 1
  Epilog Count      : 1
  E bit             : 0
  X bit             : 0
  Vers              : 0
  Function Length   : 112 (0x00070) Actual length = 448 (0x0001c0)
  ---- Epilog scopes ----
  ---- Scope 0
  Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)
  Epilog Start Index         : 1 (0x01)
  ---- Unwind codes ----
    E1          set_fp; mov fp, sp
    ---- Epilog start at index 1 ----
    8D          save_fplr_x #13 (0x0D); stp fp, lr, [sp, #-112]!
    E4          end
    E4          end