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; Assembly listing for method BilinearTest:BilinearInterpol_Vector(System.Double[],System.Double[],double,double,System.Double[],double,double,double):System.Double[]:this

; Emitting BLENDED_CODE for X64 CPU with AVX - Windows

; optimized code

; rsp based frame

; fully interruptible

; No matching PGO data

; Final local variable assignments

;

;* V00 this [V00 ] ( 0, 0 ) ref -> zero-ref this class-hnd single-def

; V01 arg1 [V01,T16] ( 4, 7 ) ref -> rbx class-hnd single-def

; V02 arg2 [V02,T09] ( 5, 34.68) ref -> rsi class-hnd single-def

; V03 arg3 [V03,T50] ( 4, 4 ) double -> mm6 single-def

; V03 arg3 [V03,T51] ( 4, 4 ) double -> mm6 single-def

; V04 arg4 [V04,T57] ( 2, 2 ) double -> mm7 single-def

; V04 arg4 [V04,T58] ( 2, 2 ) double -> mm7 single-def

; V05 arg5 [V05,T13] ( 3, 32.68) ref -> rdi class-hnd single-def

; V06 arg6 [V06,T58] ( 2, 2 ) double -> mm8 single-def

; V06 arg6 [V06,T59] ( 2, 2 ) double -> mm8 single-def

; V07 arg7 [V07,T59] ( 2, 2 ) double -> mm9 single-def

; V07 arg7 [V07,T60] ( 2, 2 ) double -> mm9 single-def

; V08 arg8 [V08,T60] ( 2, 2 ) double -> mm10 single-def

; V08 arg8 [V08,T61] ( 2, 2 ) double -> mm10 single-def

; V09 loc0 [V09,T17] ( 3, 6 ) ref -> rbp class-hnd exact single-def

; V10 loc1 [V10,T53] ( 2, 5 ) simd32 -> [rsp+1A0H] ld-addr-op

; V10 loc1 [V10,T54] ( 2, 5 ) simd32 -> [rsp+1A0H] ld-addr-op

; V11 loc2 [V11,T54] ( 2, 5 ) simd32 -> [rsp+180H] ld-addr-op

; V11 loc2 [V11,T55] ( 2, 5 ) simd32 -> [rsp+180H] ld-addr-op

; V12 loc3 [V12,T31] ( 4, 13 ) simd32 -> [rsp+160H] ld-addr-op

; V13 loc4 [V13,T55] ( 2, 5 ) simd32 -> [rsp+140H] ld-addr-op spill-single-def

; V13 loc4 [V13,T56] ( 2, 5 ) simd32 -> [rsp+140H] ld-addr-op spill-single-def

; V14 loc5 [V14,T32] ( 4, 13 ) simd32 -> [rsp+120H] ld-addr-op

; V15 loc6 [V15,T56] ( 2, 5 ) simd32 -> [rsp+100H] ld-addr-op

; V15 loc6 [V15,T57] ( 2, 5 ) simd32 -> [rsp+100H] ld-addr-op

; V16 loc7 [V16,T61] ( 2, 2 ) double -> mm6 single-def

; V16 loc7 [V16,T62] ( 2, 2 ) double -> mm6 single-def

; V17 loc8 [V17,T62] ( 2, 2 ) double -> mm7 single-def

; V17 loc8 [V17,T63] ( 2, 2 ) double -> mm7 single-def

; V18 loc9 [V18,T51] ( 3, 6 ) simd32 -> [rsp+E0H] ld-addr-op

; V18 loc9 [V18,T52] ( 3, 6 ) simd32 -> [rsp+E0H] ld-addr-op

; V19 loc10 [V19,T52] ( 3, 6 ) simd32 -> [rsp+C0H] ld-addr-op

; V19 loc10 [V19,T53] ( 3, 6 ) simd32 -> [rsp+C0H] ld-addr-op

; V20 loc11 [V20,T35] ( 3, 9 ) simd32 -> [rsp+A0H]

; V20 loc11 [V20,T36] ( 3, 9 ) simd32 -> [rsp+A0H]

; V21 loc12 [V21,T36] ( 3, 9 ) simd32 -> [rsp+80H]

; V21 loc12 [V21,T37] ( 3, 9 ) simd32 -> [rsp+80H]

; V22 loc13 [V22,T37] ( 3, 9 ) simd32 -> [rsp+60H] ld-addr-op

; V22 loc13 [V22,T38] ( 3, 9 ) simd32 -> [rsp+60H] ld-addr-op

; V23 loc14 [V23,T38] ( 3, 9 ) simd32 -> [rsp+40H] ld-addr-op

; V23 loc14 [V23,T39] ( 3, 9 ) simd32 -> [rsp+40H] ld-addr-op

; V24 loc15 [V24,T08] ( 9, 80.36) ref -> rax class-hnd exact single-def

; V25 loc16 [V25,T12] ( 9, 33 ) int -> rdx

; V26 loc17 [V26,T26] ( 5, 20 ) simd32 -> mm0 ld-addr-op

; V27 loc18 [V27,T24] ( 6, 35.84) simd32 -> mm1 ld-addr-op

; V28 loc19 [V28,T27] ( 2, 19.84) simd32 -> mm3 ld-addr-op

; V28 loc19 [V28,T27] ( 2, 19.84) simd32 -> mm4 ld-addr-op

; V29 loc20 [V29,T39] ( 2, 8 ) simd32 -> mm4 ld-addr-op

; V29 loc20 [V29,T40] ( 2, 8 ) simd32 -> mm5 ld-addr-op

;* V30 loc21 [V30 ] ( 0, 0 ) simd32 -> zero-ref ld-addr-op

; V31 loc22 [V31,T40] ( 2, 8 ) simd32 -> mm4

; V31 loc22 [V31,T41] ( 2, 8 ) simd32 -> mm5

; V32 loc23 [V32,T41] ( 2, 8 ) simd32 -> mm5

; V32 loc23 [V32,T42] ( 2, 8 ) simd32 -> mm13

; V33 loc24 [V33,T42] ( 2, 8 ) simd32 -> mm4

; V33 loc24 [V33,T43] ( 2, 8 ) simd32 -> mm5

; V34 loc25 [V34,T33] ( 3, 12 ) simd32 -> mm1 ld-addr-op

; V35 loc26 [V35,T43] ( 2, 8 ) simd32 -> mm3 ld-addr-op

; V35 loc26 [V35,T44] ( 2, 8 ) simd32 -> mm4 ld-addr-op

; V36 loc27 [V36,T25] ( 6, 35.84) simd32 -> mm5 ld-addr-op

; V36 loc27 [V36,T25] ( 6, 35.84) simd32 -> mm13 ld-addr-op

; V37 loc28 [V37,T28] ( 2, 19.84) simd32 -> mm13 ld-addr-op

; V37 loc28 [V37,T28] ( 2, 19.84) simd32 -> mm3 ld-addr-op

; V38 loc29 [V38,T44] ( 2, 8 ) simd32 -> mm10 ld-addr-op

; V38 loc29 [V38,T45] ( 2, 8 ) simd32 -> mm11 ld-addr-op

;* V39 loc30 [V39 ] ( 0, 0 ) simd32 -> zero-ref ld-addr-op

; V40 loc31 [V40,T45] ( 2, 8 ) simd32 -> mm10

; V40 loc31 [V40,T46] ( 2, 8 ) simd32 -> mm11

; V41 loc32 [V41,T46] ( 2, 8 ) simd32 -> mm0

; V41 loc32 [V41,T47] ( 2, 8 ) simd32 -> mm0

; V42 loc33 [V42,T47] ( 2, 8 ) simd32 -> mm0

; V42 loc33 [V42,T48] ( 2, 8 ) simd32 -> mm0

; V43 loc34 [V43,T34] ( 3, 12 ) simd32 -> mm5 ld-addr-op

; V43 loc34 [V43,T34] ( 3, 12 ) simd32 -> mm11 ld-addr-op

; V44 loc35 [V44,T48] ( 2, 8 ) simd32 -> mm10 ld-addr-op

; V44 loc35 [V44,T49] ( 2, 8 ) simd32 -> mm3 ld-addr-op

; V45 loc36 [V45,T49] ( 2, 8 ) simd32 -> mm0 ld-addr-op

; V45 loc36 [V45,T50] ( 2, 8 ) simd32 -> mm0 ld-addr-op

; V46 loc37 [V46,T04] ( 6, 83.20) int -> r9

; V47 loc38 [V47,T05] ( 6, 83.20) int -> r9

; V48 loc39 [V48,T06] ( 6, 83.20) int -> r9

; V49 loc40 [V49,T07] ( 6, 83.20) int -> r9

; V50 OutArgs [V50 ] ( 1, 1 ) lclBlk (32) [rsp+00H] "OutgoingArgSpace"

; V51 tmp1 [V51,T29] ( 2, 16 ) simd32 -> mm4 "fgInsertCommaFormTemp is creating a new local variable"

; V51 tmp1 [V51,T29] ( 2, 16 ) simd32 -> mm5 "fgInsertCommaFormTemp is creating a new local variable"

; V52 tmp2 [V52,T20] ( 2, 63.36) double -> mm5 "Strict ordering of exceptions for Array store"

; V52 tmp2 [V52,T20] ( 2, 63.36) double -> mm13 "Strict ordering of exceptions for Array store"

; V53 tmp3 [V53,T21] ( 2, 63.36) double -> mm5 "Strict ordering of exceptions for Array store"

; V53 tmp3 [V53,T21] ( 2, 63.36) double -> mm13 "Strict ordering of exceptions for Array store"

; V54 tmp4 [V54,T30] ( 2, 16 ) simd32 -> mm10 "fgInsertCommaFormTemp is creating a new local variable"

; V54 tmp4 [V54,T30] ( 2, 16 ) simd32 -> mm11 "fgInsertCommaFormTemp is creating a new local variable"

; V55 tmp5 [V55,T22] ( 2, 63.36) double -> mm10 "Strict ordering of exceptions for Array store"

; V55 tmp5 [V55,T22] ( 2, 63.36) double -> mm11 "Strict ordering of exceptions for Array store"

; V56 tmp6 [V56,T23] ( 2, 63.36) double -> mm10 "Strict ordering of exceptions for Array store"

; V56 tmp6 [V56,T23] ( 2, 63.36) double -> mm13 "Strict ordering of exceptions for Array store"

; V57 tmp7 [V57,T00] ( 3, 95.04) int -> r10 "index expr"

; V58 tmp8 [V58,T01] ( 3, 95.04) int -> r10 "index expr"

; V59 tmp9 [V59,T02] ( 3, 95.04) int -> r10 "index expr"

; V60 tmp10 [V60,T03] ( 3, 95.04) int -> r10 "index expr"

; V61 cse0 [V61,T18] ( 3, 3 ) int -> r15 "CSE - conservative"

; V62 cse1 [V62,T19] ( 3, 3 ) int -> r13 "CSE - conservative"

; V63 cse2 [V63,T10] ( 4, 33.68) int -> r14 "CSE - aggressive"

; V64 cse3 [V64,T11] ( 4, 33.68) int -> r12 "CSE - aggressive"

; V65 cse4 [V65,T14] ( 5, 14 ) int -> rcx "CSE - moderate"

; V66 cse5 [V66,T15] ( 3, 12 ) int -> r8 "CSE - moderate"

; V66 cse5 [V66,T35] ( 3, 12 ) simd32 -> mm3 "CSE - moderate"

; V67 rat0 [V67 ] ( 1, 1 ) simd32 -> [rsp+20H] must-init "SIMDInitTempVar"

; V67 cse6 [V67,T15] ( 3, 12 ) int -> r8 "CSE - moderate"

; V68 rat0 [V68 ] ( 1, 1 ) simd32 -> [rsp+20H] must-init "SIMDInitTempVar"

;

; Lcl frame size = 632

G_M4985_IG01: ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG

push r15

push r14

push r13

push r12

push rdi

push rsi

push rbp

push rbx

sub rsp, 632

vzeroupper

vmovaps qword ptr [rsp+260H], xmm6

vmovaps qword ptr [rsp+250H], xmm7

vmovaps qword ptr [rsp+240H], xmm8

vmovaps qword ptr [rsp+230H], xmm9

vmovaps qword ptr [rsp+220H], xmm10

vmovaps qword ptr [rsp+210H], xmm11

vmovaps qword ptr [rsp+200H], xmm12

vmovaps qword ptr [rsp+1F0H], xmm13

vmovaps qword ptr [rsp+1E0H], xmm14

vmovaps qword ptr [rsp+1D0H], xmm15

vxorps xmm4, xmm4

vmovdqa xmmword ptr [rsp+20H], xmm4

vmovdqa xmmword ptr [rsp+30H], xmm4

mov rbx, rdx

; gcrRegs +[rbx]

mov rsi, r8

; gcrRegs +[rsi]

vmovaps xmm6, xmm3

vmovsd xmm7, qword ptr [rsp+2E0H]

mov rdi, gword ptr [rsp+2E8H]

; gcrRegs +[rdi]

vmovsd xmm8, qword ptr [rsp+2F0H]

vmovsd xmm9, qword ptr [rsp+2F8H]

vmovsd xmm10, qword ptr [rsp+300H]

;; bbWeight=1 PerfScore 47.33

G_M4985_IG02: ; gcrefRegs=000000C8 {rbx rsi rdi}, byrefRegs=00000000 {}, byref

mov rcx, 0xD1FFAB1E ; System.Double[]

mov edx, 0x400

call CORINFO_HELP_NEWARR_1_VC

; gcrRegs +[rax]

; gcr arg pop 0

mov rbp, rax

; gcrRegs +[rbp]

vbroadcastsd ymm11, ymm10

vmovupd ymmword ptr[rsp+1A0H], ymm11

vmovsd xmm0, qword ptr [reloc @RWD00]

vsubsd xmm10, xmm0, xmm10

vbroadcastsd ymm10, ymm10

vmovupd ymmword ptr[rsp+180H], ymm10

vbroadcastsd ymm12, ymm6

vbroadcastsd ymm13, ymm7

vmovupd ymmword ptr[rsp+140H], ymm13

vbroadcastsd ymm14, ymm8

vbroadcastsd ymm15, ymm9

vsubsd xmm0, xmm7, xmm6

mov r14d, dword ptr [rsi+8]

lea ecx, [r14-1]

mov r15d, ecx

vxorps xmm1, xmm1

vcvtsi2sd xmm1, r15d

vdivsd xmm6, xmm0, xmm1

vsubsd xmm0, xmm9, xmm8

mov r12d, dword ptr [rdi+8]

lea ecx, [r12-1]

mov r13d, ecx

vxorps xmm1, xmm1

vcvtsi2sd xmm1, r13d

vdivsd xmm7, xmm0, xmm1

vbroadcastsd ymm6, ymm6

vbroadcastsd ymm7, ymm7

vmovupd ymm0, ymmword ptr[reloc @RWD00]

vdivpd ymm8, ymm0, ymm6

vmovupd ymm0, ymmword ptr[reloc @RWD00]

vdivpd ymm9, ymm0, ymm7

vmovd xmm0, r15d

vpbroadcastd ymm0, ymm0

vmovupd ymmword ptr[rsp+60H], ymm0

vmovd xmm1, r13d

vpbroadcastd ymm1, ymm1

vmovupd ymmword ptr[rsp+40H], ymm1

mov rcx, 0xD1FFAB1E ; System.Double[]

mov edx, 4

vextractf128 xmmword ptr [rsp+170H], xmm12, 1

vextractf128 xmmword ptr [rsp+130H], xmm14, 1

vextractf128 xmmword ptr [rsp+B0H], xmm8, 1

vextractf128 xmmword ptr [rsp+90H], xmm9, 1

vextractf128 xmmword ptr [rsp+F0H], xmm6, 1

vextractf128 xmmword ptr [rsp+D0H], xmm7, 1

vextractf128 xmmword ptr [rsp+150H], xmm13, 1

vextractf128 xmmword ptr [rsp+110H], xmm15, 1

call CORINFO_HELP_NEWARR_1_VC

; gcr arg pop 0

xor edx, edx

mov ecx, dword ptr [rbx+8]

test ecx, ecx

vinsertf128 xmm12, xmm12, xmmword ptr [rsp+170H], 1

vinsertf128 xmm14, xmm14, xmmword ptr [rsp+130H], 1

vinsertf128 xmm8, xmm8, xmmword ptr [rsp+B0H], 1

vinsertf128 xmm9, xmm9, xmmword ptr [rsp+90H], 1

vinsertf128 xmm6, xmm6, xmmword ptr [rsp+F0H], 1

vinsertf128 xmm7, xmm7, xmmword ptr [rsp+D0H], 1

vinsertf128 xmm13, xmm13, xmmword ptr [rsp+150H], 1

vinsertf128 xmm15, xmm15, xmmword ptr [rsp+110H], 1

jle G_M4985_IG12

;; bbWeight=1 PerfScore 169.92

G_M4985_IG03: ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz

cmp edx, ecx

jae G_M4985_IG15

lea r8d, [rdx+3]

cmp r8d, ecx

jae G_M4985_IG15

vmovupd ymm0, ymmword ptr[rbx+8*rdx+16]

vsubpd ymm1, ymm0, ymm12

vmulpd ymm1, ymm1, ymm8

vxorps ymm2, ymm2, ymm2

vcvtpd2ps ymm1, ymm1

vcvtpd2ps ymm3, ymm2

vinsertf128 xmm1, xmm3, 1

vcvttps2dq ymm1, ymm1

vxorps ymm2, ymm2, ymm2

vpmaxsd ymm1, ymm1, ymm2

vmovupd ymm2, ymmword ptr[rsp+60H]

vpminsd ymm1, ymm1, ymm2

vpaddd ymm3, ymm1, ymmword ptr[reloc @RWD32]

vmovupd ymm3, ymmword ptr[reloc @RWD32]

vpminsd ymm3, ymm3, ymm2

vpaddd ymm4, ymm1, ymm3

vcvtdq2ps ymm4, ymm1

vpminsd ymm4, ymm4, ymm2

vcvtps2pd ymm4, ymm4

vcvtdq2ps ymm5, ymm1

vmulpd ymm4, ymm4, ymm6

vcvtps2pd ymm5, ymm5

vaddpd ymm4, ymm4, ymm12

vmulpd ymm5, ymm5, ymm6

vminpd ymm5, ymm0, ymm13

vaddpd ymm5, ymm5, ymm12

vmaxpd ymm5, ymm12, ymm5

vminpd ymm13, ymm0, ymm13

vsubpd ymm4, ymm5, ymm4

vmaxpd ymm13, ymm12, ymm13

vmulpd ymm4, ymm4, ymm8

vsubpd ymm5, ymm13, ymm5

vmulpd ymm5, ymm5, ymm8

xor r9d, r9d

align [0 bytes]

;; bbWeight=4 PerfScore 265.67

;; bbWeight=4 PerfScore 275.00

G_M4985_IG04: ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG04, byref, isz

vmovupd ymmword ptr[rsp+20H], ymm1

mov r10d, dword ptr [rsp+4*r9+20H]

cmp r10d, r14d

jae G_M4985_IG16

mov r10d, r10d

vmovsd xmm5, qword ptr [rsi+8*r10+16]

vmovsd xmm13, qword ptr [rsi+8*r10+16]

mov r10d, r9d

vmovsd qword ptr [rax+8*r10+16], xmm5

vmovsd qword ptr [rax+8*r10+16], xmm13

inc r9d

cmp r9d, 4

jl SHORT G_M4985_IG04

;; bbWeight=15.84 PerfScore 194.04

G_M4985_IG05: ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz

vmovupd ymm1, ymmword ptr[rax+16]

xor r9d, r9d

align [0 bytes]

;; bbWeight=4 PerfScore 21.00

G_M4985_IG06: ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG06, byref, isz

vmovupd ymmword ptr[rsp+20H], ymm3

vmovupd ymmword ptr[rsp+20H], ymm4

mov r10d, dword ptr [rsp+4*r9+20H]

cmp r10d, r14d

jae G_M4985_IG16

mov r10d, r10d

vmovsd xmm5, qword ptr [rsi+8*r10+16]

vmovsd xmm13, qword ptr [rsi+8*r10+16]

mov r10d, r9d

vmovsd qword ptr [rax+8*r10+16], xmm5

vmovsd qword ptr [rax+8*r10+16], xmm13

inc r9d

cmp r9d, 4

jl SHORT G_M4985_IG06

;; bbWeight=15.84 PerfScore 194.04

G_M4985_IG07: ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz

vmovupd ymm3, ymmword ptr[rax+16]

vmovupd ymm4, ymmword ptr[rax+16]

vsubpd ymm5, ymm0, ymm14

vsubpd ymm13, ymm0, ymm14

vmulpd ymm5, ymm5, ymm9

vmulpd ymm13, ymm13, ymm9

vxorps ymm13, ymm13, ymm13

vcvtpd2ps ymm5, ymm5

vcvtpd2ps ymm11, ymm13

vinsertf128 xmm5, xmm11, 1

vcvttps2dq ymm5, ymm5

vxorps ymm11, ymm11, ymm11

vpmaxsd ymm5, ymm5, ymm11

vcvtpd2ps ymm13, ymm13

vmovupd ymm11, ymmword ptr[rsp+40H]

vcvtpd2ps ymm10, ymm11

vpminsd ymm5, ymm5, ymm11

vinsertf128 xmm13, xmm10, 1

vpaddd ymm13, ymm5, ymmword ptr[reloc @RWD32]

vcvttps2dq ymm13, ymm13

vpminsd ymm13, ymm13, ymm11

vxorps ymm10, ymm10, ymm10

vcvtdq2ps ymm10, ymm5

vpmaxsd ymm13, ymm13, ymm10

vcvtps2pd ymm10, ymm10

vmovupd ymm10, ymmword ptr[rsp+40H]

vmulpd ymm10, ymm10, ymm7

vpminsd ymm13, ymm13, ymm10

vaddpd ymm10, ymm10, ymm14

vpaddd ymm3, ymm13, ymm3

vpminsd ymm3, ymm3, ymm10

vcvtdq2ps ymm11, ymm13

vcvtps2pd ymm11, ymm11

vmulpd ymm11, ymm11, ymm7

vaddpd ymm11, ymm11, ymm14

vminpd ymm0, ymm0, ymm15

vmaxpd ymm0, ymm14, ymm0

vsubpd ymm0, ymm0, ymm10

vsubpd ymm0, ymm0, ymm11

vmulpd ymm0, ymm0, ymm9

xor r9d, r9d

align [0 bytes]

;; bbWeight=4 PerfScore 253.67

;; bbWeight=4 PerfScore 247.00

G_M4985_IG08: ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG08, byref, isz

vmovupd ymmword ptr[rsp+20H], ymm5

vmovupd ymmword ptr[rsp+20H], ymm13

mov r10d, dword ptr [rsp+4*r9+20H]

cmp r10d, r12d

jae G_M4985_IG16

mov r10d, r10d

vmovsd xmm10, qword ptr [rdi+8*r10+16]

vmovsd xmm11, qword ptr [rdi+8*r10+16]

mov r10d, r9d

vmovsd qword ptr [rax+8*r10+16], xmm10

vmovsd qword ptr [rax+8*r10+16], xmm11

inc r9d

cmp r9d, 4

jl SHORT G_M4985_IG08

;; bbWeight=15.84 PerfScore 194.04

G_M4985_IG09: ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz

vmovupd ymm5, ymmword ptr[rax+16]

vmovupd ymm11, ymmword ptr[rax+16]

xor r9d, r9d

align [0 bytes]

;; bbWeight=4 PerfScore 21.00

G_M4985_IG10: ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG10, byref, isz

vmovupd ymmword ptr[rsp+20H], ymm13

vmovupd ymmword ptr[rsp+20H], ymm3

mov r10d, dword ptr [rsp+4*r9+20H]

cmp r10d, r12d

jae G_M4985_IG16

mov r10d, r10d

vmovsd xmm10, qword ptr [rdi+8*r10+16]

vmovsd xmm13, qword ptr [rdi+8*r10+16]

mov r10d, r9d

vmovsd qword ptr [rax+8*r10+16], xmm10

vmovsd qword ptr [rax+8*r10+16], xmm13

inc r9d

cmp r9d, 4

jl SHORT G_M4985_IG10

;; bbWeight=15.84 PerfScore 194.04

G_M4985_IG11: ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref

vmovupd ymm10, ymmword ptr[rax+16]

vmovupd ymm3, ymmword ptr[rax+16]

vsubpd ymm3, ymm3, ymm1

vsubpd ymm4, ymm4, ymm1

vmulpd ymm3, ymm4, ymm3

vmulpd ymm4, ymm5, ymm4

vaddpd ymm1, ymm1, ymm3

vaddpd ymm1, ymm1, ymm4

vmovupd ymm13, ymmword ptr[rsp+180H]

vmulpd ymm1, ymm13, ymm1

vsubpd ymm3, ymm10, ymm5

vsubpd ymm3, ymm3, ymm11

vmulpd ymm0, ymm0, ymm3

vaddpd ymm0, ymm5, ymm0

vaddpd ymm0, ymm11, ymm0

vmovupd ymm10, ymmword ptr[rsp+1A0H]

vmovupd ymm11, ymmword ptr[rsp+1A0H]

vmulpd ymm0, ymm10, ymm0

vmulpd ymm0, ymm11, ymm0

vaddpd ymm0, ymm1, ymm0

cmp edx, 0x400

jae G_M4985_IG15

cmp r8d, 0x400

jae G_M4985_IG17

vmovupd ymmword ptr[rbp+8*rdx+16], ymm0

add edx, 4

cmp ecx, edx

vmovupd ymmword ptr[rsp+60H], ymm2

vmovupd ymmword ptr[rsp+40H], ymm11

vmovupd ymmword ptr[rsp+40H], ymm10

vmovupd ymmword ptr[rsp+1A0H], ymm10

vmovupd ymmword ptr[rsp+1A0H], ymm11

vmovupd ymmword ptr[rsp+180H], ymm13

jg G_M4985_IG14

;; bbWeight=4 PerfScore 200.00

G_M4985_IG12: ; gcrefRegs=00000020 {rbp}, byrefRegs=00000000 {}, byref

; gcrRegs -[rax rbx rsi rdi]

mov rax, rbp

; gcrRegs +[rax]

;; bbWeight=1 PerfScore 0.25

G_M4985_IG13: ; , epilog, nogc, extend

vmovaps xmm6, qword ptr [rsp+260H]

vmovaps xmm7, qword ptr [rsp+250H]

vmovaps xmm8, qword ptr [rsp+240H]

vmovaps xmm9, qword ptr [rsp+230H]

vmovaps xmm10, qword ptr [rsp+220H]

vmovaps xmm11, qword ptr [rsp+210H]

vmovaps xmm12, qword ptr [rsp+200H]

vmovaps xmm13, qword ptr [rsp+1F0H]

vmovaps xmm14, qword ptr [rsp+1E0H]

vmovaps xmm15, qword ptr [rsp+1D0H]

vzeroupper

add rsp, 632

pop rbx

pop rbp

pop rsi

pop rdi

pop r12

pop r13

pop r14

pop r15

ret

;; bbWeight=1 PerfScore 46.25

G_M4985_IG14: ; gcVars=0000000000000000 {}, gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref

; gcrRegs +[rbx rsi rdi]

vmovupd ymm13, ymmword ptr[rsp+140H]

jmp G_M4985_IG03

;; bbWeight=2 PerfScore 12.00

G_M4985_IG15: ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref

; gcrRegs -[rax rbx rbp rsi rdi]

call CORINFO_HELP_THROW_ARGUMENTOUTOFRANGEEXCEPTION

; gcr arg pop 0

int3

;; bbWeight=0 PerfScore 0.00

G_M4985_IG16: ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref

call CORINFO_HELP_RNGCHKFAIL

; gcr arg pop 0

int3

;; bbWeight=0 PerfScore 0.00

G_M4985_IG17: ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref

call CORINFO_HELP_THROW_ARGUMENTEXCEPTION

; gcr arg pop 0

int3

;; bbWeight=0 PerfScore 0.00

RWD00 dq 3FF0000000000000h, 3FF0000000000000h, 3FF0000000000000h, 3FF0000000000000h

RWD32 dq 0000000100000001h, 0000000100000001h, 0000000100000001h, 0000000100000001h

; Total bytes of code 1342, prolog size 182, PerfScore 1956.24, instruction count 252, allocated bytes for code 1430 (MethodHash=021bec86) for method BilinearTest:BilinearInterpol_Vector(System.Double[],System.Double[],double,double,System.Double[],double,double,double):System.Double[]:this

; Total bytes of code 1347, prolog size 182, PerfScore 1959.01, instruction count 253, allocated bytes for code 1431 (MethodHash=021bec86) for method BilinearTest:BilinearInterpol_Vector(System.Double[],System.Double[],double,double,System.Double[],double,double,double):System.Double[]:this

; ============================================================

Unwind Info:

>> Start offset : 0x000000 (not in unwind data)

>> End offset : 0xd1ffab1e (not in unwind data)

Version : 1

Flags : 0x00

SizeOfProlog : 0x7A

CountOfUnwindCodes: 30

FrameRegister : none (0)

FrameOffset : N/A (no FrameRegister) (Value=0)

UnwindCodes :

CodeOffset: 0x7A UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM15 (15)

Scaled Small Offset: 29 * 16 = 464 = 0x001D0

CodeOffset: 0x70 UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM14 (14)

Scaled Small Offset: 30 * 16 = 480 = 0x001E0

CodeOffset: 0x66 UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM13 (13)

Scaled Small Offset: 31 * 16 = 496 = 0x001F0

CodeOffset: 0x5C UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM12 (12)

Scaled Small Offset: 32 * 16 = 512 = 0x00200

CodeOffset: 0x52 UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM11 (11)

Scaled Small Offset: 33 * 16 = 528 = 0x00210

CodeOffset: 0x48 UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM10 (10)

Scaled Small Offset: 34 * 16 = 544 = 0x00220

CodeOffset: 0x3E UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM9 (9)

Scaled Small Offset: 35 * 16 = 560 = 0x00230

CodeOffset: 0x34 UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM8 (8)

Scaled Small Offset: 36 * 16 = 576 = 0x00240

CodeOffset: 0x2A UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM7 (7)

Scaled Small Offset: 37 * 16 = 592 = 0x00250

CodeOffset: 0x20 UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM6 (6)

Scaled Small Offset: 38 * 16 = 608 = 0x00260

CodeOffset: 0x13 UnwindOp: UWOP_ALLOC_LARGE (1) OpInfo: 0 - Scaled small

Size: 79 * 8 = 632 = 0x00278

CodeOffset: 0x0C UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3)

CodeOffset: 0x0B UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)

CodeOffset: 0x0A UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6)

CodeOffset: 0x09 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7)

CodeOffset: 0x08 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r12 (12)

CodeOffset: 0x06 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r13 (13)

CodeOffset: 0x04 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14)

CodeOffset: 0x02 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r15 (15)

已保存差異

原始文本

開啟檔案

; Assembly listing for method BilinearTest:BilinearInterpol_Vector(System.Double[],System.Double[],double,double,System.Double[],double,double,double):System.Double[]:this
; Emitting BLENDED_CODE for X64 CPU with AVX - Windows
; optimized code
; rsp based frame
; fully interruptible
; No matching PGO data
; Final local variable assignments
;
;* V00 this         [V00    ] (  0,  0   )     ref  ->  zero-ref    this class-hnd single-def
;  V01 arg1         [V01,T16] (  4,  7   )     ref  ->  rbx         class-hnd single-def
;  V02 arg2         [V02,T09] (  5, 34.68)     ref  ->  rsi         class-hnd single-def
;  V03 arg3         [V03,T50] (  4,  4   )  double  ->  mm6         single-def
;  V04 arg4         [V04,T57] (  2,  2   )  double  ->  mm7         single-def
;  V05 arg5         [V05,T13] (  3, 32.68)     ref  ->  rdi         class-hnd single-def
;  V06 arg6         [V06,T58] (  2,  2   )  double  ->  mm8         single-def
;  V07 arg7         [V07,T59] (  2,  2   )  double  ->  mm9         single-def
;  V08 arg8         [V08,T60] (  2,  2   )  double  ->  mm10         single-def
;  V09 loc0         [V09,T17] (  3,  6   )     ref  ->  rbp         class-hnd exact single-def
;  V10 loc1         [V10,T53] (  2,  5   )  simd32  ->  [rsp+1A0H]   ld-addr-op
;  V11 loc2         [V11,T54] (  2,  5   )  simd32  ->  [rsp+180H]   ld-addr-op
;  V12 loc3         [V12,T31] (  4, 13   )  simd32  ->  [rsp+160H]   ld-addr-op
;  V13 loc4         [V13,T55] (  2,  5   )  simd32  ->  [rsp+140H]   ld-addr-op spill-single-def
;  V14 loc5         [V14,T32] (  4, 13   )  simd32  ->  [rsp+120H]   ld-addr-op
;  V15 loc6         [V15,T56] (  2,  5   )  simd32  ->  [rsp+100H]   ld-addr-op
;  V16 loc7         [V16,T61] (  2,  2   )  double  ->  mm6         single-def
;  V17 loc8         [V17,T62] (  2,  2   )  double  ->  mm7         single-def
;  V18 loc9         [V18,T51] (  3,  6   )  simd32  ->  [rsp+E0H]   ld-addr-op
;  V19 loc10        [V19,T52] (  3,  6   )  simd32  ->  [rsp+C0H]   ld-addr-op
;  V20 loc11        [V20,T35] (  3,  9   )  simd32  ->  [rsp+A0H]  
;  V21 loc12        [V21,T36] (  3,  9   )  simd32  ->  [rsp+80H]  
;  V22 loc13        [V22,T37] (  3,  9   )  simd32  ->  [rsp+60H]   ld-addr-op
;  V23 loc14        [V23,T38] (  3,  9   )  simd32  ->  [rsp+40H]   ld-addr-op
;  V24 loc15        [V24,T08] (  9, 80.36)     ref  ->  rax         class-hnd exact single-def
;  V25 loc16        [V25,T12] (  9, 33   )     int  ->  rdx        
;  V26 loc17        [V26,T26] (  5, 20   )  simd32  ->  mm0         ld-addr-op
;  V27 loc18        [V27,T24] (  6, 35.84)  simd32  ->  mm1         ld-addr-op
;  V28 loc19        [V28,T27] (  2, 19.84)  simd32  ->  mm3         ld-addr-op
;  V29 loc20        [V29,T39] (  2,  8   )  simd32  ->  mm4         ld-addr-op
;* V30 loc21        [V30    ] (  0,  0   )  simd32  ->  zero-ref    ld-addr-op
;  V31 loc22        [V31,T40] (  2,  8   )  simd32  ->  mm4        
;  V32 loc23        [V32,T41] (  2,  8   )  simd32  ->  mm5        
;  V33 loc24        [V33,T42] (  2,  8   )  simd32  ->  mm4        
;  V34 loc25        [V34,T33] (  3, 12   )  simd32  ->  mm1         ld-addr-op
;  V35 loc26        [V35,T43] (  2,  8   )  simd32  ->  mm3         ld-addr-op
;  V36 loc27        [V36,T25] (  6, 35.84)  simd32  ->  mm5         ld-addr-op
;  V37 loc28        [V37,T28] (  2, 19.84)  simd32  ->  mm13         ld-addr-op
;  V38 loc29        [V38,T44] (  2,  8   )  simd32  ->  mm10         ld-addr-op
;* V39 loc30        [V39    ] (  0,  0   )  simd32  ->  zero-ref    ld-addr-op
;  V40 loc31        [V40,T45] (  2,  8   )  simd32  ->  mm10        
;  V41 loc32        [V41,T46] (  2,  8   )  simd32  ->  mm0        
;  V42 loc33        [V42,T47] (  2,  8   )  simd32  ->  mm0        
;  V43 loc34        [V43,T34] (  3, 12   )  simd32  ->  mm5         ld-addr-op
;  V44 loc35        [V44,T48] (  2,  8   )  simd32  ->  mm10         ld-addr-op
;  V45 loc36        [V45,T49] (  2,  8   )  simd32  ->  mm0         ld-addr-op
;  V46 loc37        [V46,T04] (  6, 83.20)     int  ->   r9        
;  V47 loc38        [V47,T05] (  6, 83.20)     int  ->   r9        
;  V48 loc39        [V48,T06] (  6, 83.20)     int  ->   r9        
;  V49 loc40        [V49,T07] (  6, 83.20)     int  ->   r9        
;  V50 OutArgs      [V50    ] (  1,  1   )  lclBlk (32) [rsp+00H]   "OutgoingArgSpace"
;  V51 tmp1         [V51,T29] (  2, 16   )  simd32  ->  mm4         "fgInsertCommaFormTemp is creating a new local variable"
;  V52 tmp2         [V52,T20] (  2, 63.36)  double  ->  mm5         "Strict ordering of exceptions for Array store"
;  V53 tmp3         [V53,T21] (  2, 63.36)  double  ->  mm5         "Strict ordering of exceptions for Array store"
;  V54 tmp4         [V54,T30] (  2, 16   )  simd32  ->  mm10         "fgInsertCommaFormTemp is creating a new local variable"
;  V55 tmp5         [V55,T22] (  2, 63.36)  double  ->  mm10         "Strict ordering of exceptions for Array store"
;  V56 tmp6         [V56,T23] (  2, 63.36)  double  ->  mm10         "Strict ordering of exceptions for Array store"
;  V57 tmp7         [V57,T00] (  3, 95.04)     int  ->  r10         "index expr"
;  V58 tmp8         [V58,T01] (  3, 95.04)     int  ->  r10         "index expr"
;  V59 tmp9         [V59,T02] (  3, 95.04)     int  ->  r10         "index expr"
;  V60 tmp10        [V60,T03] (  3, 95.04)     int  ->  r10         "index expr"
;  V61 cse0         [V61,T18] (  3,  3   )     int  ->  r15         "CSE - conservative"
;  V62 cse1         [V62,T19] (  3,  3   )     int  ->  r13         "CSE - conservative"
;  V63 cse2         [V63,T10] (  4, 33.68)     int  ->  r14         "CSE - aggressive"
;  V64 cse3         [V64,T11] (  4, 33.68)     int  ->  r12         "CSE - aggressive"
;  V65 cse4         [V65,T14] (  5, 14   )     int  ->  rcx         "CSE - moderate"
;  V66 cse5         [V66,T15] (  3, 12   )     int  ->   r8         "CSE - moderate"
;  V67 rat0         [V67    ] (  1,  1   )  simd32  ->  [rsp+20H]   must-init "SIMDInitTempVar"
;
; Lcl frame size = 632

G_M4985_IG01:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
       push     r15
       push     r14
       push     r13
       push     r12
       push     rdi
       push     rsi
       push     rbp
       push     rbx
       sub      rsp, 632
       vzeroupper 
       vmovaps  qword ptr [rsp+260H], xmm6
       vmovaps  qword ptr [rsp+250H], xmm7
       vmovaps  qword ptr [rsp+240H], xmm8
       vmovaps  qword ptr [rsp+230H], xmm9
       vmovaps  qword ptr [rsp+220H], xmm10
       vmovaps  qword ptr [rsp+210H], xmm11
       vmovaps  qword ptr [rsp+200H], xmm12
       vmovaps  qword ptr [rsp+1F0H], xmm13
       vmovaps  qword ptr [rsp+1E0H], xmm14
       vmovaps  qword ptr [rsp+1D0H], xmm15
       vxorps   xmm4, xmm4
       vmovdqa  xmmword ptr [rsp+20H], xmm4
       vmovdqa  xmmword ptr [rsp+30H], xmm4
       mov      rbx, rdx
       ; gcrRegs +[rbx]
       mov      rsi, r8
       ; gcrRegs +[rsi]
       vmovaps  xmm6, xmm3
       vmovsd   xmm7, qword ptr [rsp+2E0H]
       mov      rdi, gword ptr [rsp+2E8H]
       ; gcrRegs +[rdi]
       vmovsd   xmm8, qword ptr [rsp+2F0H]
       vmovsd   xmm9, qword ptr [rsp+2F8H]
       vmovsd   xmm10, qword ptr [rsp+300H]
						;; bbWeight=1    PerfScore 47.33
G_M4985_IG02:        ; gcrefRegs=000000C8 {rbx rsi rdi}, byrefRegs=00000000 {}, byref
       mov      rcx, 0xD1FFAB1E      ; System.Double[]
       mov      edx, 0x400
       call     CORINFO_HELP_NEWARR_1_VC
       ; gcrRegs +[rax]
       ; gcr arg pop 0
       mov      rbp, rax
       ; gcrRegs +[rbp]
       vbroadcastsd ymm11, ymm10
       vmovupd  ymmword ptr[rsp+1A0H], ymm11
       vmovsd   xmm0, qword ptr [reloc @RWD00]
       vsubsd   xmm10, xmm0, xmm10
       vbroadcastsd ymm10, ymm10
       vmovupd  ymmword ptr[rsp+180H], ymm10
       vbroadcastsd ymm12, ymm6
       vbroadcastsd ymm13, ymm7
       vmovupd  ymmword ptr[rsp+140H], ymm13
       vbroadcastsd ymm14, ymm8
       vbroadcastsd ymm15, ymm9
       vsubsd   xmm0, xmm7, xmm6
       mov      r14d, dword ptr [rsi+8]
       lea      ecx, [r14-1]
       mov      r15d, ecx
       vxorps   xmm1, xmm1
       vcvtsi2sd  xmm1, r15d
       vdivsd   xmm6, xmm0, xmm1
       vsubsd   xmm0, xmm9, xmm8
       mov      r12d, dword ptr [rdi+8]
       lea      ecx, [r12-1]
       mov      r13d, ecx
       vxorps   xmm1, xmm1
       vcvtsi2sd  xmm1, r13d
       vdivsd   xmm7, xmm0, xmm1
       vbroadcastsd ymm6, ymm6
       vbroadcastsd ymm7, ymm7
       vmovupd  ymm0, ymmword ptr[reloc @RWD00]
       vdivpd   ymm8, ymm0, ymm6
       vmovupd  ymm0, ymmword ptr[reloc @RWD00]
       vdivpd   ymm9, ymm0, ymm7
       vmovd    xmm0, r15d
       vpbroadcastd ymm0, ymm0
       vmovupd  ymmword ptr[rsp+60H], ymm0
       vmovd    xmm1, r13d
       vpbroadcastd ymm1, ymm1
       vmovupd  ymmword ptr[rsp+40H], ymm1
       mov      rcx, 0xD1FFAB1E      ; System.Double[]
       mov      edx, 4
       vextractf128 xmmword ptr [rsp+170H], xmm12, 1
       vextractf128 xmmword ptr [rsp+130H], xmm14, 1
       vextractf128 xmmword ptr [rsp+B0H], xmm8, 1
       vextractf128 xmmword ptr [rsp+90H], xmm9, 1
       vextractf128 xmmword ptr [rsp+F0H], xmm6, 1
       vextractf128 xmmword ptr [rsp+D0H], xmm7, 1
       vextractf128 xmmword ptr [rsp+150H], xmm13, 1
       vextractf128 xmmword ptr [rsp+110H], xmm15, 1
       call     CORINFO_HELP_NEWARR_1_VC
       ; gcr arg pop 0
       xor      edx, edx
       mov      ecx, dword ptr [rbx+8]
       test     ecx, ecx
       vinsertf128 xmm12, xmm12, xmmword ptr [rsp+170H], 1
       vinsertf128 xmm14, xmm14, xmmword ptr [rsp+130H], 1
       vinsertf128 xmm8, xmm8, xmmword ptr [rsp+B0H], 1
       vinsertf128 xmm9, xmm9, xmmword ptr [rsp+90H], 1
       vinsertf128 xmm6, xmm6, xmmword ptr [rsp+F0H], 1
       vinsertf128 xmm7, xmm7, xmmword ptr [rsp+D0H], 1
       vinsertf128 xmm13, xmm13, xmmword ptr [rsp+150H], 1
       vinsertf128 xmm15, xmm15, xmmword ptr [rsp+110H], 1
       jle      G_M4985_IG12
						;; bbWeight=1    PerfScore 169.92
G_M4985_IG03:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz
       cmp      edx, ecx
       jae      G_M4985_IG15
       lea      r8d, [rdx+3]
       cmp      r8d, ecx
       jae      G_M4985_IG15
       vmovupd  ymm0, ymmword ptr[rbx+8*rdx+16]
       vsubpd   ymm1, ymm0, ymm12
       vmulpd   ymm1, ymm1, ymm8
       vxorps   ymm2, ymm2, ymm2
       vcvtpd2ps ymm1, ymm1
       vcvtpd2ps ymm3, ymm2
       vinsertf128 xmm1, xmm3, 1
       vcvttps2dq ymm1, ymm1
       vxorps   ymm2, ymm2, ymm2
       vpmaxsd  ymm1, ymm1, ymm2
       vmovupd  ymm2, ymmword ptr[rsp+60H]
       vpminsd  ymm1, ymm1, ymm2
       vpaddd   ymm3, ymm1, ymmword ptr[reloc @RWD32]
       vpminsd  ymm3, ymm3, ymm2
       vcvtdq2ps ymm4, ymm1
       vcvtps2pd ymm4, ymm4
       vmulpd   ymm4, ymm4, ymm6
       vaddpd   ymm4, ymm4, ymm12
       vminpd   ymm5, ymm0, ymm13
       vmaxpd   ymm5, ymm12, ymm5
       vsubpd   ymm4, ymm5, ymm4
       vmulpd   ymm4, ymm4, ymm8
       xor      r9d, r9d
       align    [0 bytes]
						;; bbWeight=4    PerfScore 265.67
G_M4985_IG04:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG04, byref, isz
       vmovupd  ymmword ptr[rsp+20H], ymm1
       mov      r10d, dword ptr [rsp+4*r9+20H]
       cmp      r10d, r14d
       jae      G_M4985_IG16
       mov      r10d, r10d
       vmovsd   xmm5, qword ptr [rsi+8*r10+16]
       mov      r10d, r9d
       vmovsd   qword ptr [rax+8*r10+16], xmm5
       inc      r9d
       cmp      r9d, 4
       jl       SHORT G_M4985_IG04
						;; bbWeight=15.84 PerfScore 194.04
G_M4985_IG05:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz
       vmovupd  ymm1, ymmword ptr[rax+16]
       xor      r9d, r9d
       align    [0 bytes]
						;; bbWeight=4    PerfScore 21.00
G_M4985_IG06:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG06, byref, isz
       vmovupd  ymmword ptr[rsp+20H], ymm3
       mov      r10d, dword ptr [rsp+4*r9+20H]
       cmp      r10d, r14d
       jae      G_M4985_IG16
       mov      r10d, r10d
       vmovsd   xmm5, qword ptr [rsi+8*r10+16]
       mov      r10d, r9d
       vmovsd   qword ptr [rax+8*r10+16], xmm5
       inc      r9d
       cmp      r9d, 4
       jl       SHORT G_M4985_IG06
						;; bbWeight=15.84 PerfScore 194.04
G_M4985_IG07:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz
       vmovupd  ymm3, ymmword ptr[rax+16]
       vsubpd   ymm5, ymm0, ymm14
       vmulpd   ymm5, ymm5, ymm9
       vxorps   ymm13, ymm13, ymm13
       vcvtpd2ps ymm5, ymm5
       vcvtpd2ps ymm11, ymm13
       vinsertf128 xmm5, xmm11, 1
       vcvttps2dq ymm5, ymm5
       vxorps   ymm11, ymm11, ymm11
       vpmaxsd  ymm5, ymm5, ymm11
       vmovupd  ymm11, ymmword ptr[rsp+40H]
       vpminsd  ymm5, ymm5, ymm11
       vpaddd   ymm13, ymm5, ymmword ptr[reloc @RWD32]
       vpminsd  ymm13, ymm13, ymm11
       vcvtdq2ps ymm10, ymm5
       vcvtps2pd ymm10, ymm10
       vmulpd   ymm10, ymm10, ymm7
       vaddpd   ymm10, ymm10, ymm14
       vminpd   ymm0, ymm0, ymm15
       vmaxpd   ymm0, ymm14, ymm0
       vsubpd   ymm0, ymm0, ymm10
       vmulpd   ymm0, ymm0, ymm9
       xor      r9d, r9d
       align    [0 bytes]
						;; bbWeight=4    PerfScore 253.67
G_M4985_IG08:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG08, byref, isz
       vmovupd  ymmword ptr[rsp+20H], ymm5
       mov      r10d, dword ptr [rsp+4*r9+20H]
       cmp      r10d, r12d
       jae      G_M4985_IG16
       mov      r10d, r10d
       vmovsd   xmm10, qword ptr [rdi+8*r10+16]
       mov      r10d, r9d
       vmovsd   qword ptr [rax+8*r10+16], xmm10
       inc      r9d
       cmp      r9d, 4
       jl       SHORT G_M4985_IG08
						;; bbWeight=15.84 PerfScore 194.04
G_M4985_IG09:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz
       vmovupd  ymm5, ymmword ptr[rax+16]
       xor      r9d, r9d
       align    [0 bytes]
						;; bbWeight=4    PerfScore 21.00
G_M4985_IG10:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG10, byref, isz
       vmovupd  ymmword ptr[rsp+20H], ymm13
       mov      r10d, dword ptr [rsp+4*r9+20H]
       cmp      r10d, r12d
       jae      G_M4985_IG16
       mov      r10d, r10d
       vmovsd   xmm10, qword ptr [rdi+8*r10+16]
       mov      r10d, r9d
       vmovsd   qword ptr [rax+8*r10+16], xmm10
       inc      r9d
       cmp      r9d, 4
       jl       SHORT G_M4985_IG10
						;; bbWeight=15.84 PerfScore 194.04
G_M4985_IG11:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref
       vmovupd  ymm10, ymmword ptr[rax+16]
       vsubpd   ymm3, ymm3, ymm1
       vmulpd   ymm3, ymm4, ymm3
       vaddpd   ymm1, ymm1, ymm3
       vmovupd  ymm13, ymmword ptr[rsp+180H]
       vmulpd   ymm1, ymm13, ymm1
       vsubpd   ymm3, ymm10, ymm5
       vmulpd   ymm0, ymm0, ymm3
       vaddpd   ymm0, ymm5, ymm0
       vmovupd  ymm10, ymmword ptr[rsp+1A0H]
       vmulpd   ymm0, ymm10, ymm0
       vaddpd   ymm0, ymm1, ymm0
       cmp      edx, 0x400
       jae      G_M4985_IG15
       cmp      r8d, 0x400
       jae      G_M4985_IG17
       vmovupd  ymmword ptr[rbp+8*rdx+16], ymm0
       add      edx, 4
       cmp      ecx, edx
       vmovupd  ymmword ptr[rsp+60H], ymm2
       vmovupd  ymmword ptr[rsp+40H], ymm11
       vmovupd  ymmword ptr[rsp+1A0H], ymm10
       vmovupd  ymmword ptr[rsp+180H], ymm13
       jg       G_M4985_IG14
						;; bbWeight=4    PerfScore 200.00
G_M4985_IG12:        ; gcrefRegs=00000020 {rbp}, byrefRegs=00000000 {}, byref
       ; gcrRegs -[rax rbx rsi rdi]
       mov      rax, rbp
       ; gcrRegs +[rax]
						;; bbWeight=1    PerfScore 0.25
G_M4985_IG13:        ; , epilog, nogc, extend
       vmovaps  xmm6, qword ptr [rsp+260H]
       vmovaps  xmm7, qword ptr [rsp+250H]
       vmovaps  xmm8, qword ptr [rsp+240H]
       vmovaps  xmm9, qword ptr [rsp+230H]
       vmovaps  xmm10, qword ptr [rsp+220H]
       vmovaps  xmm11, qword ptr [rsp+210H]
       vmovaps  xmm12, qword ptr [rsp+200H]
       vmovaps  xmm13, qword ptr [rsp+1F0H]
       vmovaps  xmm14, qword ptr [rsp+1E0H]
       vmovaps  xmm15, qword ptr [rsp+1D0H]
       vzeroupper 
       add      rsp, 632
       pop      rbx
       pop      rbp
       pop      rsi
       pop      rdi
       pop      r12
       pop      r13
       pop      r14
       pop      r15
       ret      
						;; bbWeight=1    PerfScore 46.25
G_M4985_IG14:        ; gcVars=0000000000000000 {}, gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref
       ; gcrRegs +[rbx rsi rdi]
       vmovupd  ymm13, ymmword ptr[rsp+140H]
       jmp      G_M4985_IG03
						;; bbWeight=2    PerfScore 12.00
G_M4985_IG15:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
       ; gcrRegs -[rax rbx rbp rsi rdi]
       call     CORINFO_HELP_THROW_ARGUMENTOUTOFRANGEEXCEPTION
       ; gcr arg pop 0
       int3     
						;; bbWeight=0    PerfScore 0.00
G_M4985_IG16:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
       call     CORINFO_HELP_RNGCHKFAIL
       ; gcr arg pop 0
       int3     
						;; bbWeight=0    PerfScore 0.00
G_M4985_IG17:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
       call     CORINFO_HELP_THROW_ARGUMENTEXCEPTION
       ; gcr arg pop 0
       int3     
						;; bbWeight=0    PerfScore 0.00
RWD00  	dq	3FF0000000000000h, 3FF0000000000000h, 3FF0000000000000h, 3FF0000000000000h
RWD32  	dq	0000000100000001h, 0000000100000001h, 0000000100000001h, 0000000100000001h

Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0xd1ffab1e (not in unwind data)
  Version           : 1
  Flags             : 0x00
  SizeOfProlog      : 0x7A
  CountOfUnwindCodes: 30
  FrameRegister     : none (0)
  FrameOffset       : N/A (no FrameRegister) (Value=0)
  UnwindCodes       :
    CodeOffset: 0x7A UnwindOp: UWOP_SAVE_XMM128 (8)     OpInfo: XMM15 (15)
      Scaled Small Offset: 29 * 16 = 464 = 0x001D0
    CodeOffset: 0x70 UnwindOp: UWOP_SAVE_XMM128 (8)     OpInfo: XMM14 (14)
      Scaled Small Offset: 30 * 16 = 480 = 0x001E0
    CodeOffset: 0x66 UnwindOp: UWOP_SAVE_XMM128 (8)     OpInfo: XMM13 (13)
      Scaled Small Offset: 31 * 16 = 496 = 0x001F0
    CodeOffset: 0x5C UnwindOp: UWOP_SAVE_XMM128 (8)     OpInfo: XMM12 (12)
      Scaled Small Offset: 32 * 16 = 512 = 0x00200
    CodeOffset: 0x52 UnwindOp: UWOP_SAVE_XMM128 (8)     OpInfo: XMM11 (11)
      Scaled Small Offset: 33 * 16 = 528 = 0x00210
    CodeOffset: 0x48 UnwindOp: UWOP_SAVE_XMM128 (8)     OpInfo: XMM10 (10)
      Scaled Small Offset: 34 * 16 = 544 = 0x00220
    CodeOffset: 0x3E UnwindOp: UWOP_SAVE_XMM128 (8)     OpInfo: XMM9 (9)
      Scaled Small Offset: 35 * 16 = 560 = 0x00230
    CodeOffset: 0x34 UnwindOp: UWOP_SAVE_XMM128 (8)     OpInfo: XMM8 (8)
      Scaled Small Offset: 36 * 16 = 576 = 0x00240
    CodeOffset: 0x2A UnwindOp: UWOP_SAVE_XMM128 (8)     OpInfo: XMM7 (7)
      Scaled Small Offset: 37 * 16 = 592 = 0x00250
    CodeOffset: 0x20 UnwindOp: UWOP_SAVE_XMM128 (8)     OpInfo: XMM6 (6)
      Scaled Small Offset: 38 * 16 = 608 = 0x00260
    CodeOffset: 0x13 UnwindOp: UWOP_ALLOC_LARGE (1)     OpInfo: 0 - Scaled small  
      Size: 79 * 8 = 632 = 0x00278
    CodeOffset: 0x0C UnwindOp: UWOP_PUSH_NONVOL (0)     OpInfo: rbx (3)
    CodeOffset: 0x0B UnwindOp: UWOP_PUSH_NONVOL (0)     OpInfo: rbp (5)
    CodeOffset: 0x0A UnwindOp: UWOP_PUSH_NONVOL (0)     OpInfo: rsi (6)
    CodeOffset: 0x09 UnwindOp: UWOP_PUSH_NONVOL (0)     OpInfo: rdi (7)
    CodeOffset: 0x08 UnwindOp: UWOP_PUSH_NONVOL (0)     OpInfo: r12 (12)
    CodeOffset: 0x06 UnwindOp: UWOP_PUSH_NONVOL (0)     OpInfo: r13 (13)
    CodeOffset: 0x04 UnwindOp: UWOP_PUSH_NONVOL (0)     OpInfo: r14 (14)
    CodeOffset: 0x02 UnwindOp: UWOP_PUSH_NONVOL (0)     OpInfo: r15 (15)

更改後文本

開啟檔案

; Assembly listing for method BilinearTest:BilinearInterpol_Vector(System.Double[],System.Double[],double,double,System.Double[],double,double,double):System.Double[]:this
; Emitting BLENDED_CODE for X64 CPU with AVX - Windows
; optimized code
; rsp based frame
; fully interruptible
; No matching PGO data
; Final local variable assignments
;
;* V00 this         [V00    ] (  0,  0   )     ref  ->  zero-ref    this class-hnd single-def
;  V01 arg1         [V01,T16] (  4,  7   )     ref  ->  rbx         class-hnd single-def
;  V02 arg2         [V02,T09] (  5, 34.68)     ref  ->  rsi         class-hnd single-def
;  V03 arg3         [V03,T51] (  4,  4   )  double  ->  mm6         single-def
;  V04 arg4         [V04,T58] (  2,  2   )  double  ->  mm7         single-def
;  V05 arg5         [V05,T13] (  3, 32.68)     ref  ->  rdi         class-hnd single-def
;  V06 arg6         [V06,T59] (  2,  2   )  double  ->  mm8         single-def
;  V07 arg7         [V07,T60] (  2,  2   )  double  ->  mm9         single-def
;  V08 arg8         [V08,T61] (  2,  2   )  double  ->  mm10         single-def
;  V09 loc0         [V09,T17] (  3,  6   )     ref  ->  rbp         class-hnd exact single-def
;  V10 loc1         [V10,T54] (  2,  5   )  simd32  ->  [rsp+1A0H]   ld-addr-op
;  V11 loc2         [V11,T55] (  2,  5   )  simd32  ->  [rsp+180H]   ld-addr-op
;  V12 loc3         [V12,T31] (  4, 13   )  simd32  ->  [rsp+160H]   ld-addr-op
;  V13 loc4         [V13,T56] (  2,  5   )  simd32  ->  [rsp+140H]   ld-addr-op spill-single-def
;  V14 loc5         [V14,T32] (  4, 13   )  simd32  ->  [rsp+120H]   ld-addr-op
;  V15 loc6         [V15,T57] (  2,  5   )  simd32  ->  [rsp+100H]   ld-addr-op
;  V16 loc7         [V16,T62] (  2,  2   )  double  ->  mm6         single-def
;  V17 loc8         [V17,T63] (  2,  2   )  double  ->  mm7         single-def
;  V18 loc9         [V18,T52] (  3,  6   )  simd32  ->  [rsp+E0H]   ld-addr-op
;  V19 loc10        [V19,T53] (  3,  6   )  simd32  ->  [rsp+C0H]   ld-addr-op
;  V20 loc11        [V20,T36] (  3,  9   )  simd32  ->  [rsp+A0H]  
;  V21 loc12        [V21,T37] (  3,  9   )  simd32  ->  [rsp+80H]  
;  V22 loc13        [V22,T38] (  3,  9   )  simd32  ->  [rsp+60H]   ld-addr-op
;  V23 loc14        [V23,T39] (  3,  9   )  simd32  ->  [rsp+40H]   ld-addr-op
;  V24 loc15        [V24,T08] (  9, 80.36)     ref  ->  rax         class-hnd exact single-def
;  V25 loc16        [V25,T12] (  9, 33   )     int  ->  rdx        
;  V26 loc17        [V26,T26] (  5, 20   )  simd32  ->  mm0         ld-addr-op
;  V27 loc18        [V27,T24] (  6, 35.84)  simd32  ->  mm1         ld-addr-op
;  V28 loc19        [V28,T27] (  2, 19.84)  simd32  ->  mm4         ld-addr-op
;  V29 loc20        [V29,T40] (  2,  8   )  simd32  ->  mm5         ld-addr-op
;* V30 loc21        [V30    ] (  0,  0   )  simd32  ->  zero-ref    ld-addr-op
;  V31 loc22        [V31,T41] (  2,  8   )  simd32  ->  mm5        
;  V32 loc23        [V32,T42] (  2,  8   )  simd32  ->  mm13        
;  V33 loc24        [V33,T43] (  2,  8   )  simd32  ->  mm5        
;  V34 loc25        [V34,T33] (  3, 12   )  simd32  ->  mm1         ld-addr-op
;  V35 loc26        [V35,T44] (  2,  8   )  simd32  ->  mm4         ld-addr-op
;  V36 loc27        [V36,T25] (  6, 35.84)  simd32  ->  mm13         ld-addr-op
;  V37 loc28        [V37,T28] (  2, 19.84)  simd32  ->  mm3         ld-addr-op
;  V38 loc29        [V38,T45] (  2,  8   )  simd32  ->  mm11         ld-addr-op
;* V39 loc30        [V39    ] (  0,  0   )  simd32  ->  zero-ref    ld-addr-op
;  V40 loc31        [V40,T46] (  2,  8   )  simd32  ->  mm11        
;  V41 loc32        [V41,T47] (  2,  8   )  simd32  ->  mm0        
;  V42 loc33        [V42,T48] (  2,  8   )  simd32  ->  mm0        
;  V43 loc34        [V43,T34] (  3, 12   )  simd32  ->  mm11         ld-addr-op
;  V44 loc35        [V44,T49] (  2,  8   )  simd32  ->  mm3         ld-addr-op
;  V45 loc36        [V45,T50] (  2,  8   )  simd32  ->  mm0         ld-addr-op
;  V46 loc37        [V46,T04] (  6, 83.20)     int  ->   r9        
;  V47 loc38        [V47,T05] (  6, 83.20)     int  ->   r9        
;  V48 loc39        [V48,T06] (  6, 83.20)     int  ->   r9        
;  V49 loc40        [V49,T07] (  6, 83.20)     int  ->   r9        
;  V50 OutArgs      [V50    ] (  1,  1   )  lclBlk (32) [rsp+00H]   "OutgoingArgSpace"
;  V51 tmp1         [V51,T29] (  2, 16   )  simd32  ->  mm5         "fgInsertCommaFormTemp is creating a new local variable"
;  V52 tmp2         [V52,T20] (  2, 63.36)  double  ->  mm13         "Strict ordering of exceptions for Array store"
;  V53 tmp3         [V53,T21] (  2, 63.36)  double  ->  mm13         "Strict ordering of exceptions for Array store"
;  V54 tmp4         [V54,T30] (  2, 16   )  simd32  ->  mm11         "fgInsertCommaFormTemp is creating a new local variable"
;  V55 tmp5         [V55,T22] (  2, 63.36)  double  ->  mm11         "Strict ordering of exceptions for Array store"
;  V56 tmp6         [V56,T23] (  2, 63.36)  double  ->  mm13         "Strict ordering of exceptions for Array store"
;  V57 tmp7         [V57,T00] (  3, 95.04)     int  ->  r10         "index expr"
;  V58 tmp8         [V58,T01] (  3, 95.04)     int  ->  r10         "index expr"
;  V59 tmp9         [V59,T02] (  3, 95.04)     int  ->  r10         "index expr"
;  V60 tmp10        [V60,T03] (  3, 95.04)     int  ->  r10         "index expr"
;  V61 cse0         [V61,T18] (  3,  3   )     int  ->  r15         "CSE - conservative"
;  V62 cse1         [V62,T19] (  3,  3   )     int  ->  r13         "CSE - conservative"
;  V63 cse2         [V63,T10] (  4, 33.68)     int  ->  r14         "CSE - aggressive"
;  V64 cse3         [V64,T11] (  4, 33.68)     int  ->  r12         "CSE - aggressive"
;  V65 cse4         [V65,T14] (  5, 14   )     int  ->  rcx         "CSE - moderate"
;  V66 cse5         [V66,T35] (  3, 12   )  simd32  ->  mm3         "CSE - moderate"
;  V67 cse6         [V67,T15] (  3, 12   )     int  ->   r8         "CSE - moderate"
;  V68 rat0         [V68    ] (  1,  1   )  simd32  ->  [rsp+20H]   must-init "SIMDInitTempVar"
;
; Lcl frame size = 632

G_M4985_IG01:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
       push     r15
       push     r14
       push     r13
       push     r12
       push     rdi
       push     rsi
       push     rbp
       push     rbx
       sub      rsp, 632
       vzeroupper 
       vmovaps  qword ptr [rsp+260H], xmm6
       vmovaps  qword ptr [rsp+250H], xmm7
       vmovaps  qword ptr [rsp+240H], xmm8
       vmovaps  qword ptr [rsp+230H], xmm9
       vmovaps  qword ptr [rsp+220H], xmm10
       vmovaps  qword ptr [rsp+210H], xmm11
       vmovaps  qword ptr [rsp+200H], xmm12
       vmovaps  qword ptr [rsp+1F0H], xmm13
       vmovaps  qword ptr [rsp+1E0H], xmm14
       vmovaps  qword ptr [rsp+1D0H], xmm15
       vxorps   xmm4, xmm4
       vmovdqa  xmmword ptr [rsp+20H], xmm4
       vmovdqa  xmmword ptr [rsp+30H], xmm4
       mov      rbx, rdx
       ; gcrRegs +[rbx]
       mov      rsi, r8
       ; gcrRegs +[rsi]
       vmovaps  xmm6, xmm3
       vmovsd   xmm7, qword ptr [rsp+2E0H]
       mov      rdi, gword ptr [rsp+2E8H]
       ; gcrRegs +[rdi]
       vmovsd   xmm8, qword ptr [rsp+2F0H]
       vmovsd   xmm9, qword ptr [rsp+2F8H]
       vmovsd   xmm10, qword ptr [rsp+300H]
						;; bbWeight=1    PerfScore 47.33
G_M4985_IG02:        ; gcrefRegs=000000C8 {rbx rsi rdi}, byrefRegs=00000000 {}, byref
       mov      rcx, 0xD1FFAB1E      ; System.Double[]
       mov      edx, 0x400
       call     CORINFO_HELP_NEWARR_1_VC
       ; gcrRegs +[rax]
       ; gcr arg pop 0
       mov      rbp, rax
       ; gcrRegs +[rbp]
       vbroadcastsd ymm11, ymm10
       vmovupd  ymmword ptr[rsp+1A0H], ymm11
       vmovsd   xmm0, qword ptr [reloc @RWD00]
       vsubsd   xmm10, xmm0, xmm10
       vbroadcastsd ymm10, ymm10
       vmovupd  ymmword ptr[rsp+180H], ymm10
       vbroadcastsd ymm12, ymm6
       vbroadcastsd ymm13, ymm7
       vmovupd  ymmword ptr[rsp+140H], ymm13
       vbroadcastsd ymm14, ymm8
       vbroadcastsd ymm15, ymm9
       vsubsd   xmm0, xmm7, xmm6
       mov      r14d, dword ptr [rsi+8]
       lea      ecx, [r14-1]
       mov      r15d, ecx
       vxorps   xmm1, xmm1
       vcvtsi2sd  xmm1, r15d
       vdivsd   xmm6, xmm0, xmm1
       vsubsd   xmm0, xmm9, xmm8
       mov      r12d, dword ptr [rdi+8]
       lea      ecx, [r12-1]
       mov      r13d, ecx
       vxorps   xmm1, xmm1
       vcvtsi2sd  xmm1, r13d
       vdivsd   xmm7, xmm0, xmm1
       vbroadcastsd ymm6, ymm6
       vbroadcastsd ymm7, ymm7
       vmovupd  ymm0, ymmword ptr[reloc @RWD00]
       vdivpd   ymm8, ymm0, ymm6
       vmovupd  ymm0, ymmword ptr[reloc @RWD00]
       vdivpd   ymm9, ymm0, ymm7
       vmovd    xmm0, r15d
       vpbroadcastd ymm0, ymm0
       vmovupd  ymmword ptr[rsp+60H], ymm0
       vmovd    xmm1, r13d
       vpbroadcastd ymm1, ymm1
       vmovupd  ymmword ptr[rsp+40H], ymm1
       mov      rcx, 0xD1FFAB1E      ; System.Double[]
       mov      edx, 4
       vextractf128 xmmword ptr [rsp+170H], xmm12, 1
       vextractf128 xmmword ptr [rsp+130H], xmm14, 1
       vextractf128 xmmword ptr [rsp+B0H], xmm8, 1
       vextractf128 xmmword ptr [rsp+90H], xmm9, 1
       vextractf128 xmmword ptr [rsp+F0H], xmm6, 1
       vextractf128 xmmword ptr [rsp+D0H], xmm7, 1
       vextractf128 xmmword ptr [rsp+150H], xmm13, 1
       vextractf128 xmmword ptr [rsp+110H], xmm15, 1
       call     CORINFO_HELP_NEWARR_1_VC
       ; gcr arg pop 0
       xor      edx, edx
       mov      ecx, dword ptr [rbx+8]
       test     ecx, ecx
       vinsertf128 xmm12, xmm12, xmmword ptr [rsp+170H], 1
       vinsertf128 xmm14, xmm14, xmmword ptr [rsp+130H], 1
       vinsertf128 xmm8, xmm8, xmmword ptr [rsp+B0H], 1
       vinsertf128 xmm9, xmm9, xmmword ptr [rsp+90H], 1
       vinsertf128 xmm6, xmm6, xmmword ptr [rsp+F0H], 1
       vinsertf128 xmm7, xmm7, xmmword ptr [rsp+D0H], 1
       vinsertf128 xmm13, xmm13, xmmword ptr [rsp+150H], 1
       vinsertf128 xmm15, xmm15, xmmword ptr [rsp+110H], 1
       jle      G_M4985_IG12
						;; bbWeight=1    PerfScore 169.92
G_M4985_IG03:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz
       cmp      edx, ecx
       jae      G_M4985_IG15
       lea      r8d, [rdx+3]
       cmp      r8d, ecx
       jae      G_M4985_IG15
       vmovupd  ymm0, ymmword ptr[rbx+8*rdx+16]
       vsubpd   ymm1, ymm0, ymm12
       vmulpd   ymm1, ymm1, ymm8
       vxorps   ymm2, ymm2, ymm2
       vcvtpd2ps ymm1, ymm1
       vcvtpd2ps ymm3, ymm2
       vinsertf128 xmm1, xmm3, 1
       vcvttps2dq ymm1, ymm1
       vxorps   ymm2, ymm2, ymm2
       vpmaxsd  ymm1, ymm1, ymm2
       vmovupd  ymm2, ymmword ptr[rsp+60H]
       vpminsd  ymm1, ymm1, ymm2
       vmovupd  ymm3, ymmword ptr[reloc @RWD32]
       vpaddd   ymm4, ymm1, ymm3
       vpminsd  ymm4, ymm4, ymm2
       vcvtdq2ps ymm5, ymm1
       vcvtps2pd ymm5, ymm5
       vmulpd   ymm5, ymm5, ymm6
       vaddpd   ymm5, ymm5, ymm12
       vminpd   ymm13, ymm0, ymm13
       vmaxpd   ymm13, ymm12, ymm13
       vsubpd   ymm5, ymm13, ymm5
       vmulpd   ymm5, ymm5, ymm8
       xor      r9d, r9d
       align    [0 bytes]
						;; bbWeight=4    PerfScore 275.00
G_M4985_IG04:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG04, byref, isz
       vmovupd  ymmword ptr[rsp+20H], ymm1
       mov      r10d, dword ptr [rsp+4*r9+20H]
       cmp      r10d, r14d
       jae      G_M4985_IG16
       mov      r10d, r10d
       vmovsd   xmm13, qword ptr [rsi+8*r10+16]
       mov      r10d, r9d
       vmovsd   qword ptr [rax+8*r10+16], xmm13
       inc      r9d
       cmp      r9d, 4
       jl       SHORT G_M4985_IG04
						;; bbWeight=15.84 PerfScore 194.04
G_M4985_IG05:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz
       vmovupd  ymm1, ymmword ptr[rax+16]
       xor      r9d, r9d
       align    [0 bytes]
						;; bbWeight=4    PerfScore 21.00
G_M4985_IG06:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG06, byref, isz
       vmovupd  ymmword ptr[rsp+20H], ymm4
       mov      r10d, dword ptr [rsp+4*r9+20H]
       cmp      r10d, r14d
       jae      G_M4985_IG16
       mov      r10d, r10d
       vmovsd   xmm13, qword ptr [rsi+8*r10+16]
       mov      r10d, r9d
       vmovsd   qword ptr [rax+8*r10+16], xmm13
       inc      r9d
       cmp      r9d, 4
       jl       SHORT G_M4985_IG06
						;; bbWeight=15.84 PerfScore 194.04
G_M4985_IG07:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz
       vmovupd  ymm4, ymmword ptr[rax+16]
       vsubpd   ymm13, ymm0, ymm14
       vmulpd   ymm13, ymm13, ymm9
       vxorps   ymm11, ymm11, ymm11
       vcvtpd2ps ymm13, ymm13
       vcvtpd2ps ymm10, ymm11
       vinsertf128 xmm13, xmm10, 1
       vcvttps2dq ymm13, ymm13
       vxorps   ymm10, ymm10, ymm10
       vpmaxsd  ymm13, ymm13, ymm10
       vmovupd  ymm10, ymmword ptr[rsp+40H]
       vpminsd  ymm13, ymm13, ymm10
       vpaddd   ymm3, ymm13, ymm3
       vpminsd  ymm3, ymm3, ymm10
       vcvtdq2ps ymm11, ymm13
       vcvtps2pd ymm11, ymm11
       vmulpd   ymm11, ymm11, ymm7
       vaddpd   ymm11, ymm11, ymm14
       vminpd   ymm0, ymm0, ymm15
       vmaxpd   ymm0, ymm14, ymm0
       vsubpd   ymm0, ymm0, ymm11
       vmulpd   ymm0, ymm0, ymm9
       xor      r9d, r9d
       align    [0 bytes]
						;; bbWeight=4    PerfScore 247.00
G_M4985_IG08:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG08, byref, isz
       vmovupd  ymmword ptr[rsp+20H], ymm13
       mov      r10d, dword ptr [rsp+4*r9+20H]
       cmp      r10d, r12d
       jae      G_M4985_IG16
       mov      r10d, r10d
       vmovsd   xmm11, qword ptr [rdi+8*r10+16]
       mov      r10d, r9d
       vmovsd   qword ptr [rax+8*r10+16], xmm11
       inc      r9d
       cmp      r9d, 4
       jl       SHORT G_M4985_IG08
						;; bbWeight=15.84 PerfScore 194.04
G_M4985_IG09:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz
       vmovupd  ymm11, ymmword ptr[rax+16]
       xor      r9d, r9d
       align    [0 bytes]
						;; bbWeight=4    PerfScore 21.00
G_M4985_IG10:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, loop=IG10, byref, isz
       vmovupd  ymmword ptr[rsp+20H], ymm3
       mov      r10d, dword ptr [rsp+4*r9+20H]
       cmp      r10d, r12d
       jae      G_M4985_IG16
       mov      r10d, r10d
       vmovsd   xmm13, qword ptr [rdi+8*r10+16]
       mov      r10d, r9d
       vmovsd   qword ptr [rax+8*r10+16], xmm13
       inc      r9d
       cmp      r9d, 4
       jl       SHORT G_M4985_IG10
						;; bbWeight=15.84 PerfScore 194.04
G_M4985_IG11:        ; gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, byref
       vmovupd  ymm3, ymmword ptr[rax+16]
       vsubpd   ymm4, ymm4, ymm1
       vmulpd   ymm4, ymm5, ymm4
       vaddpd   ymm1, ymm1, ymm4
       vmovupd  ymm13, ymmword ptr[rsp+180H]
       vmulpd   ymm1, ymm13, ymm1
       vsubpd   ymm3, ymm3, ymm11
       vmulpd   ymm0, ymm0, ymm3
       vaddpd   ymm0, ymm11, ymm0
       vmovupd  ymm11, ymmword ptr[rsp+1A0H]
       vmulpd   ymm0, ymm11, ymm0
       vaddpd   ymm0, ymm1, ymm0
       cmp      edx, 0x400
       jae      G_M4985_IG15
       cmp      r8d, 0x400
       jae      G_M4985_IG17
       vmovupd  ymmword ptr[rbp+8*rdx+16], ymm0
       add      edx, 4
       cmp      ecx, edx
       vmovupd  ymmword ptr[rsp+60H], ymm2
       vmovupd  ymmword ptr[rsp+40H], ymm10
       vmovupd  ymmword ptr[rsp+1A0H], ymm11
       vmovupd  ymmword ptr[rsp+180H], ymm13
       jg       G_M4985_IG14
						;; bbWeight=4    PerfScore 200.00
G_M4985_IG12:        ; gcrefRegs=00000020 {rbp}, byrefRegs=00000000 {}, byref
       ; gcrRegs -[rax rbx rsi rdi]
       mov      rax, rbp
       ; gcrRegs +[rax]
						;; bbWeight=1    PerfScore 0.25
G_M4985_IG13:        ; , epilog, nogc, extend
       vmovaps  xmm6, qword ptr [rsp+260H]
       vmovaps  xmm7, qword ptr [rsp+250H]
       vmovaps  xmm8, qword ptr [rsp+240H]
       vmovaps  xmm9, qword ptr [rsp+230H]
       vmovaps  xmm10, qword ptr [rsp+220H]
       vmovaps  xmm11, qword ptr [rsp+210H]
       vmovaps  xmm12, qword ptr [rsp+200H]
       vmovaps  xmm13, qword ptr [rsp+1F0H]
       vmovaps  xmm14, qword ptr [rsp+1E0H]
       vmovaps  xmm15, qword ptr [rsp+1D0H]
       vzeroupper 
       add      rsp, 632
       pop      rbx
       pop      rbp
       pop      rsi
       pop      rdi
       pop      r12
       pop      r13
       pop      r14
       pop      r15
       ret      
						;; bbWeight=1    PerfScore 46.25
G_M4985_IG14:        ; gcVars=0000000000000000 {}, gcrefRegs=000000E9 {rax rbx rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref
       ; gcrRegs +[rbx rsi rdi]
       vmovupd  ymm13, ymmword ptr[rsp+140H]
       jmp      G_M4985_IG03
						;; bbWeight=2    PerfScore 12.00
G_M4985_IG15:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
       ; gcrRegs -[rax rbx rbp rsi rdi]
       call     CORINFO_HELP_THROW_ARGUMENTOUTOFRANGEEXCEPTION
       ; gcr arg pop 0
       int3     
						;; bbWeight=0    PerfScore 0.00
G_M4985_IG16:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
       call     CORINFO_HELP_RNGCHKFAIL
       ; gcr arg pop 0
       int3     
						;; bbWeight=0    PerfScore 0.00
G_M4985_IG17:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
       call     CORINFO_HELP_THROW_ARGUMENTEXCEPTION
       ; gcr arg pop 0
       int3     
						;; bbWeight=0    PerfScore 0.00
RWD00  	dq	3FF0000000000000h, 3FF0000000000000h, 3FF0000000000000h, 3FF0000000000000h
RWD32  	dq	0000000100000001h, 0000000100000001h, 0000000100000001h, 0000000100000001h