Untitled diff
建立於 差異永不過期
> +#define EXYNOS_4210_UPHYPWR 0x0
>> +#define EXYNOS_4212_UPHYPWR 0x0
> +
> +
> +#define EXYNOS_4210_UPHYPWR_PHY0_SUSPEND (1 << 0)
> +#define EXYNOS_4212_UPHYPWR_DEV_SUSPEND (1 << 0)
> +#define EXYNOS_4210_UPHYPWR_PHY0_PWR (1 << 3)
> +#define EXYNOS_4212_UPHYPWR_DEV_PWR (1 << 3)
> +#define EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR (1 << 4)
> +#define EXYNOS_4212_UPHYPWR_DEV_OTG_PWR (1 << 4)
> +#define EXYNOS_4210_UPHYPWR_PHY0_SLEEP (1 << 5)
> +#define EXYNOS_4212_UPHYPWR_DEV_SLEEP (1 << 5)
> +#define EXYNOS_4210_UPHYPWR_PHY0 ( \
> +#define EXYNOS_4212_UPHYPWR_DEV ( \
> + EXYNOS_4210_UPHYPWR_PHY0_SUSPEND | \
> + EXYNOS_4212_UPHYPWR_DEV_SUSPEND | \
> + EXYNOS_4210_UPHYPWR_PHY0_PWR | \
> + EXYNOS_4212_UPHYPWR_DEV_PWR | \
> + EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR | \
> + EXYNOS_4212_UPHYPWR_DEV_OTG_PWR | \
> + EXYNOS_4210_UPHYPWR_PHY0_SLEEP)
> + EXYNOS_4212_UPHYPWR_DEV_SLEEP)
> +
> +
> +#define EXYNOS_4210_UPHYPWR_PHY1_SUSPEND (1 << 6)
> +#define EXYNOS_4212_UPHYPWR_HOST_SUSPEND (1 << 6)
> +#define EXYNOS_4210_UPHYPWR_PHY1_PWR (1 << 7)
> +#define EXYNOS_4212_UPHYPWR_HOST_PWR (1 << 7)
> +#define EXYNOS_4210_UPHYPWR_PHY1_SLEEP (1 << 8)
> +#define EXYNOS_4212_UPHYPWR_HOST_SLEEP (1 << 8)
> +#define EXYNOS_4210_UPHYPWR_PHY1 ( \
> +#define EXYNOS_4212_UPHYPWR_HOST ( \
> + EXYNOS_4210_UPHYPWR_PHY1_SUSPEND | \
> + EXYNOS_4212_UPHYPWR_HOST_SUSPEND | \
> + EXYNOS_4210_UPHYPWR_PHY1_PWR | \
> + EXYNOS_4212_UPHYPWR_HOST_PWR | \
> + EXYNOS_4210_UPHYPWR_PHY1_SLEEP)
> + EXYNOS_4212_UPHYPWR_HOST_SLEEP)
> +
> +
> +#define EXYNOS_4210_UPHYPWR_HSCI0_SUSPEND (1 << 9)
> +#define EXYNOS_4212_UPHYPWR_HSCI0_SUSPEND (1 << 9)
> +#define EXYNOS_4210_UPHYPWR_HSCI0_SLEEP (1 << 10)
> +#define EXYNOS_4212_UPHYPWR_HSCI0_PWR (1 << 10)
> +#define EXYNOS_4210_UPHYPWR_HSCI0 ( \
> +#define EXYNOS_4212_UPHYPWR_HSCI0_SLEEP (1 << 11)
> + EXYNOS_4210_UPHYPWR_HSCI0_SUSPEND | \
> +#define EXYNOS_4212_UPHYPWR_HSCI0 ( \
> + EXYNOS_4210_UPHYPWR_HSCI0_SLEEP)
> + EXYNOS_4212_UPHYPWR_HSCI0_SUSPEND | \
> + EXYNOS_4212_UPHYPWR_HSCI0_PWR | \
> + EXYNOS_4212_UPHYPWR_HSCI0_SLEEP)
> +
> +
> +#define EXYNOS_4210_UPHYPWR_HSCI1_SUSPEND (1 << 11)
> +#define EXYNOS_4212_UPHYPWR_HSCI1_SUSPEND (1 << 12)
> +#define EXYNOS_4210_UPHYPWR_HSCI1_SLEEP (1 << 12)
> +#define EXYNOS_4212_UPHYPWR_HSCI1_PWR (1 << 13)
> +#define EXYNOS_4210_UPHYPWR_HSCI1 ( \
> +#define EXYNOS_4212_UPHYPWR_HSCI1_SLEEP (1 << 14)
> + EXYNOS_4210_UPHYPWR_HSCI1_SUSPEND | \
> +#define EXYNOS_4212_UPHYPWR_HSCI1 ( \
> + EXYNOS_4210_UPHYPWR_HSCI1_SLEEP)
> + EXYNOS_4212_UPHYPWR_HSCI1_SUSPEND | \
> + EXYNOS_4212_UPHYPWR_HSCI1_PWR | \
> + EXYNOS_4212_UPHYPWR_HSCI1_SLEEP)
> +
> +
> +/* PHY clock control */
> +/* PHY clock control */
> +#define EXYNOS_4210_UPHYCLK 0x4
> +#define EXYNOS_4212_UPHYCLK 0x4
> +
> +
> +#define EXYNOS_4210_UPHYCLK_PHYFSEL_MASK (0x3 << 0)
> +#define EXYNOS_4212_UPHYCLK_PHYFSEL_MASK (0x7 << 0)
> +#define EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0)
> +#define EXYNOS_4212_UPHYCLK_PHYFSEL_9MHZ6 (0x0 << 0)
> +#define EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0)
> +#define EXYNOS_4212_UPHYCLK_PHYFSEL_10MHZ (0x1 << 0)
> +#define EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
> +#define EXYNOS_4212_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
> +#define EXYNOS_4212_UPHYCLK_PHYFSEL_19MHZ2 (0x3 << 0)
> +#define EXYNOS_4212_UPHYCLK_PHYFSEL_20MHZ (0x4 << 0)
> +#define EXYNOS_4212_UPHYCLK_PHYFSEL_24MHZ (0x5 << 0)
> +#define EXYNOS_4212_UPHYCLK_PHYFSEL_50MHZ (0x7 << 0)
> +
> +
> +#define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP (0x1 << 2)
> +#define EXYNOS_4212_UPHYCLK_PHY0_ID_PULLUP (0x1 << 3)
> +#define EXYNOS_4210_UPHYCLK_PHY0_COMMON_ON (0x1 << 4)
> +#define EXYNOS_4212_UPHYCLK_PHY0_COMMON_ON (0x1 << 4)
> +#define EXYNOS_4210_UPHYCLK_PHY1_COMMON_ON (0x1 << 7)
> +#define EXYNOS_4212_UPHYCLK_PHY1_COMMON_ON (0x1 << 7)
> +
> +#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_MASK (0x7f << 10)
> +#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_12MHZ (0x24 << 10)
> +#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_15MHZ (0x1c << 10)
> +#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_16MHZ (0x1a << 10)
> +#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_19MHZ2 (0x15 << 10)
> +#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_20MHZ (0x14 << 10)
> +
> +
> +/* PHY reset control */
> +/* PHY reset control */
> +#define EXYNOS_4210_UPHYRST 0x8
> +#define EXYNOS_4212_UPHYRST 0x8
> +
> +
> +#define EXYNOS_4210_URSTCON_PHY0 (1 << 0)
> +#define EXYNOS_4212_URSTCON_DEVICE (1 << 0)
> +#define EXYNOS_4210_URSTCON_OTG_HLINK (1 << 1)
> +#define EXYNOS_4212_URSTCON_OTG_HLINK (1 << 1)
> +#define EXYNOS_4210_URSTCON_OTG_PHYLINK (1 << 2)
> +#define EXYNOS_4212_URSTCON_OTG_PHYLINK (1 << 2)
> +#define EXYNOS_4210_URSTCON_PHY1_ALL (1 << 3)
> +#define EXYNOS_4212_URSTCON_HOST_PHY (1 << 3)
> +#define EXYNOS_4210_URSTCON_PHY1_P0 (1 << 4)
> +#define EXYNOS_4212_URSTCON_PHY1 (1 << 4)
> +#define EXYNOS_4210_URSTCON_PHY1_P1P2 (1 << 5)
> +#define EXYNOS_4212_URSTCON_HSIC0 (1 << 5)
> +#define EXYNOS_4210_URSTCON_HOST_LINK_ALL (1 << 6)
> +#define EXYNOS_4212_URSTCON_HSIC1 (1 << 6)
> +#define EXYNOS_4210_URSTCON_HOST_LINK_P0 (1 << 7)
> +#define EXYNOS_4212_URSTCON_HOST_LINK_ALL (1 << 7)
> +#define EXYNOS_4210_URSTCON_HOST_LINK_P1 (1 << 8)
> +#define EXYNOS_4212_URSTCON_HOST_LINK_P0 (1 << 8)
> +#define EXYNOS_4210_URSTCON_HOST_LINK_P2 (1 << 9)
> +#define EXYNOS_4212_URSTCON_HOST_LINK_P1 (1 << 9)
> +#define EXYNOS_4212_URSTCON_HOST_LINK_P2 (1 << 10)
> +
> +
> +/* Isolation, configured in the power management unit */
> +/* Isolation, configured in the power management unit */
> +#define EXYNOS_4210_USB_ISOL_DEVICE_OFFSET 0x0
> +#define EXYNOS_4212_USB_ISOL_OFFSET 0x0
> +#define EXYNOS_4210_USB_ISOL_DEVICE (1 << 0)
> +#define EXYNOS_4212_USB_ISOL_OTG (1 << 0)
> +#define EXYNOS_4210_USB_ISOL_HOST_OFFSET 0x4
> +#define EXYNOS_4212_USB_ISOL_HSIC0_OFFSET 0x4
> +#define EXYNOS_4210_USB_ISOL_HOST (1 << 0)
> +#define EXYNOS_4212_USB_ISOL_HSIC0 (1 << 0)
> +
> +#define EXYNOS_4212_USB_ISOL_HSIC1_OFFSET 0x8
> +/* USBYPHY1 Floating prevention */
> +#define EXYNOS_4212_USB_ISOL_HSIC1 (1 << 0)
> +#define EXYNOS_4210_UPHY1CON 0x34
> +#define EXYNOS_4210_UPHY1CON_FLOAT_PREVENTION 0x1