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****** START compiling Awaitable:Test():int (MethodHash=29e49f41)

Generating code for Windows x64

OPTIONS: compCodeOpt = BLENDED_CODE

OPTIONS: compDbgCode = false

OPTIONS: compDbgInfo = true

OPTIONS: compDbgEnC = false

OPTIONS: compProcedureSplitting = false

OPTIONS: compProcedureSplittingEH = false

OPTIONS: optimizer should use profile data

IL to import:

IL_0000 16 ldc.i4.0

IL_0001 73 12 00 00 06 newobj 0x6000012

IL_0006 7b 03 00 00 04 ldfld 0x4000003

IL_000b 2a ret

lvaGrabTemp returning 0 (V00 tmp0) (a long lifetime temp) called for OutgoingArgSpace.

Local V00 should not be enregistered because: it is address exposed

; Initial local variable assignments

;

; V00 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"

*************** In compInitDebuggingInfo() for Awaitable:Test():int

getVars() returned cVars = 0, extendOthers = true

info.compStmtOffsetsCount = 0

info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )

*************** In fgFindBasicBlocks() for Awaitable:Test():int

Jump targets:

none

New Basic Block BB01 [0000] created.

BB01 [000..00C)

IL Code Size,Instr 12, 4, Basic Block count 1, Local Variable Num,Ref count 1, 0 for method Awaitable:Test():int

OPTIONS: opts.MinOpts() == false

Basic block list for 'Awaitable:Test():int'

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00C) (return)

-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import

Trees after Pre-import

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00C) (return)

-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..00C) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Starting PHASE Profile incorporation

BBOPT set, but no profile data available (hr=80004001)

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'Awaitable:Test():int'

[ 0] 0 (0x000) ldc.i4.0 0

[ 1] 1 (0x001) newobj

lvaGrabTemp returning 1 (V01 tmp1) called for NewObj constructor temp.

STMT00000 ( 0x000[E-] ... ??? )

[000002] DA--------- * STORE_LCL_VAR struct<Awaitable, 4> V01 tmp1

[000001] ----------- \--* CNS_INT int 0

06000012

In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0

STMT00001 ( ??? ... ??? )

[000004] I-C-G------ * CALL void Awaitable:.ctor(bool):this (exactContextHnd=0x00000000D1FFAB1E)

[000003] ----------- this +--* LCL_ADDR byref V01 tmp1 [+0]

[000000] ----------- arg1 \--* CNS_INT int 0

[ 1] 6 (0x006) ldfld 04000003

[ 1] 11 (0x00b) ret

STMT00002 ( 0x006[--] ... ??? )

[000009] ----------- * RETURN int

[000008] n---------- \--* IND int

[000007] ----------- \--* FIELD_ADDR byref Awaitable:Opts

[000006] ----------- \--* LCL_ADDR byref V01 tmp1 [+0]

*************** Finishing PHASE Importation

Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------

BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]

-----------------------------------------------------------------------------------------------------------------------------------------

BB01 [0000] 1 1 [000..00C) (return) i

-----------------------------------------------------------------------------------------------------------------------------------------

Différences enregistrées

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****** START compiling Awaitable:Test():int (MethodHash=29e49f41)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC  = false
OPTIONS: compProcedureSplitting   = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: optimizer should use profile data
IL to import:
IL_0000  16                ldc.i4.0    
IL_0001  73 12 00 00 06    newobj       0x6000012
IL_0006  7b 03 00 00 04    ldfld        0x4000003
IL_000b  2a                ret

lvaGrabTemp returning 0 (V00 tmp0) (a long lifetime temp) called for OutgoingArgSpace.

Local V00 should not be enregistered because: it is address exposed
; Initial local variable assignments
;
;  V00 OutArgs        struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for Awaitable:Test():int
getVars() returned cVars = 0, extendOthers = true
info.compStmtOffsetsCount    = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Awaitable:Test():int
Jump targets:
  none
New Basic Block BB01 [0000] created.
BB01 [000..00C)
IL Code Size,Instr   12,   4, Basic Block count   1, Local Variable Num,Ref count   1,  0 for method Awaitable:Test():int
OPTIONS: opts.MinOpts() == false
Basic block list for 'Awaitable:Test():int'

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import
Trees after Pre-import

------------ BB01 [000..00C) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'Awaitable:Test():int'
    [ 0]   0 (0x000) ldc.i4.0 0
    [ 1]   1 (0x001) newobj
lvaGrabTemp returning 1 (V01 tmp1) called for NewObj constructor temp.

STMT00000 ( 0x000[E-] ... ??? )
               [000002] DA---------                         *  STORE_LCL_VAR struct<Awaitable, 4> V01 tmp1         
               [000001] -----------                         \--*  CNS_INT   int    0
 06000012
In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0

STMT00001 ( ??? ... ??? )
               [000004] I-C-G------                         *  CALL      void   Awaitable:.ctor(bool):this (exactContextHnd=0x00000000D1FFAB1E)
               [000003] ----------- this                    +--*  LCL_ADDR  byref  V01 tmp1         [+0]
               [000000] ----------- arg1                    \--*  CNS_INT   int    0

[ 1]   6 (0x006) ldfld 04000003
    [ 1]  11 (0x00b) ret

STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000008] n----------                         \--*  IND       int   
               [000007] -----------                            \--*  FIELD_ADDR byref  Awaitable:Opts
               [000006] -----------                               \--*  LCL_ADDR  byref  V01 tmp1         [+0]

*************** Finishing PHASE Importation
Trees after Importation

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00B )
               [000002] DA---------                         *  STORE_LCL_VAR struct<Awaitable, 4> V01 tmp1         
               [000001] -----------                         \--*  CNS_INT   int    0

***** BB01
STMT00001 ( ??? ... ??? )
               [000004] I-C-G------                         *  CALL      void   Awaitable:.ctor(bool):this (exactContextHnd=0x00000000D1FFAB1E)
               [000003] ----------- this                    +--*  LCL_ADDR  byref  V01 tmp1         [+0]
               [000000] ----------- arg1                    \--*  CNS_INT   int    0

***** BB01
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000008] n----------                         \--*  IND       int   
               [000007] -----------                            \--*  FIELD_ADDR byref  Awaitable:Opts
               [000006] -----------                               \--*  LCL_ADDR  byref  V01 tmp1         [+0]

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE Expand patchpoints

-- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Indirect call transform

-- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import [no changes]

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Init [no changes]

*************** Starting PHASE Morph - Inlining
Expanding INLINE_CANDIDATE in statement STMT00001 in BB01:
STMT00001 ( ??? ... ??? )
               [000004] I-C-G------                         *  CALL      void   Awaitable:.ctor(bool):this (exactContextHnd=0x00000000D1FFAB1E)
               [000003] ----------- this                    +--*  LCL_ADDR  byref  V01 tmp1         [+0]
               [000000] ----------- arg1                    \--*  CNS_INT   int    0
thisArg: is a constant or invariant is byref to a struct local
               [000003] -----------                         *  LCL_ADDR  byref  V01 tmp1         [+0]

Argument #1: is a constant or invariant
               [000000] -----------                         *  CNS_INT   int    0

Folding operator with constant nodes into a constant:
               [000010] -----------                         *  CAST      int <- bool <- int
               [000000] -----------                         \--*  CNS_INT   int    0
Bashed to int constant:
               [000010] -----------                         *  CNS_INT   int    0
INLINER: inlineInfo.tokenLookupContextHandle for Awaitable:.ctor(bool):this set to 0x00000000D1FFAB1E:

Invoking compiler for the inlinee method Awaitable:.ctor(bool):this :
IL to import:
IL_0000  03                ldarg.1     
IL_0001  2c 08             brfalse.s    8 (IL_000b)
IL_0003  02                ldarg.0     
IL_0004  17                ldc.i4.1    
IL_0005  7d 03 00 00 04    stfld        0x4000003
IL_000a  2a                ret         
IL_000b  02                ldarg.0     
IL_000c  18                ldc.i4.2    
IL_000d  7d 03 00 00 04    stfld        0x4000003
IL_0012  2a                ret

INLINER impTokenLookupContextHandle for Awaitable:.ctor(bool):this is 0x00000000D1FFAB1E.
*************** In compInitDebuggingInfo() for Awaitable:.ctor(bool):this
info.compStmtOffsetsCount    = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Awaitable:.ctor(bool):this
weight= 16 : state   4 [ ldarg.1 ]
weight= 27 : state  44 [ brfalse.s ]
weight= 10 : state   3 [ ldarg.0 ]
weight= 28 : state  24 [ ldc.i4.1 ]
weight= 31 : state 111 [ stfld ]
weight= 19 : state  42 [ ret ]
weight= 10 : state   3 [ ldarg.0 ]
weight= 34 : state  25 [ ldc.i4.2 ]
weight= 31 : state 111 [ stfld ]
weight= 19 : state  42 [ ret ]
Notify VM instruction set (AVX) must be supported.
Notify VM instruction set (AVX512F) must be supported.

multiplier in instance constructors increased to 1.5.
multiplier in methods of struct increased to 4.5.
Inline candidate is mostly loads and stores.  Multiplier increased to 7.5.
Inline candidate has 1 foldable branches.  Multiplier increased to 11.5.
Inline candidate callsite is boring.  Multiplier increased to 12.8.
calleeNativeSizeEstimate=225
callsiteNativeSizeEstimate=115
benefit multiplier=12.8
threshold=1472
Native estimate for function size is within threshold for inlining 22.5 <= 147.2 (multiplier = 12.8)
Jump targets:
  IL_000b
New Basic Block BB01 [0001] created.
BB01 [000..003)
New Basic Block BB02 [0002] created.
BB02 [003..00B)
New Basic Block BB03 [0003] created.
BB03 [00B..013)
Setting edge weights for BB01 -> BB03 to [0 .. 3.402823e+38]
Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38]
Basic block list for 'Awaitable:.ctor(bool):this'

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001]  1                             1       [000..003)-> BB03 ( cond )                     
BB02 [0002]  1       BB01                  1       [003..00B)        (return)                     
BB03 [0003]  1       BB01                  1       [00B..013)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Inline @[000004] Starting PHASE Pre-import

*************** Inline @[000004] Finishing PHASE Pre-import
Trees after Pre-import

------------ BB01 [000..003) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [003..00B) (return), preds={BB01} succs={}

------------ BB03 [00B..013) (return), preds={BB01} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Inline @[000004] Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)
Computing inlinee profile scale:
   ... no callee profile data, will use non-pgo weight to scale
   ... call site not profiled, will use non-pgo weight to scale
   call site count 100 callee entry count 100 scale 1
Scaling inlinee blocks

*************** Inline @[000004] Finishing PHASE Profile incorporation
Trees after Profile incorporation

------------ BB01 [000..003) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [003..00B) (return), preds={BB01} succs={}

------------ BB03 [00B..013) (return), preds={BB01} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Inline @[000004] Starting PHASE Importation

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'Awaitable:.ctor(bool):this'
    [ 0]   0 (0x000) ldarg.1
    [ 1]   1 (0x001) brfalse.s
Folding operator with constant nodes into a constant:
               [000013] -----------                         *  EQ        int   
               [000011] -----------                         +--*  CNS_INT   int    0
               [000012] -----------                         \--*  CNS_INT   int    0
Bashed to int constant:
               [000013] -----------                         *  CNS_INT   int    1

The conditional jump becomes an unconditional jump to BB03

impImportBlockPending for BB03

Importing BB03 (PC=011) of 'Awaitable:.ctor(bool):this'
    [ 0]  11 (0x00b) ldarg.0
    [ 1]  12 (0x00c) ldc.i4.2 2
    [ 2]  13 (0x00d) stfld 04000003

STMT00003 ( 0x00B[E-] ... ??? ) <- INLRT @ ???
               [000017] nA---------                         *  STOREIND  int   
               [000016] -----------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000014] -----------                         |  \--*  LCL_ADDR  byref  V01 tmp1         [+0]
               [000015] -----------                         \--*  CNS_INT   int    2

[ 0]  18 (0x012) ret
** Note: inlinee IL was partially imported -- imported 8 of 19 bytes of method IL

*************** Inline @[000004] Finishing PHASE Importation
Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001]  1                             1       [000..003)-> BB03 (always)                     i 
BB02 [0002]  0                             1       [003..00B)        (return)                     
BB03 [0003]  1       BB01                  1       [00B..013)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..003) -> BB03 (always), preds={} succs={BB03}

------------ BB02 [003..00B) (return), preds={} succs={}

------------ BB03 [00B..013) (return), preds={BB01} succs={}

***** BB03
STMT00003 ( 0x00B[E-] ... ??? ) <- INLRT @ ???
               [000017] nA---------                         *  STOREIND  int   
               [000016] -----------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000014] -----------                         |  \--*  LCL_ADDR  byref  V01 tmp1         [+0]
               [000015] -----------                         \--*  CNS_INT   int    2

*************** Inline @[000004] Starting PHASE Expand patchpoints

-- no patchpoints to transform

*************** Inline @[000004] Finishing PHASE Expand patchpoints [no changes]

*************** Inline @[000004] Starting PHASE Indirect call transform

-- no candidates to transform

*************** Inline @[000004] Finishing PHASE Indirect call transform [no changes]

*************** Inline @[000004] Starting PHASE Post-import
BB02 was not imported, marking as removed (0)

Renumbering the basic blocks for fgPostImportationCleanup

*************** Before renumbering the basic blocks

***************  Exception Handling table is empty
Renumber BB03 to BB02

*************** After renumbering the basic blocks

***************  Exception Handling table is empty

New BlockSet epoch 1, # of blocks (including unused BB00): 3, bitset array size: 1 (short)

*************** Inline @[000004] Finishing PHASE Post-import
Trees after Post-import

------------ BB01 [000..003) -> BB02 (always), preds={} succs={BB02}

------------ BB02 [00B..013) (return), preds={BB01} succs={}

***** BB02
STMT00003 ( 0x00B[E-] ... ??? ) <- INLRT @ ???
               [000017] nA---------                         *  STOREIND  int   
               [000016] -----------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000014] -----------                         |  \--*  LCL_ADDR  byref  V01 tmp1         [+0]
               [000015] -----------                         \--*  CNS_INT   int    2

----------- Statements (and blocks) added due to the inlining of call [000004] -----------

Arguments setup:

Inlinee method body:New Basic Block BB02 [0004] created.
Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38]

Convert bbJumpKind of BB04 to BBJ_NONE
Setting edge weights for BB04 -> BB02 to [0 .. 3.402823e+38]
Setting edge weights for BB01 -> BB03 to [0 .. 3.402823e+38]
fgInlineAppendStatements: no gc ref inline locals.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB03 [0001]  1       BB01                  1       [000..000)-> BB04 (always)                     i internal 
BB04 [0003]  1       BB03                  1       [000..000)                                     i internal 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB03 [000..000) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB04 [000..000), preds={BB03} succs={BB02}

***** BB04
STMT00003 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ ???
               [000017] nA---------                         *  STOREIND  int   
               [000016] -----------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000014] -----------                         |  \--*  LCL_ADDR  byref  V01 tmp1         [+0]
               [000015] -----------                         \--*  CNS_INT   int    2

-------------------------------------------------------------------------------------------------------------------
Successfully inlined Awaitable:.ctor(bool):this (19 IL bytes) (depth 1) [profitable inline]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'Awaitable:Test():int' calling 'Awaitable:.ctor(bool):this'
INLINER: during 'fgInline' result 'success' reason 'profitable inline'
**************** Inline Tree

Inlines into 06000013 [via ExtendedDefaultPolicy] Awaitable:Test():int:
  [INL01 IL=0001 TR=000004 06000012] [INLINED: call site: profitable inline] Awaitable:.ctor(bool):this
Budget: initialTime=96, finalTime=98, initialBudget=960, currentBudget=960
Budget: initialSize=404, finalSize=514

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..006)                                     i 
BB03 [0001]  1       BB01                  1       [000..000)-> BB04 (always)                     i internal 
BB04 [0003]  1       BB03                  1       [000..000)                                     i internal 
BB02 [0004]  1       BB04                  1       [006..00C)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB04 to BB03
Renumber BB02 to BB04

*************** After renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..006)                                     i 
BB02 [0001]  1       BB01                  1       [000..000)-> BB03 (always)                     i internal 
BB03 [0003]  1       BB02                  1       [000..000)                                     i internal 
BB04 [0004]  1       BB03                  1       [006..00C)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

New BlockSet epoch 2, # of blocks (including unused BB00): 5, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..006)                                     i 
BB02 [0001]  1       BB01                  1       [000..000)-> BB03 (always)                     i internal 
BB03 [0003]  1       BB02                  1       [000..000)                                     i internal 
BB04 [0004]  1       BB03                  1       [006..00C)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..006), preds={} succs={BB02}

------------ BB02 [000..000) -> BB03 (always), preds={BB01} succs={BB03}

------------ BB03 [000..000), preds={BB02} succs={BB04}

***** BB03
STMT00003 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ ???
               [000017] nA---------                         *  STOREIND  int   
               [000016] -----------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000014] -----------                         |  \--*  LCL_ADDR  byref  V01 tmp1         [+0]
               [000015] -----------                         \--*  CNS_INT   int    2

------------ BB04 [006..00C) (return), preds={BB03} succs={}

***** BB04
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000008] n----------                         \--*  IND       int   
               [000007] -----------                            \--*  FIELD_ADDR byref  Awaitable:Opts
               [000006] -----------                               \--*  LCL_ADDR  byref  V01 tmp1         [+0]

*************** Starting PHASE Allocate Objects
no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..006)                                     i 
BB02 [0001]  1       BB01                  1       [000..000)-> BB03 (always)                     i internal 
BB03 [0003]  1       BB02                  1       [000..000)                                     i internal 
BB04 [0004]  1       BB03                  1       [006..00C)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks [no changes]

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally
No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Tail merge

*************** Finishing PHASE Tail merge [no changes]

*************** Starting PHASE Merge throw blocks

*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.

*************** Finishing PHASE Merge throw blocks [no changes]

*************** Starting PHASE Update flow graph early pass

Compacting BB02 into BB01:
*************** In fgDebugCheckBBlist

Removing unconditional jump to next block (BB01 -> BB03) (converted BB01 to fall-through)

Compacting BB03 into BB01:
*************** In fgDebugCheckBBlist

Compacting BB04 into BB01:
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Update flow graph early pass
Trees after Update flow graph early pass

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00003 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ ???
               [000017] nA---------                         *  STOREIND  int   
               [000016] -----------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000014] -----------                         |  \--*  LCL_ADDR  byref  V01 tmp1         [+0]
               [000015] -----------                         \--*  CNS_INT   int    2

*************** Starting PHASE Morph - Promote Structs

lvaTable before fgPromoteStructs
; Initial local variable assignments
;
;  V00 OutArgs        struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V01 tmp1           struct <Awaitable, 4> ld-addr-op "NewObj constructor temp"
  struct promotion of V00 is disabled because it has already been marked address exposed

Promoting struct local V01 (Awaitable):
lvaGrabTemp returning 2 (V02 tmp2) (a long lifetime temp) called for field V01.Opts (fldOffset=0x0).

lvaTable after fgPromoteStructs
; Initial local variable assignments
;
;  V00 OutArgs        struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V01 tmp1           struct <Awaitable, 4> ld-addr-op "NewObj constructor temp"
;  V02 tmp2              int  V01.Opts(offs=0x00) P-INDEP "field V01.Opts (fldOffset=0x0)"

*************** Finishing PHASE Morph - Promote Structs
Trees after Morph - Promote Structs

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00B )
               [000002] DA---------                         *  STORE_LCL_VAR struct<Awaitable, 4>(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V02 tmp2         
               [000001] -----------                         \--*  CNS_INT   int    0

***** BB01
STMT00003 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ ???
               [000017] nA---------                         *  STOREIND  int   
               [000016] -----------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000014] -----------                         |  \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                            |     *    int    V01.Awaitable:Opts (offs=0x00) -> V02 tmp2         
               [000015] -----------                         \--*  CNS_INT   int    2

*************** Starting PHASE Morph - Structs/AddrExp
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x00B )
               [000002] DA---------                         *  STORE_LCL_VAR struct<Awaitable, 4>(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V02 tmp2         
               [000001] -----------                         \--*  CNS_INT   int    0

LocalAddressVisitor visiting statement:
STMT00003 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ ???
               [000017] nA---------                         *  STOREIND  int   
               [000016] -----------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000014] -----------                         |  \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                            |     *    int    V01.Awaitable:Opts (offs=0x00) -> V02 tmp2         
               [000015] -----------                         \--*  CNS_INT   int    2
Replacing the field in promoted struct with local var V02
LocalAddressVisitor modified statement:
STMT00003 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ ???
               [000017] DA---------                         *  STORE_LCL_VAR int    V02 tmp2         
               [000015] -----------                         \--*  CNS_INT   int    2

LocalAddressVisitor visiting statement:
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000008] n----------                         \--*  IND       int   
               [000007] -----------                            \--*  FIELD_ADDR byref  Awaitable:Opts
               [000006] -----------                               \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                                     *    int    V01.Awaitable:Opts (offs=0x00) -> V02 tmp2         
Replacing the field in promoted struct with local var V02
LocalAddressVisitor modified statement:
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000008] -----------                         \--*  LCL_VAR   int    V02 tmp2

*************** Finishing PHASE Morph - Structs/AddrExp
Trees after Morph - Structs/AddrExp

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00003 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ ???
               [000017] DA---------                         *  STORE_LCL_VAR int    V02 tmp2         
               [000015] -----------                         \--*  CNS_INT   int    2

***** BB01
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000008] -----------                         \--*  LCL_VAR   int    V02 tmp2

*************** Starting PHASE Early liveness

Local V00 should not be enregistered because: struct size does not match reg size
Tracked variable (1 out of 3) table:
V02 tmp2          [   int]: refCnt =    3, refCntWtd =   0

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={   }
     DEF(1)={V02}

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (0)={}
     OUT(0)={}

Store [000002] is dead and has no side effects, removing statement

removing useless STMT00000 ( 0x000[E-] ... 0x00B )
               [000002] DA---------                         *  STORE_LCL_VAR struct<Awaitable, 4>(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V02 tmp2         
               [000001] -----------                         \--*  CNS_INT   int    0
 from BB01

*************** Finishing PHASE Early liveness
Trees after Early liveness

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000008] -----------                         \--*  LCL_VAR   int    V02 tmp2          (last use)

*************** Starting PHASE Physical promotion

*************** Finishing PHASE Physical promotion [no changes]

*************** Starting PHASE Forward Substitution

===> BB01
    [000017]:  [000008] is last use of [000017] (V02)  -- fwd subbing [000015]; new next stmt is
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000015] -----------                         \--*  CNS_INT   int    2

removing useless STMT00003 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ ???
               [000017] DA---------                         *  STORE_LCL_VAR int    V02 tmp2         
               [000015] -----------                         \--*  CNS_INT   int    2
 from BB01

*************** Finishing PHASE Forward Substitution
Trees after Forward Substitution

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000015] -----------                         \--*  CNS_INT   int    2

*************** Starting PHASE Morph - ByRefs

*************** Finishing PHASE Morph - ByRefs [no changes]

*************** Starting PHASE Morph - Global

*************** In fgMorphBlocks()

Morphing BB01 of 'Awaitable:Test():int'

fgMorphTree BB01, STMT00002 (before)
               [000009] -----------                         *  RETURN    int   
               [000015] -----------                         \--*  CNS_INT   int    2

*************** In fgMarkDemotedImplicitByRefArgs()

*************** Finishing PHASE Morph - Global
Trees after Morph - Global

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----+-----                         *  RETURN    int   
               [000015] -----+-----                         \--*  CNS_INT   int    2

*************** Starting PHASE GS Cookie
No GS security needed

*************** Finishing PHASE GS Cookie [no changes]

*************** Starting PHASE Compute edge weights (1, false)

-- no profile data, so using default called count
 -- not optimizing or no profile data, so not computing edge weights

*************** Finishing PHASE Compute edge weights (1, false) [no changes]

*************** Starting PHASE Create EH funclets

*************** Finishing PHASE Create EH funclets [no changes]

*************** Starting PHASE Invert loops

*************** Before renumbering the basic blocks

***************  Exception Handling table is empty
=============== No blocks renumbered!

New BlockSet epoch 3, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** Finishing PHASE Invert loops
Trees after Invert loops

------------ BB01 [000..00C) (return), preds={} succs={}

*************** Starting PHASE Optimize control flow

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

*************** In fgDebugCheckBBlist

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize control flow
Trees after Optimize control flow

------------ BB01 [000..00C) (return), preds={} succs={}

*************** Starting PHASE Post-morph tail merge

*************** Finishing PHASE Post-morph tail merge [no changes]

*************** Starting PHASE Compute blocks reachability
Return blocks: BB01

Renumbering the basic blocks for fgComputeReachability pass #1

*************** Before renumbering the basic blocks

***************  Exception Handling table is empty
=============== No blocks renumbered!
Enter blocks: BB01

Dominator computation start blocks (those blocks with no incoming edges):
BB01

After computing reachability sets:
------------------------------------------------
BBnum  Reachable by 
------------------------------------------------
BB01 : BB01 
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
------------------------------------------------
BBnum  Dominated by
------------------------------------------------
BB01:  BB01

Inside fgBuildDomTree

After computing the Dominance Tree:

After numbering the dominator tree:
BB01: pre=01, post=01

*************** Finishing PHASE Compute blocks reachability [no changes]

*************** Starting PHASE Set block weights

*************** Finishing PHASE Set block weights [no changes]

*************** Starting PHASE Find loops
*************** In optFindLoops()
*************** In optMarkLoopHeads()
0 loop heads marked

*************** Finishing PHASE Find loops
Trees after Find loops

------------ BB01 [000..00C) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Clone loops

*************** In optCloneLoops()
  No loops to clone

*************** Finishing PHASE Clone loops [no changes]

*************** Starting PHASE Unroll loops

*************** Finishing PHASE Unroll loops [no changes]

*************** Starting PHASE Clear loop info

*************** Finishing PHASE Clear loop info [no changes]

*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function

*************** Finishing PHASE Morph array ops [no changes]

*************** Starting PHASE Mark local vars

*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** marking local variables in block BB01 (weight=1)
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----+-----                         *  RETURN    int   
               [000015] -----+-----                         \--*  CNS_INT   int    2

*** lvaComputeRefCounts -- implicit counts ***

*************** Finishing PHASE Mark local vars [no changes]

*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()

*************** Finishing PHASE Find oper order
Trees after Find oper order

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x006[--] ... ??? )
     (  2,  2) [000009] -----------                         *  RETURN    int   
     (  1,  1) [000015] -----------                         \--*  CNS_INT   int    2

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has    2 tree nodes

*************** Finishing PHASE Set block order
Trees after Set block order

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x006[--] ... ??? )
N002 (  2,  2) [000009] -----------                         *  RETURN    int   
N001 (  1,  1) [000015] -----------                         \--*  CNS_INT   int    2

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 2.

***************  Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]

Inside fgBuildDomTree

After computing the Dominance Tree:

*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit

Local V00 should not be enregistered because: struct size does not match reg size
Tracked variable (0 out of 3) table:

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={}
     DEF(0)={}

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (0)={}
     OUT(0)={}

*************** In optRemoveRedundantZeroInits()
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()

*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation

------------ BB01 [000..00C) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
SSA checks completed successfully
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method

*************** Finishing PHASE Early Value Propagation [no changes]

*************** Starting PHASE Do value numbering

*************** In fgValueNumber()
Memory Initial Value in BB01 is: $80
The SSA definition for ByrefExposed (#1) at start of BB01 is $80 {InitVal($40)}
The SSA definition for GcHeap (#1) at start of BB01 is $80 {InitVal($40)}

***** BB01, STMT00002(before)
N002 (  2,  2) [000009] -----------                         *  RETURN    int   
N001 (  1,  1) [000015] -----------                         \--*  CNS_INT   int    2

N001 [000015]   CNS_INT   2 => $41 {IntCns 2}
N002 [000009]   RETURN    => $VN.Void

***** BB01, STMT00002(after)
N002 (  2,  2) [000009] -----------                         *  RETURN    int    $VN.Void
N001 (  1,  1) [000015] -----------                         \--*  CNS_INT   int    2 $41

finish(BB01).

*************** Finishing PHASE Do value numbering
Trees after Do value numbering

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00002 ( 0x006[--] ... ??? )
N002 (  2,  2) [000009] -----------                         *  RETURN    int    $VN.Void
N001 (  1,  1) [000015] -----------                         \--*  CNS_INT   int    2 $41

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
SSA checks completed successfully
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Hoist loop code

No loops; no hoisting

*************** Finishing PHASE Hoist loop code [no changes]

*************** Starting PHASE VN based copy prop
Copy Assertion for BB01
  curSsaName stack: { }

*************** Finishing PHASE VN based copy prop [no changes]

*************** Starting PHASE Redundant branch opts

*************** Finishing PHASE Redundant branch opts [no changes]

*************** Starting PHASE Optimize Valnum CSEs

*************** Finishing PHASE Optimize Valnum CSEs
Trees after Optimize Valnum CSEs

------------ BB01 [000..00C) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
SSA checks completed successfully
*************** In fgDebugCheckLoopTable
Disabling SSA checking before assertion prop

*************** Starting PHASE Assertion prop

*************** Finishing PHASE Assertion prop [no changes]

*************** Starting PHASE Optimize index checks

*************** Finishing PHASE Optimize index checks [no changes]

*************** Starting PHASE VN-based dead store removal

*************** Finishing PHASE VN-based dead store removal [no changes]

*************** Starting PHASE Stress gtSplitTree

*************** Finishing PHASE Stress gtSplitTree [no changes]

*************** Starting PHASE Expand runtime lookups

*************** Finishing PHASE Expand runtime lookups [no changes]

*************** Starting PHASE Expand static init
Nothing to expand.

*************** Finishing PHASE Expand static init [no changes]

*************** Starting PHASE Expand TLS access
Nothing to expand.

*************** Finishing PHASE Expand TLS access [no changes]

*************** Starting PHASE Insert GC Polls

*************** Finishing PHASE Insert GC Polls [no changes]

*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()

optimized 0 BBJ_COND cases, 0 BBJ_RETURN cases in 1 passes

*************** Finishing PHASE Optimize bools [no changes]

*************** Starting PHASE If conversion

*************** Finishing PHASE If conversion [no changes]

*************** Starting PHASE Optimize layout

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

*************** In fgDebugCheckBBlist

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize layout
Trees after Optimize layout

------------ BB01 [000..00C) (return), preds={} succs={}

*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method

*************** Finishing PHASE Determine first cold block [no changes]

*************** Starting PHASE Rationalize IR

*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR

------------ BB01 [000..00C) (return), preds={} succs={}
               [000019] -----------                            IL_OFFSET void   INLRT @ 0x006[--]
N001 (  1,  1) [000015] -----------                   t15 =    CNS_INT   int    2 $41
                                                            /--*  t15    int    
N002 (  2,  2) [000009] -----------                         *  RETURN    int    $VN.Void

*************** Starting PHASE Do 'simple' lowering

*************** Finishing PHASE Do 'simple' lowering [no changes]

*************** Starting PHASE Lowering nodeinfo
lowering GT_RETURN
N002 (  2,  2) [000009] -----------                         *  RETURN    int    $VN.Void
============Lower has completed modifying nodes.

-------------------------------------------------------------------------------------------------------------------

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** lvaComputeRefCounts -- implicit counts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
;  V00 OutArgs        struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V01 tmp1           struct <Awaitable, 4> ld-addr-op "NewObj constructor temp"
;  V02 tmp2              int  V01.Opts(offs=0x00) P-INDEP "field V01.Opts (fldOffset=0x0)"
In fgLocalVarLivenessInit

Local V00 should not be enregistered because: struct size does not match reg size
Tracked variable (0 out of 3) table:

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={}
     DEF(0)={}

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (0)={}
     OUT(0)={}

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

*************** In fgDebugCheckBBlist

*************** In fgRemoveDeadBlocks()
Removing unreachable blocks for fgRemoveDeadBlocks iteration #1
*************** In fgDebugCheckBBlist

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** lvaComputeRefCounts -- implicit counts ***

*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo

*************** Starting PHASE Calculate stack level slots

*************** Finishing PHASE Calculate stack level slots [no changes]

*************** Starting PHASE Linear scan register alloc
Clearing modified regs.

buildIntervals ========

-----------------
LIVENESS:
-----------------
BB01
use: {}
def: {}
 in: {}
out: {}

FP callee save candidate vars: None

floatVarCount = 0; hasLoops = false, singleExit = true
TUPLE STYLE DUMP BEFORE LSRA
Start LSRA Block Sequence: 
Current block: BB01
Final LSRA Block Sequence:
BB01 (  1   )

BB01 [000..00C) (return), preds={} succs={}
=====
  N000.                    IL_OFFSET INLRT @ 0x006[--]
  N001. t15             =  CNS_INT   2
  N002.                    RETURN   ; t15

buildIntervals second part ========

NEW BLOCK BB01
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N002 (???,???) [000019] -----------                         *  IL_OFFSET void   INLRT @ 0x006[--] REG NA

DefList: {  }
N004 (  1,  1) [000015] -----------                         *  CNS_INT   int    2 REG NA $41
Interval  0: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N004.t15. CNS_INT }
N006 (  2,  2) [000009] -----------                         *  RETURN    int    REG NA $VN.Void
<RefPosition #2   @6   RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #3   @6   RefTypeUse <Ivl:0> BB01 regmask=[rax] minReg=1 last fixed wt=100.00>

Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval  0: int (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[rax]

Linear scan intervals after buildIntervals:
Interval  0: int (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[rax]

*************** In LinearScan::allocateRegisters()

Linear scan intervals before allocateRegisters:
Interval  0: int (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[rax]

Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.

----------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LoRP#Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
----------------------------------------+----+----+----+----+----+----+----+----+----+
                                        |    |    |    |    |    |    |    |    |    |
         0.#0 BB1 PredBB0               |    |    |    |    |    |    |    |    |    |
[000015] 5.#1 C0   Def    Alloc    rax  |C0 a|    |    |    |    |    |    |    |    |
[000009] 6.#2 rax  Fixd   Keep     rax  |C0 a|    |    |    |    |    |    |    |    |
         6.#3 C0   Use *  Keep     rax  |C0 i|    |    |    |    |    |    |    |    |

------------
REFPOSITIONS AFTER ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #2   @6   RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #3   @6   RefTypeUse <Ivl:0> BB01 regmask=[rax] minReg=1 last fixed wt=100.00>
Active intervals at end of allocation:

Trees after linear scan register allocator (LSRA)

------------ BB01 [000..00C) (return), preds={} succs={}
N002 (???,???) [000019] -----------                            IL_OFFSET void   INLRT @ 0x006[--] REG NA
N004 (  1,  1) [000015] -----------                   t15 =    CNS_INT   int    2 REG rax $41
                                                            /--*  t15    int    
N006 (  2,  2) [000009] -----------                         *  RETURN    int    REG NA $VN.Void

-------------------------------------------------------------------------------------------------------------------

Final allocation
----------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LoRP#Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
----------------------------------------+----+----+----+----+----+----+----+----+----+
         0.#0 BB1 PredBB0               |    |    |    |    |    |    |    |    |    |
[000015] 5.#1 C0   Def    Alloc    rax  |C0 a|    |    |    |    |    |    |    |    |
[000009] 6.#2 rax  Fixd   Keep     rax  |C0 a|    |    |    |    |    |    |    |    |
         6.#3 C0   Use *  Keep     rax  |C0 i|    |    |    |    |    |    |    |    |

Recording the maximum number of concurrent spills:

----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars:  0
Total Reg Cand Vars: 0
Total number of Intervals: 0
Total number of RefPositions: 3
Total Number of spill temps created: 0
..........
..........
Total SpillCount : 0   Weighted: 0.000000
Total CopyReg : 0   Weighted: 0.000000
Total ResolutionMovs : 0   Weighted: 0.000000
Total SplitEdges : 0   Weighted: 0.000000
..........

TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: 
BB01 [000..00C) (return), preds={} succs={}
=====
  N002.                    IL_OFFSET INLRT @ 0x006[--]
  N004. rax             =  CNS_INT   2
  N006.                    RETURN   ; rax

*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc

*************** Starting PHASE Place 'align' instructions

*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()

*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Modified regs: [rax]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
--- delta bump 8 for RA
--- delta bump 0 for RSP frame
--- virtual stack offset to actual stack offset delta is 8
-- V00 was 0, now 8
; Final local variable assignments
;
;# V00 OutArgs      [V00    ] (  1,  1   )  struct ( 0) [rsp+00H]   do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V01 tmp1         [V01    ] (  0,  0   )  struct ( 8) zero-ref    ld-addr-op "NewObj constructor temp"
;* V02 tmp2         [V02    ] (  0,  0   )     int  ->  zero-ref    V01.Opts(offs=0x00) P-INDEP "field V01.Opts (fldOffset=0x0)"
;
; Lcl frame size = 0
Created:
      G_M24766_IG02:        ; offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
  BB01 : first block
*************** After genMarkLabelsForCodegen()

=============== Generating BB01 [000..00C) (return), preds={} succs={} flags=0x00000000.00020011: i label LIR 
BB01 IN (0)={}
     OUT(0)={}

Liveness not changing: 0000000000000000 {}
							Live regs: (unchanged) 0000 {}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 0000 {}

L_M24766_BB01:
Label: G_M24766_IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Added IP mapping: 0x0006 (G_M24766_IG02,ins#0,ofs#0) label
Generating: N002 (???,???) [000019] -----------                            IL_OFFSET void   INLRT @ 0x006[--] REG NA
Generating: N004 (  1,  1) [000015] -----------                   t15 =    CNS_INT   int    2 REG rax $41
Mapped BB01 to G_M24766_IG02
IN0001:        mov      eax, 2
                                                                        /--*  t15    int    
Generating: N006 (  2,  2) [000009] -----------                         *  RETURN    int    REG NA $VN.Void
Added IP mapping: EPILOG (G_M24766_IG02,ins#1,ofs#5) label
Reserving epilog IG for block BB01
Saved:
      G_M24766_IG02:        ; offs=000000H, size=0005H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
Created:
      G_M24766_IG03:        ; offs=000005H, size=0000H, bbWeight=1, gcrefRegs=0000 {}
*************** After placeholder IG creation
G_M24766_IG01:        ; func=00, offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M24766_IG02:        ; offs=000000H, size=0005H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M24766_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}

Variable Live Range History Dump for BB01
..None..
Liveness not changing: 0000000000000000 {}

# compCycleEstimate =      2, compSizeEstimate =     2 Awaitable:Test():int
; Final local variable assignments
;
;# V00 OutArgs      [V00    ] (  1,  1   )  struct ( 0) [rsp+00H]   do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V01 tmp1         [V01    ] (  0,  0   )  struct ( 8) zero-ref    ld-addr-op "NewObj constructor temp"
;* V02 tmp2         [V02    ] (  0,  0   )     int  ->  zero-ref    V01.Opts(offs=0x00) P-INDEP "field V01.Opts (fldOffset=0x0)"
;
; Lcl frame size = 0
*************** Before prolog / epilog generation
G_M24766_IG01:        ; func=00, offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M24766_IG02:        ; offs=000000H, size=0005H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M24766_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M24766_IG01,ins#0,ofs#0) label

__prolog:
*************** In genEnregisterIncomingStackArgs()

Saved:
      G_M24766_IG01:        ; offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc
*************** In genFnEpilog()

__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {}
IN0002:        ret      
Saved:
      G_M24766_IG03:        ; offs=000005H, size=0001H, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M24766_IG01:        ; func=00, offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M24766_IG02:        ; offs=000000H, size=0005H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M24766_IG03:        ; offs=000005H, size=0001H, bbWeight=1, epilog, nogc, extend
*************** In emitJumpDistBind()
Emitter Jump List:
  total jump count: 0

*************** Finishing PHASE Generate code

*************** Starting PHASE Emit code

Hot  code size = 0x6 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x4)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)

***************************************************************************
Instructions as they come out of the scheduler

G_M24766_IG01:        ; offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
						;; size=0 bbWeight=1 PerfScore 0.00
G_M24766_IG02:        ; offs=000000H, size=0005H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
IN0001: 000000 mov      eax, 2
						;; size=5 bbWeight=1 PerfScore 0.25
G_M24766_IG03:        ; offs=000005H, size=0001H, bbWeight=1, epilog, nogc, extend
IN0002: 000005 ret      
						;; size=1 bbWeight=1 PerfScore 1.00Allocated method code size =    6 , actual size =    6, unused size =    0

; Total bytes of code 6, prolog size 0, PerfScore 1.85, instruction count 2, allocated bytes for code 6 (MethodHash=29e49f41) for method Awaitable:Test():int
; ============================================================

*************** After end code gen, before unwindEmit()
G_M24766_IG01:        ; func=00, offs=000000H, size=0000H, bbWeight=1, PerfScore 0.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M24766_IG02:        ; offs=000000H, size=0005H, bbWeight=1, PerfScore 0.25, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref

IN0001: 000000 mov      eax, 2

G_M24766_IG03:        ; offs=000005H, size=0001H, bbWeight=1, PerfScore 1.00, epilog, nogc, extend

IN0002: 000005 ret

*************** Finishing PHASE Emit code

*************** Starting PHASE Emit GC+EH tables
Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0xd1ffab1e (not in unwind data)
  Version           : 1
  Flags             : 0x00
  SizeOfProlog      : 0x00
  CountOfUnwindCodes: 0
  FrameRegister     : none (0)
  FrameOffset       : N/A (no FrameRegister) (Value=0)
  UnwindCodes       :
allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x6, unwindSize=0x4, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 2
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs EPILOG : 0x00000005 ( STACK_EMPTY )

*************** In genSetScopeInfo()
VarLocInfo count is 0
; Variable debug info: 0 live ranges, 0 vars for method Awaitable:Test():int
*************** In gcInfoBlockHdrSave()
Set code length to 6.
Set ReturnKind to Scalar.
Set Outgoing stack arg area size to 0.
Defining 0 call sites:

*************** Finishing PHASE Emit GC+EH tables
Method code size: 6

Allocations for Awaitable:Test():int (MethodHash=29e49f41)
count:        258, size:      39273, max =       5288
allocateMemory:      65536, nraUsed:      44464

Alloc'd bytes by kind:
                  kind |       size |     pct
  ---------------------+------------+--------
         AssertionProp |       6500 |  16.55%
               ASTNode |       3008 |   7.66%
              InstDesc |       2096 |   5.34%
              ImpStack |        384 |   0.98%
            BasicBlock |       2040 |   5.19%
              CallArgs |        160 |   0.41%
              FlowEdge |        240 |   0.61%
     TreeStatementList |          0 |   0.00%
               SiScope |          0 |   0.00%
       DominatorMemory |         96 |   0.24%
                  LSRA |       6744 |  17.17%
         LSRA_Interval |         80 |   0.20%
      LSRA_RefPosition |        320 |   0.81%
          Reachability |         40 |   0.10%
                   SSA |         48 |   0.12%
           ValueNumber |       3010 |   7.66%
              LvaTable |       1548 |   3.94%
            UnwindInfo |          0 |   0.00%
                hashBv |         40 |   0.10%
                bitset |         32 |   0.08%
          FixedBitVect |         32 |   0.08%
               Generic |       1080 |   2.75%
   LocalAddressVisitor |          0 |   0.00%
         FieldSeqStore |          0 |   0.00%
          MemorySsaMap |          0 |   0.00%
          MemoryPhiArg |          0 |   0.00%
                   CSE |       1024 |   2.61%
                    GC |       1224 |   3.12%
       CorTailCallInfo |          0 |   0.00%
              Inlining |       1344 |   3.42%
            ArrayStack |          0 |   0.00%
             DebugInfo |        144 |   0.37%
             DebugOnly |       6551 |  16.68%
               Codegen |       1224 |   3.12%
               LoopOpt |          0 |   0.00%
             LoopClone |          0 |   0.00%
             LoopHoist |          0 |   0.00%
               Unknown |         96 |   0.24%
            RangeCheck |          0 |   0.00%
              CopyProp |          0 |   0.00%
             Promotion |          0 |   0.00%
           SideEffects |          0 |   0.00%
       ObjectAllocator |          0 |   0.00%
    VariableLiveRanges |         40 |   0.10%
           ClassLayout |        128 |   0.33%
       TailMergeThrows |          0 |   0.00%
             EarlyProp |          0 |   0.00%
              ZeroInit |          0 |   0.00%
                   Pgo |          0 |   0.00%

****** DONE compiling Awaitable:Test():int

Texte modifié

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lvaGrabTemp returning 0 (V00 tmp0) (a long lifetime temp) called for OutgoingArgSpace.

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import
Trees after Pre-import

------------ BB01 [000..00C) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'Awaitable:Test():int'
    [ 0]   0 (0x000) ldc.i4.0 0
    [ 1]   1 (0x001) newobj
lvaGrabTemp returning 1 (V01 tmp1) called for NewObj constructor temp.

[ 1]   6 (0x006) ldfld 04000003
    [ 1]  11 (0x00b) ret

*************** Finishing PHASE Importation
Trees after Importation

------------ BB01 [000..00C) (return), preds={} succs={}

*************** Starting PHASE Expand patchpoints

-- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Indirect call transform

-- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import [no changes]

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Init [no changes]

Argument #1: is a constant or invariant
               [000000] -----------                         *  CNS_INT   int    0

Invoking compiler for the inlinee method Awaitable:.ctor(bool):this :
IL to import:
IL_0000  02                ldarg.0     
IL_0001  03                ldarg.1     
IL_0002  2d 03             brtrue.s     3 (IL_0007)
IL_0004  18                ldc.i4.2    
IL_0005  2b 01             br.s         1 (IL_0008)
IL_0007  17                ldc.i4.1    
IL_0008  7d 03 00 00 04    stfld        0x4000003
IL_000d  2a                ret

INLINER impTokenLookupContextHandle for Awaitable:.ctor(bool):this is 0x00000000D1FFAB1E.
*************** In compInitDebuggingInfo() for Awaitable:.ctor(bool):this
info.compStmtOffsetsCount    = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Awaitable:.ctor(bool):this
Jump targets:
  IL_0007
  IL_0008
New Basic Block BB01 [0001] created.
BB01 [000..004)
New Basic Block BB02 [0002] created.
BB02 [004..007)
New Basic Block BB03 [0003] created.
BB03 [007..008)
New Basic Block BB04 [0004] created.
BB04 [008..00E)
Setting edge weights for BB01 -> BB03 to [0 .. 3.402823e+38]
Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38]
Setting edge weights for BB02 -> BB04 to [0 .. 3.402823e+38]
Setting edge weights for BB03 -> BB04 to [0 .. 3.402823e+38]
Basic block list for 'Awaitable:.ctor(bool):this'

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001]  1                             1       [000..004)-> BB03 ( cond )                     
BB02 [0002]  1       BB01                  1       [004..007)-> BB04 (always)                     
BB03 [0003]  1       BB01                  1       [007..008)                                     
BB04 [0004]  2       BB02,BB03             1       [008..00E)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Inline @[000004] Starting PHASE Pre-import

*************** Inline @[000004] Finishing PHASE Pre-import
Trees after Pre-import

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001]  1                             1       [000..004)-> BB03 ( cond )                     
BB02 [0002]  1       BB01                  1       [004..007)-> BB04 (always)                     
BB03 [0003]  1       BB01                  1       [007..008)                                     
BB04 [0004]  2       BB02,BB03             1       [008..00E)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [004..007) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [007..008), preds={BB01} succs={BB04}

------------ BB04 [008..00E) (return), preds={BB02,BB03} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Inline @[000004] Finishing PHASE Profile incorporation
Trees after Profile incorporation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001]  1                             1       [000..004)-> BB03 ( cond )                     
BB02 [0002]  1       BB01                  1       [004..007)-> BB04 (always)                     
BB03 [0003]  1       BB01                  1       [007..008)                                     
BB04 [0004]  2       BB02,BB03             1       [008..00E)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}

------------ BB02 [004..007) -> BB04 (always), preds={BB01} succs={BB04}

------------ BB03 [007..008), preds={BB01} succs={BB04}

------------ BB04 [008..00E) (return), preds={BB02,BB03} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Inline @[000004] Starting PHASE Importation

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'Awaitable:.ctor(bool):this'
    [ 0]   0 (0x000) ldarg.0
    [ 1]   1 (0x001) ldarg.1
    [ 2]   2 (0x002) brtrue.s
Folding operator with constant nodes into a constant:
               [000014] -----------                         *  NE        int   
               [000012] -----------                         +--*  CNS_INT   int    0
               [000013] -----------                         \--*  CNS_INT   int    0
Bashed to int constant:
               [000014] -----------                         *  CNS_INT   int    0

The block falls through into the next BB02

*************** In impGetSpillTmpBase(BB01)

lvaGrabTemps(1) returning 2..2 (long lifetime temps) called for IL Stack Entries
Spilling stack entries into temps

STMT00003 ( 0x000[E-] ... ??? ) <- INLRT @ ???
               [000015] DA---------                         *  STORE_LCL_VAR byref  V02 tmp2         
               [000011] -----------                         \--*  LCL_ADDR  byref  V01 tmp1         [+0]

impImportBlockPending for BB02

Importing BB02 (PC=004) of 'Awaitable:.ctor(bool):this'
    [ 1]   4 (0x004) ldc.i4.2 2
    [ 2]   5 (0x005) br.s
*************** In impGetSpillTmpBase(BB02)

lvaGrabTemps(2) returning 3..4 (long lifetime temps) called for IL Stack Entries
Spilling stack entries into temps

STMT00004 ( ??? ... ??? ) <- INLRT @ ???
               [000019] DA---------                         *  STORE_LCL_VAR byref  V03 tmp3         
               [000017] -----------                         \--*  LCL_VAR   byref  V02 tmp2

STMT00005 ( ??? ... ??? ) <- INLRT @ ???
               [000021] DA---------                         *  STORE_LCL_VAR int    V04 tmp4         
               [000018] -----------                         \--*  CNS_INT   int    2

impImportBlockPending for BB04

Importing BB04 (PC=008) of 'Awaitable:.ctor(bool):this'
    [ 2]   8 (0x008) stfld 04000003

STMT00006 ( ??? ... ??? ) <- INLRT @ ???
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000023] -----------                         |  \--*  LCL_VAR   byref  V03 tmp3         
               [000024] -----------                         \--*  LCL_VAR   int    V04 tmp4

[ 0]  13 (0x00d) ret
** Note: inlinee IL was partially imported -- imported 13 of 14 bytes of method IL

*************** Inline @[000004] Finishing PHASE Importation
Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001]  1                             1       [000..004)                                     i 
BB02 [0002]  1       BB01                  1       [004..007)-> BB04 (always)                     i 
BB03 [0003]  0                             1       [007..008)                                     
BB04 [0004]  2       BB02,BB03             1       [008..00E)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..004), preds={} succs={BB02}

***** BB01
STMT00003 ( 0x000[E-] ... ??? ) <- INLRT @ ???
               [000015] DA---------                         *  STORE_LCL_VAR byref  V02 tmp2         
               [000011] -----------                         \--*  LCL_ADDR  byref  V01 tmp1         [+0]

------------ BB02 [004..007) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00004 ( ??? ... ??? ) <- INLRT @ ???
               [000019] DA---------                         *  STORE_LCL_VAR byref  V03 tmp3         
               [000017] -----------                         \--*  LCL_VAR   byref  V02 tmp2

***** BB02
STMT00005 ( ??? ... ??? ) <- INLRT @ ???
               [000021] DA---------                         *  STORE_LCL_VAR int    V04 tmp4         
               [000018] -----------                         \--*  CNS_INT   int    2

------------ BB03 [007..008), preds={} succs={BB04}

------------ BB04 [008..00E) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00006 ( ??? ... ??? ) <- INLRT @ ???
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000023] -----------                         |  \--*  LCL_VAR   byref  V03 tmp3         
               [000024] -----------                         \--*  LCL_VAR   int    V04 tmp4

*************** Inline @[000004] Starting PHASE Expand patchpoints

-- no patchpoints to transform

*************** Inline @[000004] Finishing PHASE Expand patchpoints [no changes]

*************** Inline @[000004] Starting PHASE Indirect call transform

-- no candidates to transform

*************** Inline @[000004] Finishing PHASE Indirect call transform [no changes]

*************** Inline @[000004] Starting PHASE Post-import
BB03 was not imported, marking as removed (0)

Renumbering the basic blocks for fgPostImportationCleanup

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001]  1                             1       [000..004)                                     i 
BB02 [0002]  1       BB01                  1       [004..007)-> BB04 (always)                     i 
BB04 [0004]  1       BB02                  1       [008..00E)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
Renumber BB04 to BB03

*************** After renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001]  1                             1       [000..004)                                     i 
BB02 [0002]  1       BB01                  1       [004..007)-> BB03 (always)                     i 
BB03 [0004]  1       BB02                  1       [008..00E)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

New BlockSet epoch 1, # of blocks (including unused BB00): 4, bitset array size: 1 (short)

*************** Inline @[000004] Finishing PHASE Post-import
Trees after Post-import

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001]  1                             1       [000..004)                                     i 
BB02 [0002]  1       BB01                  1       [004..007)-> BB03 (always)                     i 
BB03 [0004]  1       BB02                  1       [008..00E)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..004), preds={} succs={BB02}

------------ BB02 [004..007) -> BB03 (always), preds={BB01} succs={BB03}

------------ BB03 [008..00E) (return), preds={BB02} succs={}

***** BB03
STMT00006 ( ??? ... ??? ) <- INLRT @ ???
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000023] -----------                         |  \--*  LCL_VAR   byref  V03 tmp3         
               [000024] -----------                         \--*  LCL_VAR   int    V04 tmp4

----------- Statements (and blocks) added due to the inlining of call [000004] -----------

Arguments setup:

Inlinee method body:New Basic Block BB02 [0005] created.
Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38]

Convert bbJumpKind of BB05 to BBJ_NONE
Setting edge weights for BB05 -> BB02 to [0 .. 3.402823e+38]
Setting edge weights for BB01 -> BB03 to [0 .. 3.402823e+38]
fgInlineAppendStatements: no gc ref inline locals.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB03 [0001]  1       BB01                  1       [000..000)                                     i internal 
BB04 [0002]  1       BB03                  1       [000..000)-> BB05 (always)                     i internal 
BB05 [0004]  1       BB04                  1       [000..000)                                     i internal 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB03 [000..000), preds={BB01} succs={BB04}

***** BB03
STMT00003 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
               [000015] DA---------                         *  STORE_LCL_VAR byref  V02 tmp2         
               [000011] -----------                         \--*  LCL_ADDR  byref  V01 tmp1         [+0]

------------ BB04 [000..000) -> BB05 (always), preds={BB03} succs={BB05}

***** BB04
STMT00004 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000019] DA---------                         *  STORE_LCL_VAR byref  V03 tmp3         
               [000017] -----------                         \--*  LCL_VAR   byref  V02 tmp2

***** BB04
STMT00005 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000021] DA---------                         *  STORE_LCL_VAR int    V04 tmp4         
               [000018] -----------                         \--*  CNS_INT   int    2

------------ BB05 [000..000), preds={BB04} succs={BB02}

***** BB05
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000023] -----------                         |  \--*  LCL_VAR   byref  V03 tmp3         
               [000024] -----------                         \--*  LCL_VAR   int    V04 tmp4

-------------------------------------------------------------------------------------------------------------------
Successfully inlined Awaitable:.ctor(bool):this (14 IL bytes) (depth 1) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Awaitable:Test():int' calling 'Awaitable:.ctor(bool):this'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'
**************** Inline Tree

Inlines into 06000013 [via ExtendedDefaultPolicy] Awaitable:Test():int:
  [INL01 IL=0001 TR=000004 06000012] [INLINED: callee: below ALWAYS_INLINE size] Awaitable:.ctor(bool):this
Budget: initialTime=96, finalTime=108, initialBudget=960, currentBudget=960
Budget: initialSize=404, finalSize=404

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..006)                                     i 
BB03 [0001]  1       BB01                  1       [000..000)                                     i internal 
BB04 [0002]  1       BB03                  1       [000..000)-> BB05 (always)                     i internal 
BB05 [0004]  1       BB04                  1       [000..000)                                     i internal 
BB02 [0005]  1       BB05                  1       [006..00C)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB04 to BB03
Renumber BB05 to BB04
Renumber BB02 to BB05

*************** After renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..006)                                     i 
BB02 [0001]  1       BB01                  1       [000..000)                                     i internal 
BB03 [0002]  1       BB02                  1       [000..000)-> BB04 (always)                     i internal 
BB04 [0004]  1       BB03                  1       [000..000)                                     i internal 
BB05 [0005]  1       BB04                  1       [006..00C)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

New BlockSet epoch 2, # of blocks (including unused BB00): 6, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..006)                                     i 
BB02 [0001]  1       BB01                  1       [000..000)                                     i internal 
BB03 [0002]  1       BB02                  1       [000..000)-> BB04 (always)                     i internal 
BB04 [0004]  1       BB03                  1       [000..000)                                     i internal 
BB05 [0005]  1       BB04                  1       [006..00C)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..006), preds={} succs={BB02}

------------ BB02 [000..000), preds={BB01} succs={BB03}

***** BB02
STMT00003 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
               [000015] DA---------                         *  STORE_LCL_VAR byref  V02 tmp2         
               [000011] -----------                         \--*  LCL_ADDR  byref  V01 tmp1         [+0]

------------ BB03 [000..000) -> BB04 (always), preds={BB02} succs={BB04}

***** BB03
STMT00004 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000019] DA---------                         *  STORE_LCL_VAR byref  V03 tmp3         
               [000017] -----------                         \--*  LCL_VAR   byref  V02 tmp2

***** BB03
STMT00005 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000021] DA---------                         *  STORE_LCL_VAR int    V04 tmp4         
               [000018] -----------                         \--*  CNS_INT   int    2

------------ BB04 [000..000), preds={BB03} succs={BB05}

***** BB04
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000023] -----------                         |  \--*  LCL_VAR   byref  V03 tmp3         
               [000024] -----------                         \--*  LCL_VAR   int    V04 tmp4

------------ BB05 [006..00C) (return), preds={BB04} succs={}

***** BB05
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000008] n----------                         \--*  IND       int   
               [000007] -----------                            \--*  FIELD_ADDR byref  Awaitable:Opts
               [000006] -----------                               \--*  LCL_ADDR  byref  V01 tmp1         [+0]

*************** Starting PHASE Allocate Objects
no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..006)                                     i 
BB02 [0001]  1       BB01                  1       [000..000)                                     i internal 
BB03 [0002]  1       BB02                  1       [000..000)-> BB04 (always)                     i internal 
BB04 [0004]  1       BB03                  1       [000..000)                                     i internal 
BB05 [0005]  1       BB04                  1       [006..00C)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks [no changes]

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally
No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Tail merge

*************** Finishing PHASE Tail merge [no changes]

*************** Starting PHASE Merge throw blocks

*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.

*************** Finishing PHASE Merge throw blocks [no changes]

*************** Starting PHASE Update flow graph early pass

Compacting BB02 into BB01:
*************** In fgDebugCheckBBlist

Compacting BB03 into BB01:
*************** In fgDebugCheckBBlist

Removing unconditional jump to next block (BB01 -> BB04) (converted BB01 to fall-through)

Compacting BB04 into BB01:
*************** In fgDebugCheckBBlist

Compacting BB05 into BB01:
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Update flow graph early pass
Trees after Update flow graph early pass

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00003 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
               [000015] DA---------                         *  STORE_LCL_VAR byref  V02 tmp2         
               [000011] -----------                         \--*  LCL_ADDR  byref  V01 tmp1         [+0]

***** BB01
STMT00004 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000019] DA---------                         *  STORE_LCL_VAR byref  V03 tmp3         
               [000017] -----------                         \--*  LCL_VAR   byref  V02 tmp2

***** BB01
STMT00005 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000021] DA---------                         *  STORE_LCL_VAR int    V04 tmp4         
               [000018] -----------                         \--*  CNS_INT   int    2

***** BB01
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000023] -----------                         |  \--*  LCL_VAR   byref  V03 tmp3         
               [000024] -----------                         \--*  LCL_VAR   int    V04 tmp4

*************** Starting PHASE Morph - Promote Structs

lvaTable before fgPromoteStructs
; Initial local variable assignments
;
;  V00 OutArgs        struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V01 tmp1           struct <Awaitable, 4> ld-addr-op "NewObj constructor temp"
;  V02 tmp2            byref 
;  V03 tmp3            byref 
;  V04 tmp4              int 
  struct promotion of V00 is disabled because it has already been marked address exposed

Promoting struct local V01 (Awaitable):
lvaGrabTemp returning 5 (V05 tmp5) (a long lifetime temp) called for field V01.Opts (fldOffset=0x0).

lvaTable after fgPromoteStructs
; Initial local variable assignments
;
;  V00 OutArgs        struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V01 tmp1           struct <Awaitable, 4> ld-addr-op "NewObj constructor temp"
;  V02 tmp2            byref 
;  V03 tmp3            byref 
;  V04 tmp4              int 
;  V05 tmp5              int  V01.Opts(offs=0x00) P-INDEP "field V01.Opts (fldOffset=0x0)"

*************** Finishing PHASE Morph - Promote Structs
Trees after Morph - Promote Structs

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00B )
               [000002] DA---------                         *  STORE_LCL_VAR struct<Awaitable, 4>(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000001] -----------                         \--*  CNS_INT   int    0

***** BB01
STMT00003 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
               [000015] DA---------                         *  STORE_LCL_VAR byref  V02 tmp2         
               [000011] -----------                         \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                               *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5

*************** Starting PHASE Morph - Structs/AddrExp
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x00B )
               [000002] DA---------                         *  STORE_LCL_VAR struct<Awaitable, 4>(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000001] -----------                         \--*  CNS_INT   int    0

LocalAddressVisitor visiting statement:
STMT00003 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
               [000015] DA---------                         *  STORE_LCL_VAR byref  V02 tmp2         
               [000011] -----------                         \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                               *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5

Local V05 should not be enregistered because: it is address exposed

Local V01 should not be enregistered because: it is address exposed
LocalAddressVisitor modified statement:
STMT00003 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
               [000015] DA---------                         *  STORE_LCL_VAR byref  V02 tmp2         
               [000011] -----------                         \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                               *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5

LocalAddressVisitor visiting statement:
STMT00004 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000019] DA---------                         *  STORE_LCL_VAR byref  V03 tmp3         
               [000017] -----------                         \--*  LCL_VAR   byref  V02 tmp2

LocalAddressVisitor visiting statement:
STMT00005 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000021] DA---------                         *  STORE_LCL_VAR int    V04 tmp4         
               [000018] -----------                         \--*  CNS_INT   int    2

LocalAddressVisitor visiting statement:
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000023] -----------                         |  \--*  LCL_VAR   byref  V03 tmp3         
               [000024] -----------                         \--*  LCL_VAR   int    V04 tmp4

LocalAddressVisitor visiting statement:
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000008] n----------                         \--*  IND       int   
               [000007] -----------                            \--*  FIELD_ADDR byref  Awaitable:Opts
               [000006] -----------                               \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                                     *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
Replacing the field in promoted struct with local var V05
LocalAddressVisitor modified statement:
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000008] -----------                         \--*  LCL_VAR   int   (AX) V05 tmp5

*************** Finishing PHASE Morph - Structs/AddrExp
Trees after Morph - Structs/AddrExp

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00B )
               [000002] DA---------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000001] -----------                         \--*  CNS_INT   int    0

***** BB01
STMT00002 ( 0x006[--] ... ??? )
               [000009] -----------                         *  RETURN    int   
               [000008] -----------                         \--*  LCL_VAR   int   (AX) V05 tmp5

*************** Starting PHASE Early liveness

Local V00 should not be enregistered because: struct size does not match reg size

Local V05 should not be enregistered because: field of a dependently promoted struct
Tracked variable (3 out of 6) table:
V02 tmp2          [ byref]: refCnt =    2, refCntWtd =   0   
V03 tmp3          [ byref]: refCnt =    2, refCntWtd =   0   
V04 tmp4          [   int]: refCnt =    2, refCntWtd =   0

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={           } + ByrefExposed
     DEF(3)={V02 V03 V04} + ByrefExposed

** Memory liveness computed, GcHeap states and ByrefExposed states diverge
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (0)={} + ByrefExposed
     OUT(0)={}

*************** Finishing PHASE Early liveness
Trees after Early liveness

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00004 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000019] DA---------                         *  STORE_LCL_VAR byref  V03 tmp3         
               [000017] -----------                         \--*  LCL_VAR   byref  V02 tmp2          (last use)

***** BB01
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000023] -----------                         |  \--*  LCL_VAR   byref  V03 tmp3          (last use)
               [000024] -----------                         \--*  LCL_VAR   int    V04 tmp4          (last use)

*************** Starting PHASE Physical promotion

*************** Finishing PHASE Physical promotion [no changes]

*************** Starting PHASE Forward Substitution

===> BB01
    [000002]:  not store (unaliased single-use lcl)
    [000015]:  [000017] is last use of [000015] (V02)  -- fwd subbing [000011]; new next stmt is
STMT00004 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000019] DA---------                         *  STORE_LCL_VAR byref  V03 tmp3         
               [000011] -----------                         \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                               *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5

removing useless STMT00003 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
               [000015] DA---------                         *  STORE_LCL_VAR byref  V02 tmp2         
               [000011] -----------                         \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                               *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
 from BB01
    [000002]:  not store (unaliased single-use lcl)
    [000019]:  no next stmt use
    [000021]:  [000024] is last use of [000021] (V04)  -- fwd subbing [000018]; new next stmt is
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000023] -----------                         |  \--*  LCL_VAR   byref  V03 tmp3          (last use)
               [000018] -----------                         \--*  CNS_INT   int    2

removing useless STMT00005 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000021] DA---------                         *  STORE_LCL_VAR int    V04 tmp4         
               [000018] -----------                         \--*  CNS_INT   int    2
 from BB01
    [000019]:  [000023] is last use of [000019] (V03)  -- fwd subbing [000011]; new next stmt is
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000011] -----------                         |  \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                            |     *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000018] -----------                         \--*  CNS_INT   int    2

removing useless STMT00004 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000019] DA---------                         *  STORE_LCL_VAR byref  V03 tmp3         
               [000011] -----------                         \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                               *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
 from BB01
    [000002]:  not store (unaliased single-use lcl)

*************** Finishing PHASE Forward Substitution
Trees after Forward Substitution

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000011] -----------                         |  \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                            |     *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000018] -----------                         \--*  CNS_INT   int    2

*************** Starting PHASE Morph - ByRefs

*************** Finishing PHASE Morph - ByRefs [no changes]

*************** Starting PHASE Morph - Global

*************** In fgMorphBlocks()

Morphing BB01 of 'Awaitable:Test():int'

fgMorphTree BB01, STMT00000 (before)
               [000002] DA---------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000001] -----------                         \--*  CNS_INT   int    0
MorphInitBlock:
PrepareDst for [000002] have found a local var V01.

Local V01 should not be enregistered because: written/read in a block op
MorphInitBlock (after):
               [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000001] -----+-----                         \--*  CNS_INT   int    0

fgMorphTree BB01, STMT00006 (before)
               [000026] nA-XG------                         *  STOREIND  int   
               [000025] ---X-------                         +--*  FIELD_ADDR byref  Awaitable:Opts
               [000011] -----------                         |  \--*  LCL_ADDR  byref  V01 tmp1         [+0]
                                                            |     *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000018] -----------                         \--*  CNS_INT   int    2

Final value of Compiler::fgMorphFieldAddr after morphing:
               [000011] -----+-----                         *  LCL_ADDR  byref  V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5

fgMorphTree BB01, STMT00006 (after)
               [000011] DA--G+-----                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000018] -----+-----                         \--*  CNS_INT   int    2

fgMorphTree BB01, STMT00002 (before)
               [000009] -----------                         *  RETURN    int   
               [000008] -----------                         \--*  LCL_VAR   int   (AX) V05 tmp5

*************** In fgMarkDemotedImplicitByRefArgs()

*************** Finishing PHASE Morph - Global
Trees after Morph - Global

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00B )
               [000002] DA--G+-----                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000001] -----+-----                         \--*  CNS_INT   int    0

***** BB01
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000011] DA--G+-----                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000018] -----+-----                         \--*  CNS_INT   int    2

***** BB01
STMT00002 ( 0x006[--] ... ??? )
               [000009] ----G+-----                         *  RETURN    int   
               [000008] ----G+-----                         \--*  LCL_VAR   int   (AX) V05 tmp5

*************** Starting PHASE GS Cookie
No GS security needed

*************** Finishing PHASE GS Cookie [no changes]

*************** Starting PHASE Compute edge weights (1, false)

-- no profile data, so using default called count
 -- not optimizing or no profile data, so not computing edge weights

*************** Finishing PHASE Compute edge weights (1, false) [no changes]

*************** Starting PHASE Create EH funclets

*************** Finishing PHASE Create EH funclets [no changes]

*************** Starting PHASE Invert loops

*************** Before renumbering the basic blocks

***************  Exception Handling table is empty
=============== No blocks renumbered!

New BlockSet epoch 3, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** Finishing PHASE Invert loops
Trees after Invert loops

------------ BB01 [000..00C) (return), preds={} succs={}

*************** Starting PHASE Optimize control flow

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

*************** In fgDebugCheckBBlist

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize control flow
Trees after Optimize control flow

------------ BB01 [000..00C) (return), preds={} succs={}

*************** Starting PHASE Post-morph tail merge

*************** Finishing PHASE Post-morph tail merge [no changes]

*************** Starting PHASE Compute blocks reachability
Return blocks: BB01

Renumbering the basic blocks for fgComputeReachability pass #1

*************** Before renumbering the basic blocks

***************  Exception Handling table is empty
=============== No blocks renumbered!
Enter blocks: BB01

Dominator computation start blocks (those blocks with no incoming edges):
BB01

Inside fgBuildDomTree

After computing the Dominance Tree:

After numbering the dominator tree:
BB01: pre=01, post=01

*************** Finishing PHASE Compute blocks reachability [no changes]

*************** Starting PHASE Set block weights

*************** Finishing PHASE Set block weights [no changes]

*************** Starting PHASE Find loops
*************** In optFindLoops()
*************** In optMarkLoopHeads()
0 loop heads marked

*************** Finishing PHASE Find loops
Trees after Find loops

------------ BB01 [000..00C) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Clone loops

*************** In optCloneLoops()
  No loops to clone

*************** Finishing PHASE Clone loops [no changes]

*************** Starting PHASE Unroll loops

*************** Finishing PHASE Unroll loops [no changes]

*************** Starting PHASE Clear loop info

*************** Finishing PHASE Clear loop info [no changes]

*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function

*************** Finishing PHASE Morph array ops [no changes]

*************** Starting PHASE Mark local vars

*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** marking local variables in block BB01 (weight=1)
STMT00000 ( 0x000[E-] ... 0x00B )
               [000002] DA--G+-----                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000001] -----+-----                         \--*  CNS_INT   int    0
New refCnts for V05: refCnt =  1, refCntWtd = 2
New refCnts for V01: refCnt =  1, refCntWtd = 2
V01 needs explicit zero init. Disqualified as a single-def register candidate.
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
               [000011] DA--G+-----                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
               [000018] -----+-----                         \--*  CNS_INT   int    2
New refCnts for V05: refCnt =  2, refCntWtd = 4
New refCnts for V01: refCnt =  2, refCntWtd = 4
STMT00002 ( 0x006[--] ... ??? )
               [000009] ----G+-----                         *  RETURN    int   
               [000008] ----G+-----                         \--*  LCL_VAR   int   (AX) V05 tmp5         
New refCnts for V01: refCnt =  3, refCntWtd = 6
New refCnts for V05: refCnt =  3, refCntWtd = 5

*** lvaComputeRefCounts -- implicit counts ***

*************** Finishing PHASE Mark local vars [no changes]

*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()

*************** Finishing PHASE Find oper order
Trees after Find oper order

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00B )
     ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
     (  1,  1) [000001] -----------                         \--*  CNS_INT   int    0

***** BB01
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
     (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
     (  1,  1) [000018] -----------                         \--*  CNS_INT   int    2

***** BB01
STMT00002 ( 0x006[--] ... ??? )
     (  4,  3) [000009] ----G------                         *  RETURN    int   
     (  3,  2) [000008] ----G------                         \--*  LCL_VAR   int   (AX) V05 tmp5

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has    2 tree nodes

*************** Finishing PHASE Set block order
Trees after Set block order

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00B )
N002 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
N001 (  1,  1) [000001] -----------                         \--*  CNS_INT   int    0

***** BB01
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
N002 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
N001 (  1,  1) [000018] -----------                         \--*  CNS_INT   int    2

***** BB01
STMT00002 ( 0x006[--] ... ??? )
N002 (  4,  3) [000009] ----G------                         *  RETURN    int   
N001 (  3,  2) [000008] ----G------                         \--*  LCL_VAR   int   (AX) V05 tmp5

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 2.

***************  Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]

Inside fgBuildDomTree

After computing the Dominance Tree:

*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit

Local V00 should not be enregistered because: struct size does not match reg size

Local V05 should not be enregistered because: field of a dependently promoted struct
Tracked variable (0 out of 6) table:

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={} + ByrefExposed
     DEF(0)={} + ByrefExposed

** Memory liveness computed, GcHeap states and ByrefExposed states diverge
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (0)={} + ByrefExposed
     OUT(0)={}

*************** In optRemoveRedundantZeroInits()
Marking V01 as having an explicit init
Marking V01 as having an explicit init
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()

*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation

------------ BB01 [000..00C) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
SSA checks completed successfully
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method

*************** Finishing PHASE Early Value Propagation [no changes]

*************** Starting PHASE Do value numbering

***** BB01, STMT00000(before)
N002 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
N001 (  1,  1) [000001] -----------                         \--*  CNS_INT   int    0

N001 [000001]   CNS_INT   0 => $41 {IntCns 0}
  fgCurMemoryVN[ByrefExposed] assigned for local assign at [000002] to VN: $81.
N002 [000002]   STORE_LCL_VAR V01 tmp1         
                                                                int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          => $VN.Void

***** BB01, STMT00000(after)
N002 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
N001 (  1,  1) [000001] -----------                         \--*  CNS_INT   int    0 $41

---------

***** BB01, STMT00006(before)
N002 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5         
N001 (  1,  1) [000018] -----------                         \--*  CNS_INT   int    2

N001 [000018]   CNS_INT   2 => $42 {IntCns 2}
  fgCurMemoryVN[ByrefExposed] assigned for local assign at [000011] to VN: $82.
N002 [000011]   STORE_LCL_FLD V01 tmp1         [+0]
                                                                int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          => $VN.Void

***** BB01, STMT00006(after)
N002 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
N001 (  1,  1) [000018] -----------                         \--*  CNS_INT   int    2 $42

---------

***** BB01, STMT00002(before)
N002 (  4,  3) [000009] ----G------                         *  RETURN    int   
N001 (  3,  2) [000008] ----G------                         \--*  LCL_VAR   int   (AX) V05 tmp5

N001 [000008]   LCL_VAR   V05 tmp5          => <l:$180 {ByrefExposedLoad($44, $140, $82)}, c:$1c0 {MemOpaque:NotInLoop}>
N002 [000009]   RETURN    => $VN.Void

***** BB01, STMT00002(after)
N002 (  4,  3) [000009] ----G------                         *  RETURN    int    $VN.Void
N001 (  3,  2) [000008] ----G------                         \--*  LCL_VAR   int   (AX) V05 tmp5          <l:$180, c:$1c0>

finish(BB01).

*************** Finishing PHASE Do value numbering
Trees after Do value numbering

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00B )
N002 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
N001 (  1,  1) [000001] -----------                         \--*  CNS_INT   int    0 $41

***** BB01
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
N002 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
N001 (  1,  1) [000018] -----------                         \--*  CNS_INT   int    2 $42

***** BB01
STMT00002 ( 0x006[--] ... ??? )
N002 (  4,  3) [000009] ----G------                         *  RETURN    int    $VN.Void
N001 (  3,  2) [000008] ----G------                         \--*  LCL_VAR   int   (AX) V05 tmp5          <l:$180, c:$1c0>

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
SSA checks completed successfully
*************** In fgDebugCheckLoopTable

*************** Starting PHASE Hoist loop code

No loops; no hoisting

*************** Finishing PHASE Hoist loop code [no changes]

*************** Starting PHASE VN based copy prop
Copy Assertion for BB01
  curSsaName stack: { }

*************** Finishing PHASE VN based copy prop [no changes]

*************** Starting PHASE Redundant branch opts

*************** Finishing PHASE Redundant branch opts [no changes]

*************** Starting PHASE Optimize Valnum CSEs

*************** Finishing PHASE Optimize Valnum CSEs
Trees after Optimize Valnum CSEs

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00B )
N002 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
N001 (  1,  1) [000001] -----------                         \--*  CNS_INT   int    0 $41

***** BB01
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
N002 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
N001 (  1,  1) [000018] -----------                         \--*  CNS_INT   int    2 $42

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
SSA checks completed successfully
*************** In fgDebugCheckLoopTable
Disabling SSA checking before assertion prop

*************** Starting PHASE Assertion prop

*************** Finishing PHASE Assertion prop [no changes]

*************** Starting PHASE Optimize index checks

*************** Finishing PHASE Optimize index checks [no changes]

*************** Starting PHASE VN-based dead store removal

*************** Finishing PHASE VN-based dead store removal [no changes]

*************** Starting PHASE Stress gtSplitTree

*************** Finishing PHASE Stress gtSplitTree [no changes]

*************** Starting PHASE Expand runtime lookups

*************** Finishing PHASE Expand runtime lookups [no changes]

*************** Starting PHASE Expand static init
Nothing to expand.

*************** Finishing PHASE Expand static init [no changes]

*************** Starting PHASE Expand TLS access
Nothing to expand.

*************** Finishing PHASE Expand TLS access [no changes]

*************** Starting PHASE Insert GC Polls

*************** Finishing PHASE Insert GC Polls [no changes]

*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()

optimized 0 BBJ_COND cases, 0 BBJ_RETURN cases in 1 passes

*************** Finishing PHASE Optimize bools [no changes]

*************** Starting PHASE If conversion

*************** Finishing PHASE If conversion [no changes]

*************** Starting PHASE Optimize layout

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

*************** In fgDebugCheckBBlist

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize layout
Trees after Optimize layout

------------ BB01 [000..00C) (return), preds={} succs={}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00B )
N002 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
N001 (  1,  1) [000001] -----------                         \--*  CNS_INT   int    0 $41

***** BB01
STMT00006 ( INL01 @ ??? ... ??? ) <- INLRT @ ???
N002 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
N001 (  1,  1) [000018] -----------                         \--*  CNS_INT   int    2 $42

*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method

*************** Finishing PHASE Determine first cold block [no changes]

*************** Starting PHASE Rationalize IR

*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR

------------ BB01 [000..00C) (return), preds={} succs={}
               [000028] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000001] -----------                    t1 =    CNS_INT   int    0 $41
                                                            /--*  t1     int    
N002 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
N001 (  1,  1) [000018] -----------                   t18 =    CNS_INT   int    2 $42
                                                            /--*  t18    int    
N002 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
               [000029] -----------                            IL_OFFSET void   INLRT @ 0x006[--]
N001 (  3,  2) [000008] -----------                    t8 =    LCL_VAR   int   (AX) V05 tmp5          <l:$180, c:$1c0>
                                                            /--*  t8     int    
N002 (  4,  3) [000009] ----G------                         *  RETURN    int    $VN.Void

*************** Starting PHASE Do 'simple' lowering

*************** Finishing PHASE Do 'simple' lowering [no changes]

*************** Starting PHASE Lowering nodeinfo
lowering store lcl var/field (before):
N001 (  1,  1) [000001] -----------                    t1 =    CNS_INT   int    0 $41
                                                            /--*  t1     int    
N002 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void

lowering store lcl var/field (after):
N001 (  1,  1) [000001] -----------                    t1 =    CNS_INT   int    0 $41
                                                            /--*  t1     int    
N002 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void

lowering store lcl var/field (before):
N001 (  1,  1) [000018] -----------                   t18 =    CNS_INT   int    2 $42
                                                            /--*  t18    int    
N002 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void

lowering store lcl var/field (after):
N001 (  1,  1) [000018] -c---------                   t18 =    CNS_INT   int    2 $42
                                                            /--*  t18    int    
N002 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void

lowering GT_RETURN
N002 (  4,  3) [000009] ----G------                         *  RETURN    int    $VN.Void
============Lower has completed modifying nodes.

------------ BB01 [000..00C) (return), preds={} succs={}
               [000028] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000001] -----------                    t1 =    CNS_INT   int    0 $41
                                                            /--*  t1     int    
N002 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
N001 (  1,  1) [000018] -c---------                   t18 =    CNS_INT   int    2 $42
                                                            /--*  t18    int    
N002 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
               [000029] -----------                            IL_OFFSET void   INLRT @ 0x006[--]
N001 (  3,  2) [000008] -----------                    t8 =    LCL_VAR   int   (AX) V05 tmp5          <l:$180, c:$1c0>
                                                            /--*  t8     int    
N002 (  4,  3) [000009] ----G------                         *  RETURN    int    $VN.Void

-------------------------------------------------------------------------------------------------------------------

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V05: refCnt =  1, refCntWtd = 2
New refCnts for V01: refCnt =  1, refCntWtd = 2
New refCnts for V05: refCnt =  2, refCntWtd = 4
New refCnts for V01: refCnt =  2, refCntWtd = 4
New refCnts for V01: refCnt =  3, refCntWtd = 6
New refCnts for V05: refCnt =  3, refCntWtd = 5

*** lvaComputeRefCounts -- implicit counts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
;  V00 OutArgs        struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V01 tmp1           struct <Awaitable, 4> do-not-enreg[XS] addr-exposed ld-addr-op "NewObj constructor temp"
;  V02 tmp2            byref 
;  V03 tmp3            byref 
;  V04 tmp4              int 
;  V05 tmp5              int  do-not-enreg[X] addr-exposed V01.Opts(offs=0x00) P-DEP "field V01.Opts (fldOffset=0x0)"
In fgLocalVarLivenessInit

Local V00 should not be enregistered because: struct size does not match reg size

Local V05 should not be enregistered because: field of a dependently promoted struct
Tracked variable (0 out of 6) table:

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={} + ByrefExposed
     DEF(0)={} + ByrefExposed

** Memory liveness computed, GcHeap states and ByrefExposed states diverge
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (0)={} + ByrefExposed
     OUT(0)={}

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

*************** In fgDebugCheckBBlist

*************** In fgRemoveDeadBlocks()
Removing unreachable blocks for fgRemoveDeadBlocks iteration #1
*************** In fgDebugCheckBBlist

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- implicit counts ***

*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo

------------ BB01 [000..00C) (return), preds={} succs={}
               [000028] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  1) [000001] -----------                    t1 =    CNS_INT   int    0 $41
                                                            /--*  t1     int    
N002 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1         
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
N001 (  1,  1) [000018] -c---------                   t18 =    CNS_INT   int    2 $42
                                                            /--*  t18    int    
N002 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0]
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          $VN.Void
               [000029] -----------                            IL_OFFSET void   INLRT @ 0x006[--]
N001 (  3,  2) [000008] -----------                    t8 =    LCL_VAR   int   (AX) V05 tmp5          <l:$180, c:$1c0>
                                                            /--*  t8     int    
N002 (  4,  3) [000009] ----G------                         *  RETURN    int    $VN.Void

*************** Starting PHASE Calculate stack level slots

*************** Finishing PHASE Calculate stack level slots [no changes]

*************** Starting PHASE Linear scan register alloc
Clearing modified regs.

buildIntervals ========

-----------------
LIVENESS:
-----------------
BB01
use: {}
def: {}
 in: {}
out: {}

FP callee save candidate vars: None

floatVarCount = 0; hasLoops = false, singleExit = true
TUPLE STYLE DUMP BEFORE LSRA
Start LSRA Block Sequence: 
Current block: BB01
Final LSRA Block Sequence:
BB01 (  1   )

BB01 [000..00C) (return), preds={} succs={}
=====
  N000.                    IL_OFFSET INLRT @ 0x000[E-]
  N001. t1              =  CNS_INT   0
  N002.                    V01 MEM; t1
  N001.                    CNS_INT   2
  N002.                    V01 MEM
  N000.                    IL_OFFSET INLRT @ 0x006[--]
  N001. t8              =  V05 MEM
  N002.                    RETURN   ; t8

buildIntervals second part ========

NEW BLOCK BB01
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N002 (???,???) [000028] -----------                         *  IL_OFFSET void   INLRT @ 0x000[E-] REG NA

DefList: {  }
N004 (  1,  1) [000001] -----------                         *  CNS_INT   int    0 REG NA $41
Interval  0: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N004.t1. CNS_INT }
N006 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1          NA
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          REG NA $VN.Void
<RefPosition #2   @6   RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last wt=100.00>

DefList: {  }
N008 (  1,  1) [000018] -c---------                         *  CNS_INT   int    2 REG NA $42
Contained
DefList: {  }
N010 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0] NA
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          REG NA $VN.Void

DefList: {  }
N012 (???,???) [000029] -----------                         *  IL_OFFSET void   INLRT @ 0x006[--] REG NA

DefList: {  }
N014 (  3,  2) [000008] -----------                         *  LCL_VAR   int   (AX) V05 tmp5          NA REG NA <l:$180, c:$1c0>
Interval  1: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #3   @15  RefTypeDef <Ivl:1> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>

DefList: { N014.t8. LCL_VAR }
N016 (  4,  3) [000009] ----G------                         *  RETURN    int    REG NA $VN.Void
<RefPosition #4   @16  RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #5   @16  RefTypeUse <Ivl:1> BB01 regmask=[rax] minReg=1 last fixed wt=100.00>

Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval  0: int (constant) RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval  1: int RefPositions {#3@15 #5@16} physReg:NA Preferences=[rax]

------------
REFPOSITIONS BEFORE VALIDATING INTERVALS: 
------------
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #2   @6   RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #3   @15  RefTypeDef <Ivl:1> LCL_VAR BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #4   @16  RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #5   @16  RefTypeUse <Ivl:1> BB01 regmask=[rax] minReg=1 last fixed wt=100.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: 
BB01 [000..00C) (return), preds={} succs={}
=====
  N002.                    IL_OFFSET INLRT @ 0x000[E-]
  N004.                    CNS_INT   0
        Def:<I0>(#1)
  N006.                    V01 MEM
                               Use:<I0>(#2) *
  N008.                    CNS_INT   2
  N010.                    V01 MEM
  N012.                    IL_OFFSET INLRT @ 0x006[--]
  N014.                    V05 MEM
        Def:<I1>(#3)
  N016.                    RETURN   
                               Use:<I1>(#5) Fixed:rax(#4) *

Linear scan intervals after buildIntervals:
Interval  0: int (constant) RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval  1: int RefPositions {#3@15 #5@16} physReg:NA Preferences=[rax]

*************** In LinearScan::allocateRegisters()

Linear scan intervals before allocateRegisters:
Interval  0: int (constant) RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval  1: int RefPositions {#3@15 #5@16} physReg:NA Preferences=[rax]

------------
REFPOSITIONS BEFORE ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #2   @6   RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #3   @15  RefTypeDef <Ivl:1> LCL_VAR BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #4   @16  RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #5   @16  RefTypeUse <Ivl:1> BB01 regmask=[rax] minReg=1 last fixed wt=100.00>

-----------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LocRP#Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
-----------------------------------------+----+----+----+----+----+----+----+----+----+
                                         |    |    |    |    |    |    |    |    |    |
          0.#0 BB1 PredBB0               |    |    |    |    |    |    |    |    |    |
[000001]  5.#1 C0   Def    BSFIT(A) rax  |C0 a|    |    |    |    |    |    |    |    |
[000002]  6.#2 C0   Use *  Keep     rax  |C0 a|    |    |    |    |    |    |    |    |
[000008] 15.#3 I1   Def    Alloc    rax  |I1 a|    |    |    |    |    |    |    |    |
[000009] 16.#4 rax  Fixd   Keep     rax  |I1 a|    |    |    |    |    |    |    |    |
         16.#5 I1   Use *  Keep     rax  |    |    |    |    |    |    |    |    |    |

------------
REFPOSITIONS AFTER ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #2   @6   RefTypeUse <Ivl:0> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #3   @15  RefTypeDef <Ivl:1> LCL_VAR BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #4   @16  RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #5   @16  RefTypeUse <Ivl:1> BB01 regmask=[rax] minReg=1 last fixed wt=100.00>
Active intervals at end of allocation:

Trees after linear scan register allocator (LSRA)

------------ BB01 [000..00C) (return), preds={} succs={}
N002 (???,???) [000028] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
N004 (  1,  1) [000001] -----------                    t1 =    CNS_INT   int    0 REG rax $41
                                                            /--*  t1     int    
N006 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1          NA
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          REG NA $VN.Void
N008 (  1,  1) [000018] -c---------                   t18 =    CNS_INT   int    2 REG NA $42
                                                            /--*  t18    int    
N010 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0] NA
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          REG NA $VN.Void
N012 (???,???) [000029] -----------                            IL_OFFSET void   INLRT @ 0x006[--] REG NA
N014 (  3,  2) [000008] -----------                    t8 =    LCL_VAR   int   (AX) V05 tmp5          rax REG rax <l:$180, c:$1c0>
                                                            /--*  t8     int    
N016 (  4,  3) [000009] ----G------                         *  RETURN    int    REG NA $VN.Void

-------------------------------------------------------------------------------------------------------------------

Final allocation
-----------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID   LocRP#Name Type  Action    Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
-----------------------------------------+----+----+----+----+----+----+----+----+----+
          0.#0 BB1 PredBB0               |    |    |    |    |    |    |    |    |    |
[000001]  5.#1 C0   Def    Alloc    rax  |C0 a|    |    |    |    |    |    |    |    |
[000002]  6.#2 C0   Use *  Keep     rax  |C0 i|    |    |    |    |    |    |    |    |
[000008] 15.#3 I1   Def    Alloc    rax  |I1 a|    |    |    |    |    |    |    |    |
[000009] 16.#4 rax  Fixd   Keep     rax  |I1 a|    |    |    |    |    |    |    |    |
         16.#5 I1   Use *  Keep     rax  |I1 i|    |    |    |    |    |    |    |    |

Recording the maximum number of concurrent spills:

----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars:  0
Total Reg Cand Vars: 0
Total number of Intervals: 1
Total number of RefPositions: 5
Total Number of spill temps created: 0
..........
BB01 [  100.00]: BEST_FIT = 1
..........
Total SpillCount : 0   Weighted: 0.000000
Total CopyReg : 0   Weighted: 0.000000
Total ResolutionMovs : 0   Weighted: 0.000000
Total SplitEdges : 0   Weighted: 0.000000
..........
Total BEST_FIT [#11] : 1   Weighted: 100.000000

TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: 
BB01 [000..00C) (return), preds={} succs={}
=====
  N002.                    IL_OFFSET INLRT @ 0x000[E-]
  N004. rax             =  CNS_INT   0
  N006.                    V01 MEM; rax
  N008.                    CNS_INT   2
  N010.                    V01 MEM
  N012.                    IL_OFFSET INLRT @ 0x006[--]
  N014. rax             =  V05 MEM
  N016.                    RETURN   ; rax

*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc

*************** Starting PHASE Place 'align' instructions

*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()

*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Modified regs: [rax]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V01 tmp1, size=8, stkOffs=-0x10
--- delta bump 8 for RA
--- delta bump 8 for RSP frame
--- virtual stack offset to actual stack offset delta is 16
-- V00 was 0, now 16
-- V01 was -16, now 0
Adjusting offset of dependent V05 of V01: parent 0 field 0 net 0
; Final local variable assignments
;
;# V00 OutArgs      [V00    ] (  1,  1   )  struct ( 0) [rsp+00H]   do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V01 tmp1         [V01    ] (  3,  6   )  struct ( 8) [rsp+00H]   do-not-enreg[XS] addr-exposed ld-addr-op "NewObj constructor temp"
;* V02 tmp2         [V02    ] (  0,  0   )   byref  ->  zero-ref   
;* V03 tmp3         [V03    ] (  0,  0   )   byref  ->  zero-ref   
;* V04 tmp4         [V04    ] (  0,  0   )     int  ->  zero-ref   
;  V05 tmp5         [V05    ] (  3,  5   )     int  ->  [rsp+00H]   do-not-enreg[X] addr-exposed V01.Opts(offs=0x00) P-DEP "field V01.Opts (fldOffset=0x0)"
;
; Lcl frame size = 8
Created:
      G_M24766_IG02:        ; offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
  BB01 : first block
*************** After genMarkLabelsForCodegen()

=============== Generating BB01 [000..00C) (return), preds={} succs={} flags=0x00000000.00020011: i label LIR 
BB01 IN (0)={} + ByrefExposed
     OUT(0)={}

Liveness not changing: 0000000000000000 {}
							Live regs: (unchanged) 0000 {}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 0000 {}

L_M24766_BB01:
Label: G_M24766_IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Added IP mapping: 0x0000 STACK_EMPTY (G_M24766_IG02,ins#0,ofs#0) label
Generating: N002 (???,???) [000028] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
Generating: N004 (  1,  1) [000001] -----------                    t1 =    CNS_INT   int    0 REG rax $41
Mapped BB01 to G_M24766_IG02
IN0001:        xor      eax, eax
                                                                        /--*  t1     int    
Generating: N006 ( 11,  8) [000002] DA--G------                         *  STORE_LCL_VAR struct<Awaitable, 4>(AX)(P) V01 tmp1          NA
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          REG NA $VN.Void
IN0002:        mov      dword ptr [V01 rsp], eax
Generating: N008 (  1,  1) [000018] -c---------                   t18 =    CNS_INT   int    2 REG NA $42
                                                                        /--*  t18    int    
Generating: N010 (  5,  6) [000011] DA--G------                         *  STORE_LCL_FLD int   (AX)(P) V01 tmp1         [+0] NA
                                                            *    int    V01.Awaitable:Opts (offs=0x00) -> V05 tmp5          REG NA $VN.Void
IN0003:        mov      dword ptr [V01 rsp], 2
Added IP mapping: 0x0006 (G_M24766_IG02,ins#3,ofs#12)
Generating: N012 (???,???) [000029] -----------                            IL_OFFSET void   INLRT @ 0x006[--] REG NA
Generating: N014 (  3,  2) [000008] -----------                    t8 =    LCL_VAR   int   (AX) V05 tmp5          rax REG rax <l:$180, c:$1c0>
IN0004:        mov      eax, dword ptr [V05 rsp]
                                                                        /--*  t8     int    
Generating: N016 (  4,  3) [000009] ----G------                         *  RETURN    int    REG NA $VN.Void
Added IP mapping: EPILOG (G_M24766_IG02,ins#4,ofs#15) label
Reserving epilog IG for block BB01
Saved:
      G_M24766_IG02:        ; offs=000000H, size=000FH, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
Created:
      G_M24766_IG03:        ; offs=00000FH, size=0000H, bbWeight=1, gcrefRegs=0000 {}
*************** After placeholder IG creation
G_M24766_IG01:        ; func=00, offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M24766_IG02:        ; offs=000000H, size=000FH, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M24766_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}

Variable Live Range History Dump for BB01
..None..
Liveness not changing: 0000000000000000 {}

# compCycleEstimate =     20, compSizeEstimate =    17 Awaitable:Test():int
; Final local variable assignments
;
;# V00 OutArgs      [V00    ] (  1,  1   )  struct ( 0) [rsp+00H]   do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V01 tmp1         [V01    ] (  3,  6   )  struct ( 8) [rsp+00H]   do-not-enreg[XS] addr-exposed ld-addr-op "NewObj constructor temp"
;* V02 tmp2         [V02    ] (  0,  0   )   byref  ->  zero-ref   
;* V03 tmp3         [V03    ] (  0,  0   )   byref  ->  zero-ref   
;* V04 tmp4         [V04    ] (  0,  0   )     int  ->  zero-ref   
;  V05 tmp5         [V05    ] (  3,  5   )     int  ->  [rsp+00H]   do-not-enreg[X] addr-exposed V01.Opts(offs=0x00) P-DEP "field V01.Opts (fldOffset=0x0)"
;
; Lcl frame size = 8
*************** Before prolog / epilog generation
G_M24766_IG01:        ; func=00, offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M24766_IG02:        ; offs=000000H, size=000FH, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M24766_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M24766_IG01,ins#0,ofs#0) label

__prolog:
IN0005:        push     rax
*************** In genEnregisterIncomingStackArgs()

Saved:
      G_M24766_IG01:        ; offs=000000H, size=0001H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc
*************** In genFnEpilog()

__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {}
IN0006:        add      rsp, 8
IN0007:        ret      
Saved:
      G_M24766_IG03:        ; offs=00000FH, size=0005H, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M24766_IG01:        ; func=00, offs=000000H, size=0001H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M24766_IG02:        ; offs=000001H, size=000FH, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M24766_IG03:        ; offs=000010H, size=0005H, bbWeight=1, epilog, nogc, extend
*************** In emitJumpDistBind()
Emitter Jump List:
  total jump count: 0

*************** Finishing PHASE Generate code

*************** Starting PHASE Emit code

Hot  code size = 0x15 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x6)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)

***************************************************************************
Instructions as they come out of the scheduler

G_M24766_IG01:        ; offs=000000H, size=0001H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0005: 000000 push     rax
						;; size=1 bbWeight=1 PerfScore 1.00
G_M24766_IG02:        ; offs=000001H, size=000FH, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
IN0001: 000001 xor      eax, eax
IN0002: 000003 mov      dword ptr [rsp], eax
IN0003: 000006 mov      dword ptr [rsp], 2
IN0004: 00000D mov      eax, dword ptr [rsp]
						;; size=15 bbWeight=1 PerfScore 3.25
G_M24766_IG03:        ; offs=000010H, size=0005H, bbWeight=1, epilog, nogc, extend
IN0006: 000010 add      rsp, 8
IN0007: 000014 ret      
						;; size=5 bbWeight=1 PerfScore 1.25Allocated method code size =   21 , actual size =   21, unused size =    0

; Total bytes of code 21, prolog size 1, PerfScore 7.60, instruction count 7, allocated bytes for code 21 (MethodHash=29e49f41) for method Awaitable:Test():int
; ============================================================

*************** After end code gen, before unwindEmit()
G_M24766_IG01:        ; func=00, offs=000000H, size=0001H, bbWeight=1, PerfScore 1.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG

IN0005: 000000 push     rax

G_M24766_IG02:        ; offs=000001H, size=000FH, bbWeight=1, PerfScore 3.25, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref

IN0001: 000001 xor      eax, eax
IN0002: 000003 mov      dword ptr [V01 rsp], eax
IN0003: 000006 mov      dword ptr [V01 rsp], 2
IN0004: 00000D mov      eax, dword ptr [V05 rsp]

G_M24766_IG03:        ; offs=000010H, size=0005H, bbWeight=1, PerfScore 1.25, epilog, nogc, extend

IN0006: 000010 add      rsp, 8
IN0007: 000014 ret

*************** Finishing PHASE Emit code

*************** Starting PHASE Emit GC+EH tables
Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0xd1ffab1e (not in unwind data)
  Version           : 1
  Flags             : 0x00
  SizeOfProlog      : 0x01
  CountOfUnwindCodes: 1
  FrameRegister     : none (0)
  FrameOffset       : N/A (no FrameRegister) (Value=0)
  UnwindCodes       :
    CodeOffset: 0x01 UnwindOp: UWOP_ALLOC_SMALL (2)     OpInfo: 0 * 8 + 8 = 8 = 0x08
allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x15, unwindSize=0x6, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 4
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000001 ( STACK_EMPTY )
IL offs 0x0006 : 0x0000000D
IL offs EPILOG : 0x00000010 ( STACK_EMPTY )

*************** In genSetScopeInfo()
VarLocInfo count is 0
; Variable debug info: 0 live ranges, 0 vars for method Awaitable:Test():int
*************** In gcInfoBlockHdrSave()
Set code length to 21.
Set ReturnKind to Scalar.
Set Outgoing stack arg area size to 0.
Defining 0 call sites:

*************** Finishing PHASE Emit GC+EH tables
Method code size: 21

Allocations for Awaitable:Test():int (MethodHash=29e49f41)
count:        425, size:      53715, max =       5288
allocateMemory:      65536, nraUsed:      58896

Alloc'd bytes by kind:
                  kind |       size |     pct
  ---------------------+------------+--------
         AssertionProp |       6500 |  12.10%
               ASTNode |       4400 |   8.19%
              InstDesc |       2440 |   4.54%
              ImpStack |        456 |   0.85%
            BasicBlock |       2368 |   4.41%
              CallArgs |        160 |   0.30%
              FlowEdge |        336 |   0.63%
     TreeStatementList |          0 |   0.00%
               SiScope |          0 |   0.00%
       DominatorMemory |         96 |   0.18%
                  LSRA |       6744 |  12.56%
         LSRA_Interval |        160 |   0.30%
      LSRA_RefPosition |        480 |   0.89%
          Reachability |         40 |   0.07%
                   SSA |         80 |   0.15%
           ValueNumber |       6970 |  12.98%
              LvaTable |       1560 |   2.90%
            UnwindInfo |          0 |   0.00%
                hashBv |         40 |   0.07%
                bitset |         32 |   0.06%
          FixedBitVect |         32 |   0.06%
               Generic |       1086 |   2.02%
   LocalAddressVisitor |          0 |   0.00%
         FieldSeqStore |          0 |   0.00%
          MemorySsaMap |         80 |   0.15%
          MemoryPhiArg |          0 |   0.00%
                   CSE |       1024 |   1.91%
                    GC |       1224 |   2.28%
       CorTailCallInfo |          0 |   0.00%
              Inlining |       1304 |   2.43%
            ArrayStack |          0 |   0.00%
             DebugInfo |        192 |   0.36%
             DebugOnly |      14215 |  26.46%
               Codegen |       1224 |   2.28%
               LoopOpt |          0 |   0.00%
             LoopClone |          0 |   0.00%
             LoopHoist |          0 |   0.00%
               Unknown |        200 |   0.37%
            RangeCheck |          0 |   0.00%
              CopyProp |          0 |   0.00%
             Promotion |          0 |   0.00%
           SideEffects |          0 |   0.00%
       ObjectAllocator |          0 |   0.00%
    VariableLiveRanges |         40 |   0.07%
           ClassLayout |        128 |   0.24%
       TailMergeThrows |          0 |   0.00%
             EarlyProp |          0 |   0.00%
              ZeroInit |        104 |   0.19%
                   Pgo |          0 |   0.00%

****** DONE compiling Awaitable:Test():int

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