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predicate_registers

作成日 差分は期限切れになりません
59 削除
289 行
47 追加
281 行
; Assembly listing for method JIT.HardwareIntrinsics.Arm._Sve.TernaryOpTest__Sve_ConditionalSelect_int:RunBasicScenario_Load():this (FullOpts)
; Assembly listing for method JIT.HardwareIntrinsics.Arm._Sve.TernaryOpTest__Sve_ConditionalSelect_int:RunBasicScenario_Load():this (FullOpts)
; Emitting BLENDED_CODE for generic ARM64 - Windows
; Emitting BLENDED_CODE for generic ARM64 - Windows
; FullOpts code
; FullOpts code
; optimized code
; optimized code
; fp based frame
; fp based frame
; partially interruptible
; partially interruptible
; No matching PGO data
; No matching PGO data
; 0 inlinees with PGO data; 26 single block inlinees; 0 inlinees without PGO data
; 0 inlinees with PGO data; 26 single block inlinees; 0 inlinees without PGO data
; Final local variable assignments
; Final local variable assignments
;
;
; V00 this [V00,T02] ( 4, 4 ) ref -> x19 this class-hnd single-def <JIT.HardwareIntrinsics.Arm._Sve.TernaryOpTest__Sve_ConditionalSelect_int>
; V00 this [V00,T02] ( 4, 4 ) ref -> x19 this class-hnd single-def <JIT.HardwareIntrinsics.Arm._Sve.TernaryOpTest__Sve_ConditionalSelect_int>
; V01 loc0 [V01,T32] ( 2, 2 ) simd16 -> d8 HFA(simd16) <System.Numerics.Vector`1[int]>
; V01 loc0 [V01,T32] ( 2, 2 ) simd16 -> d8 HFA(simd16) <System.Numerics.Vector`1[int]>
; V02 loc1 [V02,T33] ( 2, 2 ) simd16 -> d8 HFA(simd16) <System.Numerics.Vector`1[int]>
; V02 loc1 [V02,T33] ( 2, 2 ) simd16 -> d8 HFA(simd16) <System.Numerics.Vector`1[int]>
;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V04 tmp1 [V04,T30] ( 2, 4 ) simd16 -> d10 "impAppendStmt"
; V04 tmp1 [V04,T30] ( 2, 4 ) simd16 -> d8 "impAppendStmt"
; V05 tmp2 [V05,T31] ( 2, 4 ) simd16 -> d9 "impAppendStmt"
; V05 tmp2 [V05,T31] ( 2, 4 ) simd16 -> d9 "impAppendStmt"
; V06 tmp3 [V06,T19] ( 2, 4 ) long -> x21 "impAppendStmt"
; V06 tmp3 [V06,T19] ( 2, 4 ) long -> x21 "impAppendStmt"
; V07 tmp4 [V07,T20] ( 2, 4 ) long -> x22 "impAppendStmt"
; V07 tmp4 [V07,T20] ( 2, 4 ) long -> x22 "impAppendStmt"
; V08 tmp5 [V08,T21] ( 2, 4 ) long -> x23 "impAppendStmt"
; V08 tmp5 [V08,T21] ( 2, 4 ) long -> x23 "impAppendStmt"
;* V09 tmp6 [V09 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" <System.String>
;* V09 tmp6 [V09 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" <System.String>
; V10 tmp7 [V10,T01] ( 4, 8 ) byref -> x21 single-def "Inlining Arg"
; V10 tmp7 [V10,T01] ( 4, 8 ) byref -> x21 single-def "Inlining Arg"
;* V11 tmp8 [V11 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
;* V11 tmp8 [V11 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
; V12 tmp9 [V12,T22] ( 2, 4 ) long -> x0 "Inlining Arg"
; V12 tmp9 [V12,T22] ( 2, 4 ) long -> x0 "Inlining Arg"
; V13 tmp10 [V13,T10] ( 3, 6 ) long -> x1 "Inlining Arg"
; V13 tmp10 [V13,T10] ( 3, 6 ) long -> x1 "Inlining Arg"
; V14 tmp11 [V14,T03] ( 3, 6 ) byref -> x21 single-def "Inlining Arg"
; V14 tmp11 [V14,T03] ( 3, 6 ) byref -> x21 single-def "Inlining Arg"
;* V15 tmp12 [V15 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
;* V15 tmp12 [V15 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
; V16 tmp13 [V16,T23] ( 2, 4 ) long -> x0 "Inlining Arg"
; V16 tmp13 [V16,T23] ( 2, 4 ) long -> x0 "Inlining Arg"
; V17 tmp14 [V17,T11] ( 3, 6 ) long -> x1 "Inlining Arg"
; V17 tmp14 [V17,T11] ( 3, 6 ) long -> x1 "Inlining Arg"
; V18 tmp15 [V18,T04] ( 3, 6 ) byref -> x21 single-def "Inlining Arg"
; V18 tmp15 [V18,T04] ( 3, 6 ) byref -> x21 single-def "Inlining Arg"
;* V19 tmp16 [V19 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
;* V19 tmp16 [V19 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
; V20 tmp17 [V20,T24] ( 2, 4 ) long -> x0 "Inlining Arg"
; V20 tmp17 [V20,T24] ( 2, 4 ) long -> x0 "Inlining Arg"
; V21 tmp18 [V21,T12] ( 3, 6 ) long -> x1 "Inlining Arg"
; V21 tmp18 [V21,T12] ( 3, 6 ) long -> x1 "Inlining Arg"
; V22 tmp19 [V22,T05] ( 3, 6 ) byref -> x21 single-def "Inlining Arg"
; V22 tmp19 [V22,T05] ( 3, 6 ) byref -> x21 single-def "Inlining Arg"
;* V23 tmp20 [V23 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
;* V23 tmp20 [V23 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
; V24 tmp21 [V24,T25] ( 2, 4 ) long -> x0 "Inlining Arg"
; V24 tmp21 [V24,T25] ( 2, 4 ) long -> x0 "Inlining Arg"
; V25 tmp22 [V25,T13] ( 3, 6 ) long -> x1 "Inlining Arg"
; V25 tmp22 [V25,T13] ( 3, 6 ) long -> x1 "Inlining Arg"
; V26 tmp23 [V26,T06] ( 3, 6 ) byref -> x21 single-def "Inlining Arg"
; V26 tmp23 [V26,T06] ( 3, 6 ) byref -> x21 single-def "Inlining Arg"
;* V27 tmp24 [V27 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
;* V27 tmp24 [V27 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
; V28 tmp25 [V28,T26] ( 2, 4 ) long -> x0 "Inlining Arg"
; V28 tmp25 [V28,T26] ( 2, 4 ) long -> x0 "Inlining Arg"
; V29 tmp26 [V29,T14] ( 3, 6 ) long -> x1 "Inlining Arg"
; V29 tmp26 [V29,T14] ( 3, 6 ) long -> x1 "Inlining Arg"
; V30 tmp27 [V30,T07] ( 3, 6 ) byref -> x22 single-def "Inlining Arg"
; V30 tmp27 [V30,T07] ( 3, 6 ) byref -> x22 single-def "Inlining Arg"
;* V31 tmp28 [V31 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
;* V31 tmp28 [V31 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
; V32 tmp29 [V32,T27] ( 2, 4 ) long -> x0 "Inlining Arg"
; V32 tmp29 [V32,T27] ( 2, 4 ) long -> x0 "Inlining Arg"
; V33 tmp30 [V33,T15] ( 3, 6 ) long -> x1 "Inlining Arg"
; V33 tmp30 [V33,T15] ( 3, 6 ) long -> x1 "Inlining Arg"
; V34 tmp31 [V34,T08] ( 3, 6 ) byref -> x23 single-def "Inlining Arg"
; V34 tmp31 [V34,T08] ( 3, 6 ) byref -> x23 single-def "Inlining Arg"
;* V35 tmp32 [V35 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
;* V35 tmp32 [V35 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
; V36 tmp33 [V36,T28] ( 2, 4 ) long -> x0 "Inlining Arg"
; V36 tmp33 [V36,T28] ( 2, 4 ) long -> x0 "Inlining Arg"
; V37 tmp34 [V37,T16] ( 3, 6 ) long -> x1 "Inlining Arg"
; V37 tmp34 [V37,T16] ( 3, 6 ) long -> x1 "Inlining Arg"
; V38 tmp35 [V38,T09] ( 3, 6 ) byref -> x20 single-def "Inlining Arg"
; V38 tmp35 [V38,T09] ( 3, 6 ) byref -> x20 single-def "Inlining Arg"
;* V39 tmp36 [V39 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
;* V39 tmp36 [V39 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline stloc first use temp"
; V40 tmp37 [V40,T29] ( 2, 4 ) long -> x0 "Inlining Arg"
; V40 tmp37 [V40,T29] ( 2, 4 ) long -> x0 "Inlining Arg"
; V41 tmp38 [V41,T17] ( 3, 6 ) long -> x4 "Inlining Arg"
; V41 tmp38 [V41,T17] ( 3, 6 ) long -> x4 "Inlining Arg"
; V42 cse0 [V42,T00] ( 9, 9 ) byref -> x20 "CSE #01: aggressive"
; V42 cse0 [V42,T00] ( 9, 9 ) byref -> x20 "CSE #01: aggressive"
; V43 cse1 [V43,T18] ( 4, 4 ) mask -> d8 "CSE #02: moderate"
; V43 cse1 [V43,T18] ( 4, 4 ) mask -> p0 "CSE #02: moderate"
;
;
; Lcl frame size = 0
; Lcl frame size = 8


G_M58422_IG01: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M58422_IG01: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
stp fp, lr, [sp, #-0x60]!
stp fp, lr, [sp, #-0x60]!
stp d8, d9, [sp, #0x10]
stp d8, d9, [sp, #0x18]
stp d10, d11, [sp, #0x20]
stp d10, d11, [sp, #0x28]
str d12, [sp, #0x30]
stp x19, x20, [sp, #0x38]
stp x19, x20, [sp, #0x38]
stp x21, x22, [sp, #0x48]
stp x21, x22, [sp, #0x48]
str x23, [sp, #0x58]
str x23, [sp, #0x58]
mov fp, sp
mov fp, sp
mov x19, x0
mov x19, x0
; gcrRegs +[x19]
; gcrRegs +[x19]
;; size=36 bbWeight=1 PerfScore 8.00
;; size=32 bbWeight=1 PerfScore 7.00
G_M58422_IG02: ; bbWeight=1, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, byref
G_M58422_IG02: ; bbWeight=1, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, byref
movz x0, #0xD1FFAB1E
movz x0, #0xD1FFAB1E
movk x0, #0xD1FFAB1E LSL #16
movk x0, #0xD1FFAB1E LSL #16
movk x0, #0xD1FFAB1E LSL #32
movk x0, #0xD1FFAB1E LSL #32
movz x1, #0xD1FFAB1E
movz x1, #0xD1FFAB1E
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #32
movk x1, #0xD1FFAB1E LSL #32
movz x2, #0xD1FFAB1E // code for <unknown method>
movz x2, #0xD1FFAB1E // code for <unknown method>
movk x2, #0xD1FFAB1E LSL #16
movk x2, #0xD1FFAB1E LSL #16
movk x2, #0xD1FFAB1E LSL #32
movk x2, #0xD1FFAB1E LSL #32
ldr x2, [x2]
ldr x2, [x2]
blr x2
blr x2
; gcrRegs +[x0]
; gcrRegs +[x0]
movz x1, #0xD1FFAB1E // code for <unknown method>
movz x1, #0xD1FFAB1E // code for <unknown method>
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #32
movk x1, #0xD1FFAB1E LSL #32
ldr x1, [x1]
ldr x1, [x1]
blr x1
blr x1
; gcrRegs -[x0]
; gcrRegs -[x0]
ptrue p7.s
ptrue p0.s
mov z8.s, p7/z, #1
mov z8.s, p0/z, #1
add x20, x19, #64
add x20, x19, #64
; byrRegs +[x20]
; byrRegs +[x20]
mov x21, x20
mov x21, x20
; byrRegs +[x21]
; byrRegs +[x21]
ldrsb wzr, [x21]
ldrsb wzr, [x21]
add x0, x21, #40
add x0, x21, #40
; byrRegs +[x0]
; byrRegs +[x0]
movz x1, #0xD1FFAB1E // code for <unknown method>
movz x1, #0xD1FFAB1E // code for <unknown method>
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #32
movk x1, #0xD1FFAB1E LSL #32
ldr x1, [x1]
ldr x1, [x1]
mov v9.d[0], v8.d[1]
mov v9.d[0], v8.d[1]
blr x1
blr x1
; byrRegs -[x0]
; byrRegs -[x0]
ldr x1, [x21, #0x20]
ldr x1, [x21, #0x20]
add x0, x0, x1
add x0, x0, x1
sub x0, x0, #1
sub x0, x0, #1
sub x1, x1, #1
sub x1, x1, #1
bic x0, x0, x1
bic x0, x0, x1
ptrue p7.s
ptrue p0.s
mov v8.d[1], v9.d[0]
mov v8.d[1], v9.d[0]
cmpne p8.s, p7/z, z8.s, #0
cmpne p0.s, p0/z, z8.s, #0
mov p7.b, p8.b
ld1w { z8.s }, p0/z, [x0]
ld1w { z10.s }, p7/z, [x0]
mov x21, x20
mov x21, x20
add x0, x21, #48
add x0, x21, #48
; byrRegs +[x0]
; byrRegs +[x0]
movz x1, #0xD1FFAB1E // code for <unknown method>
movz x1, #0xD1FFAB1E // code for <unknown method>
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #32
movk x1, #0xD1FFAB1E LSL #32
ldr x1, [x1]
ldr x1, [x1]
mov v11.d[0], v10.d[1]
mov v10.d[0], v8.d[1]
blr x1
blr x1
; byrRegs -[x0]
; byrRegs -[x0]
ldr x1, [x21, #0x20]
ldr x1, [x21, #0x20]
add x0, x0, x1
add x0, x0, x1
sub x0, x0, #1
sub x0, x0, #1
sub x1, x1, #1
sub x1, x1, #1
bic x0, x0, x1
bic x0, x0, x1
mov p7.b, p8.b
ld1w { z9.s }, p0/z, [x0]
ld1w { z9.s }, p7/z, [x0]
mov x21, x20
mov x21, x20
add x0, x21, #56
add x0, x21, #56
; byrRegs +[x0]
; byrRegs +[x0]
movz x1, #0xD1FFAB1E // code for <unknown method>
movz x1, #0xD1FFAB1E // code for <unknown method>
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #32
movk x1, #0xD1FFAB1E LSL #32
ldr x1, [x1]
ldr x1, [x1]
mov v12.d[0], v9.d[1]
mov v11.d[0], v9.d[1]
blr x1
blr x1
; byrRegs -[x0]
; byrRegs -[x0]
ldr x1, [x21, #0x20]
ldr x1, [x21, #0x20]
ptrue p7.s
ptrue p1.s
mov v10.d[1], v11.d[0]
mov v8.d[1], v10.d[0]
cmpne p7.s, p7/z, z10.s, #0
cmpne p1.s, p1/z, z8.s, #0
add x0, x0, x1
add x0, x0, x1
sub x0, x0, #1
sub x0, x0, #1
sub x1, x1, #1
sub x1, x1, #1
bic x0, x0, x1
bic x0, x0, x1
mov p6.b, p8.b
ld1w { z16.s }, p0/z, [x0]
ld1w { z16.s }, p6/z, [x0]
mov v9.d[1], v11.d[0]
mov v9.d[1], v12.d[0]
sel z8.s, p1, z9.s, z16.s
sel z8.s, p7, z9.s, z16.s
mov x21, x20
mov x21, x20
add x0, x21, #64
add x0, x21, #64
; byrRegs +[x0]
; byrRegs +[x0]
movz x1, #0xD1FFAB1E // code for <unknown method>
movz x1, #0xD1FFAB1E // code for <unknown method>
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #32
movk x1, #0xD1FFAB1E LSL #32
ldr x1, [x1]
ldr x1, [x1]
mov v9.d[0], v8.d[1]
mov v9.d[0], v8.d[1]
blr x1
blr x1
; byrRegs -[x0]
; byrRegs -[x0]
ldr x1, [x21, #0x20]
ldr x1, [x21, #0x20]
add x0, x0, x1
add x0, x0, x1
sub x0, x0, #1
sub x0, x0, #1
sub x1, x1, #1
sub x1, x1, #1
bic x0, x0, x1
bic x0, x0, x1
mov v8.d[1], v9.d[0]
mov v8.d[1], v9.d[0]
str q8, [x0]
str q8, [x0]
mov x21, x20
mov x21, x20
add x0, x21, #40
add x0, x21, #40
; byrRegs +[x0]
; byrRegs +[x0]
movz x1, #0xD1FFAB1E // code for <unknown method>
movz x1, #0xD1FFAB1E // code for <unknown method>
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #32
movk x1, #0xD1FFAB1E LSL #32
ldr x1, [x1]
ldr x1, [x1]
blr x1
blr x1
; byrRegs -[x0]
; byrRegs -[x0]
ldr x1, [x21, #0x20]
ldr x1, [x21, #0x20]
add x0, x0, x1
add x0, x0, x1
sub x0, x0, #1
sub x0, x0, #1
sub x1, x1, #1
sub x1, x1, #1
bic x21, x0, x1
bic x21, x0, x1
; byrRegs -[x21]
; byrRegs -[x21]
mov x22, x20
mov x22, x20
; byrRegs +[x22]
; byrRegs +[x22]
add x0, x22, #48
add x0, x22, #48
; byrRegs +[x0]
; byrRegs +[x0]
movz x1, #0xD1FFAB1E // code for <unknown method>
movz x1, #0xD1FFAB1E // code for <unknown method>
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #32
movk x1, #0xD1FFAB1E LSL #32
ldr x1, [x1]
ldr x1, [x1]
blr x1
blr x1
; byrRegs -[x0]
; byrRegs -[x0]
ldr x1, [x22, #0x20]
ldr x1, [x22, #0x20]
add x0, x0, x1
add x0, x0, x1
sub x0, x0, #1
sub x0, x0, #1
sub x1, x1, #1
sub x1, x1, #1
bic x22, x0, x1
bic x22, x0, x1
; byrRegs -[x22]
; byrRegs -[x22]
mov x23, x20
mov x23, x20
; byrRegs +[x23]
; byrRegs +[x23]
add x0, x23, #56
add x0, x23, #56
; byrRegs +[x0]
; byrRegs +[x0]
movz x1, #0xD1FFAB1E // code for <unknown method>
movz x1, #0xD1FFAB1E // code for <unknown method>
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #32
movk x1, #0xD1FFAB1E LSL #32
ldr x1, [x1]
ldr x1, [x1]
blr x1
blr x1
; byrRegs -[x0]
; byrRegs -[x0]
ldr x1, [x23, #0x20]
ldr x1, [x23, #0x20]
add x0, x0, x1
add x0, x0, x1
sub x0, x0, #1
sub x0, x0, #1
sub x1, x1, #1
sub x1, x1, #1
bic x23, x0, x1
bic x23, x0, x1
; byrRegs -[x23]
; byrRegs -[x23]
add x0, x20, #64
add x0, x20, #64
; byrRegs +[x0]
; byrRegs +[x0]
movz x1, #0xD1FFAB1E // code for <unknown method>
movz x1, #0xD1FFAB1E // code for <unknown method>
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #16
movk x1, #0xD1FFAB1E LSL #32
movk x1, #0xD1FFAB1E LSL #32
ldr x1, [x1]
ldr x1, [x1]
blr x1
blr x1
; byrRegs -[x0]
; byrRegs -[x0]
ldr x4, [x20, #0x20]
ldr x4, [x20, #0x20]
add x0, x0, x4
add x0, x0, x4
sub x0, x0, #1
sub x0, x0, #1
sub x4, x4, #1
sub x4, x4, #1
bic x4, x0, x4
bic x4, x0, x4
mov x0, x19
mov x0, x19
; gcrRegs +[x0]
; gcrRegs +[x0]
mov x1, x21
mov x1, x21
mov x2, x22
mov x2, x22
mov x3, x23
mov x3, x23
movz x5, #0xD1FFAB1E
movz x5, #0xD1FFAB1E
movk x5, #0xD1FFAB1E LSL #16
movk x5, #0xD1FFAB1E LSL #16
movk x5, #0xD1FFAB1E LSL #32
movk x5, #0xD1FFAB1E LSL #32
movz x6, #0xD1FFAB1E // code for <unknown method>
movz x6, #0xD1FFAB1E // code for <unknown method>
movk x6, #0xD1FFAB1E LSL #16
movk x6, #0xD1FFAB1E LSL #16
movk x6, #0xD1FFAB1E LSL #32
movk x6, #0xD1FFAB1E LSL #32
ldr x6, [x6]
ldr x6, [x6]
blr x6
blr x6
; gcrRegs -[x0 x19]
; gcrRegs -[x0 x19]
; byrRegs -[x20]
; byrRegs -[x20]
;; size=588 bbWeight=1 PerfScore 173.00
;; size=576 bbWeight=1 PerfScore 167.00
G_M58422_IG03: ; bbWeight=1, epilog, nogc, extend
G_M58422_IG03: ; bbWeight=1, epilog, nogc, extend
ldr x23, [sp, #0x58]
ldr x23, [sp, #0x58]
ldp x21, x22, [sp, #0x48]
ldp x21, x22, [sp, #0x48]
ldp x19, x20, [sp, #0x38]
ldp x19, x20, [sp, #0x38]
ldr d12, [sp, #0x30]
ldp d10, d11, [sp, #0x28]
ldp d10, d11, [sp, #0x20]
ldp d8, d9, [sp, #0x18]
ldp d8, d9, [sp, #0x10]
ldp fp, lr, [sp], #0x60
ldp fp, lr, [sp], #0x60
ret lr
ret lr
;; size=32 bbWeight=1 PerfScore 10.00
;; size=28 bbWeight=1 PerfScore 8.00


; Total bytes of code 656, prolog size 32, PerfScore 191.00, instruction count 164, allocated bytes for code 656 (MethodHash=74bf1bc9) for method JIT.HardwareIntrinsics.Arm._Sve.TernaryOpTest__Sve_ConditionalSelect_int:RunBasicScenario_Load():this (FullOpts)
; Total bytes of code 636, prolog size 28, PerfScore 182.00, instruction count 159, allocated bytes for code 636 (MethodHash=74bf1bc9) for method JIT.HardwareIntrinsics.Arm._Sve.TernaryOpTest__Sve_ConditionalSelect_int:RunBasicScenario_Load():this (FullOpts)
; ============================================================
; ============================================================


Unwind Info:
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0xd1ffab1e (not in unwind data)
>> End offset : 0xd1ffab1e (not in unwind data)
Code Words : 4
Code Words : 3
Epilog Count : 1
Epilog Count : 1
E bit : 0
E bit : 0
X bit : 0
X bit : 0
Vers : 0
Vers : 0
Function Length : 164 (0x000a4) Actual length = 656 (0x000290)
Function Length : 159 (0x0009f) Actual length = 636 (0x00027c)
---- Epilog scopes ----
---- Epilog scopes ----
---- Scope 0
---- Scope 0
Epilog Start Offset : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)
Epilog Start Offset : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)
Epilog Start Index : 1 (0x01)
Epilog Start Index : 1 (0x01)
---- Unwind codes ----
---- Unwind codes ----
E1 set_fp; mov fp, sp
E1 set_fp; mov fp, sp
---- Epilog start at index 1 ----
---- Epilog start at index 1 ----
D1 0B save_reg X#4 Z#11 (0x0B); str x23, [sp, #88]
D1 0B save_reg X#4 Z#11 (0x0B); str x23, [sp, #88]
E6 save_next
E6 save_next
C8 07 save_regp X#0 Z#7 (0x07); stp x19, x20, [sp, #56]
C8 07 save_regp X#0 Z#7 (0x07); stp x19, x20, [sp, #56]
DD 06 save_freg X#4 Z#6 (0x06); str d12, [sp, #48]
E6 save_next
E6 save_next
D8 02 save_fregp X#0 Z#2 (0x02); stp d8, d9, [sp, #16]
D8 03 save_fregp X#0 Z#3 (0x03); stp d8, d9, [sp, #24]
8B save_fplr_x #11 (0x0B); stp fp, lr, [sp, #-96]!
8B save_fplr_x #11 (0x0B); stp fp, lr, [sp, #-96]!
E4 end
E4 end
E4 end
E4 end
E4 end
E4 end




保存された差分