Untitled Diff
8 removals
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Total | 148 |
Removed | -2.7%4 |
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Total | 693 |
Removed | -1.9%13 |
148 lines
7 additions
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Total | 147 |
Added | +2.0%3 |
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Total | 689 |
Added | +1.3%9 |
147 lines
; Assembly listing for method ILGEN_CLASS:ILGEN_METHOD(ubyte,long,int):long
; Assembly listing for method ILGEN_CLASS:ILGEN_METHOD(ubyte,long,int):long
; Emitting BLENDED_CODE for generic ARM64 CPU - Unix
; Emitting BLENDED_CODE for generic ARM64 CPU - Unix
; optimized code
; optimized code
; fp based frame
; fp based frame
; partially interruptible
; partially interruptible
; No matching PGO data
; No matching PGO data
; Final local variable assignments
; Final local variable assignments
;
;
; V00 arg0 [V00,T01] ( 3, 3 ) ubyte -> x20 single-def
; V00 arg0 [V00,T01] ( 3, 3 ) ubyte -> x20 single-def
; V01 arg1 [V01,T02] ( 3, 3 ) long -> x21
; V01 arg1 [V01,T02] ( 3, 3 ) long -> x21
; V02 arg2 [V02,T00] ( 5, 5 ) int -> x19
; V02 arg2 [V02,T00] ( 5, 5 ) int -> x19
;* V03 loc0 [V03 ] ( 0, 0 ) byte -> zero-ref
;* V03 loc0 [V03 ] ( 0, 0 ) byte -> zero-ref
; V04 loc1 [V04,T08] ( 2, 2 ) double -> [fp+10H] must-init
; V04 loc1 [V04,T08] ( 2, 2 ) double -> [fp+10H] must-init
;# V05 OutArgs [V05 ] ( 1, 1 ) lclBlk ( 0) [sp+00H] "OutgoingArgSpace"
;# V05 OutArgs [V05 ] ( 1, 1 ) lclBlk ( 0) [sp+00H] "OutgoingArgSpace"
;* V06 tmp1 [V06,T07] ( 0, 0 ) int -> zero-ref "impSpillLclRefs"
;* V06 tmp1 [V06,T07] ( 0, 0 ) int -> zero-ref "impSpillLclRefs"
; V07 tmp2 [V07,T04] ( 2, 4 ) int -> x21 "impAppendStmt"
; V07 tmp2 [V07,T04] ( 2, 4 ) int -> x21 "impAppendStmt"
;* V08 tmp3 [V08 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
;* V08 tmp3 [V08 ] ( 0, 0 ) int -> zero-ref "impAppendStmt"
;* V09 tmp4 [V09 ] ( 0, 0 ) int -> zero-ref "impSpillLclRefs"
;* V09 tmp4 [V09 ] ( 0, 0 ) int -> zero-ref "impSpillLclRefs"
; V10 cse0 [V10,T06] ( 2, 2 ) int -> x0 "CSE - aggressive"
; V10 cse0 [V10,T06] ( 2, 2 ) int -> x0 "CSE - aggressive"
; V11 cse1 [V11,T03] ( 4, 4 ) long -> x1 "CSE - aggressive"
; V11 cse1 [V11,T03] ( 4, 4 ) long -> x1 "CSE - aggressive"
; V12 cse2 [V12,T05] ( 3, 3 ) int -> x20 "CSE - aggressive"
; V12 cse2 [V12,T05] ( 3, 3 ) int -> x20 "CSE - aggressive"
;
;
; Lcl frame size = 8
; Lcl frame size = 8
G_M16326_IG01: ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M16326_IG01: ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
stp fp, lr, [sp,#-48]!
stp fp, lr, [sp,#-48]!
stp x19, x20, [sp,#24]
stp x19, x20, [sp,#24]
str x21, [sp,#40]
str x21, [sp,#40]
mov fp, sp
mov fp, sp
mov w20, w0
mov w20, w0
mov x21, x1
mov x21, x1
mov w19, w2
mov w19, w2
movi v0.16b, #0x00
movi v0.16b, #0x00
;; bbWeight=1 PerfScore 5.50
;; bbWeight=1 PerfScore 5.50
G_M16326_IG02: ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, isz
G_M16326_IG02: ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, isz
str d0, [fp,#16]
str d0, [fp,#16]
bl CORINFO_HELP_DBL2INT_OVF
bl CORINFO_HELP_DBL2INT_OVF
cmp w0, #255
cmp w0, #255
bhi G_M16326_IG05
bhi G_M16326_IG05
cmp x21, #0
cmp x21, #0
cset x1, ne
cset x1, ne
and w0, w0, w1
and w0, w0, w1
scvtf d0, w0
scvtf d0, w0
bl CORINFO_HELP_DBL2LNG_OVF
bl CORINFO_HELP_DBL2LNG_OVF
ldr d0, [@RWD00]
ldr d0, [@RWD00]
bl CORINFO_HELP_DBL2UINT_OVF
bl CORINFO_HELP_DBL2UINT_OVF
mov w21, w0
mov w21, w0
mov w0, #0
mov w0, #0
bl CORINFO_HELP_OVERFLOW
bl CORINFO_HELP_OVERFLOW
mov w0, #0
mov w0, #0
cmp w21, #0
cmp w21, #0
beq G_M16326_IG06
beq G_M16326_IG06
udiv w0, w0, w21
udiv w0, w0, w21
mov w19, wzr
mov w19, wzr
mov w0, #0
mov w0, #0
bl CORINFO_HELP_OVERFLOW
bl CORINFO_HELP_OVERFLOW
mov w0, #0
mov w0, #0
sxtw x21, w0
sxtw x21, w0
ldr d0, [fp,#16] // [V04 loc1]
ldr d0, [fp,#16] // [V04 loc1]
fcvt s0, d0
fcvt s0, d0
fcvt d0, s0
fcvt d0, s0
bl CORINFO_HELP_DBL2LNG_OVF
bl CORINFO_HELP_DBL2LNG_OVF
uxtb w20, w20
uxtb w20, w20
lsr x0, x0, x20
lsr x0, x0, x20
smulh x1, x21, x0
smulh x1, x21, x0
mul x0, x21, x0
mul x0, x21, x0
cmp x1, x0, ASR #63
cmp x1, x0, ASR #63
bne G_M16326_IG05
bne G_M16326_IG05
ldr d0, [@RWD08]
ldr d0, [@RWD08]
bl CORINFO_HELP_DBL2INT_OVF
bl CORINFO_HELP_DBL2INT_OVF
cmp w0, #127
cmp w0, #127
bgt G_M16326_IG05
bgt G_M16326_IG05
cmn w0, #128
cmn w0, #128
blt G_M16326_IG05
blt G_M16326_IG05
cmp w20, #0
cmp w20, #0
cset x0, lt
cset x0, lt
mvn w0, w0
mvn w0, w0
cmp w19, #0
cmp w19, #0
beq G_M16326_IG06
beq G_M16326_IG06
cmn w19, #1
cmn w19, #1
bne G_M16326_IG03
bne G_M16326_IG03
adds wzr, w19, w19
adds wzr, w19, w19
bne G_M16326_IG03
bne G_M16326_IG03
bvs G_M16326_IG05
bvs G_M16326_IG05
;; bbWeight=1 PerfScore 63.00
;; bbWeight=1 PerfScore 63.00
G_M16326_IG03: ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, isz
G_M16326_IG03: ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, isz
sdiv w1, w19, w19
sdiv w1, w19, w19
lsl w0, w0, #0
cmp w0, #16, LSL #12
cmp w0, #16, LSL #12
bhs G_M16326_IG05
bhs G_M16326_IG05
movz x1, #0xd1ffab1e
movz x1, #0xd1ffab1e
movk x1, #0xd1ffab1e LSL #16
movk x1, #0xd1ffab1e LSL #16
movk x1, #0xd1ffab1e LSL #32
movk x1, #0xd1ffab1e LSL #32
movk x1, #0xd1ffab1e LSL #48
movk x1, #0xd1ffab1e LSL #48
asr x0, x1, x0
asr x0, x1, x0
cmp x0, x1
cmp x0, x1
cset x0, lt
cset x0, lt
ldr d16, [@RWD16]
ldr d16, [@RWD16]
fcvtzu w2, d16
fcvtzu w2, d16
cmp w2, #0
cmp w2, #0
beq G_M16326_IG06
beq G_M16326_IG06
udiv w0, w0, w2
udiv w0, w0, w2
mov x0, x1
mov x0, x1
;; bbWeight=1 PerfScore 34.00
;; bbWeight=1 PerfScore 33.00
G_M16326_IG04: ; , epilog, nogc, extend
G_M16326_IG04: ; , epilog, nogc, extend
ldr x21, [sp,#40]
ldr x21, [sp,#40]
ldp x19, x20, [sp,#24]
ldp x19, x20, [sp,#24]
ldp fp, lr, [sp],#48
ldp fp, lr, [sp],#48
ret lr
ret lr
;; bbWeight=1 PerfScore 5.00
;; bbWeight=1 PerfScore 5.00
G_M16326_IG05: ; gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, gcvars, byref
G_M16326_IG05: ; gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, gcvars, byref
bl CORINFO_HELP_OVERFLOW
bl CORINFO_HELP_OVERFLOW
;; bbWeight=0 PerfScore 0.00
;; bbWeight=0 PerfScore 0.00
G_M16326_IG06: ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
G_M16326_IG06: ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
bl CORINFO_HELP_THROWDIVZERO
bl CORINFO_HELP_THROWDIVZERO
brk #0
brk #0
;; bbWeight=0 PerfScore 0.00
;; bbWeight=0 PerfScore 0.00
RWD00 dq 7FF8000000000000h ; nan
RWD00 dq 7FF8000000000000h ; nan
RWD08 dq FFF8000000000000h ; -nan(ind)
RWD08 dq FFF8000000000000h ; -nan(ind)
RWD16 dq 739233EAE9C3B79Ah ; 5.09090169e+248
RWD16 dq 739233EAE9C3B79Ah ; 5.09090169e+248
; Total bytes of code 324, prolog size 16, PerfScore 139.90, instruction count 81, allocated bytes for code 324 (MethodHash=8874c039) for method ILGEN_CLASS:ILGEN_METHOD(ubyte,long,int):long
; Total bytes of code 320, prolog size 16, PerfScore 138.50, instruction count 80, allocated bytes for code 320 (MethodHash=8874c039) for method ILGEN_CLASS:ILGEN_METHOD(ubyte,long,int):long
; ============================================================
; ============================================================
Unwind Info:
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0xd1ffab1e (not in unwind data)
>> End offset : 0xd1ffab1e (not in unwind data)
Code Words : 2
Code Words : 2
Epilog Count : 1
Epilog Count : 1
E bit : 0
E bit : 0
X bit : 0
X bit : 0
Vers : 0
Vers : 0
Function Length : 81 (0x00051) Actual length = 324 (0x000144)
Function Length : 80 (0x00050) Actual length = 320 (0x000140)
---- Epilog scopes ----
---- Epilog scopes ----
---- Scope 0
---- Scope 0
Epilog Start Offset : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)
Epilog Start Offset : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)
Epilog Start Index : 1 (0x01)
Epilog Start Index : 1 (0x01)
---- Unwind codes ----
---- Unwind codes ----
E1 set_fp; mov fp, sp
E1 set_fp; mov fp, sp
---- Epilog start at index 1 ----
---- Epilog start at index 1 ----
D0 85 save_reg X#2 Z#5 (0x05); str x21, [sp, #40]
D0 85 save_reg X#2 Z#5 (0x05); str x21, [sp, #40]
C8 03 save_regp X#0 Z#3 (0x03); stp x19, x20, [sp, #24]
C8 03 save_regp X#0 Z#3 (0x03); stp x19, x20, [sp, #24]
85 save_fplr_x #5 (0x05); stp fp, lr, [sp, #-48]!
85 save_fplr_x #5 (0x05); stp fp, lr, [sp, #-48]!
E4 end
E4 end
E4 end
E4 end