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创建于 7年前差异永不过期

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#include "F28x_Project.h"

void scib_echoback_init(void);

void scib_fifo_init(void);

void scib_xmit(int a);

void scib_msg(char *msg);

void main(void)

{

char *msg;

InitSysCtrl();

// GPIO

InitGpio();

EALLOW;

// Set the mux to SCITXDB on GPIO 18

// Set the mux to SCITXDB on GPIO 29

GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0;

GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 0;

GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2;

GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1;

// Select CPU 1

GpioCtrlRegs.GPACSEL3.bit.GPIO18 = 0;

GpioCtrlRegs.GPACSEL4.bit.GPIO29 = 0;

// Async mode

GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3;

GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3;

EDIS;

// Interrupts

DINT;

InitPieCtrl();

IER = 0x0000;

IFR = 0x0000;

InitPieVectTable();

EINT;

// SCI

scib_fifo_init();

scib_echoback_init();

for (;;) {

msg = "Salut\n\0";

scib_msg(msg);

}

void scib_echoback_init()

{

ScibRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback

SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback

// No parity,8 char bits,

// async mode, idle-line protocol

ScibRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK,

SciaRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK,

// Disable RX ERR, SLEEP, TXWAKE

ScibRegs.SCICTL2.all = 0x0003; // Enable RXBKINTENA and TXINTENA

SciaRegs.SCICTL2.all = 0x0003; // Enable RXBKINTENA and TXINTENA

// SCIB at 9600 baud

// @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B.

// @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86.

ScibRegs.SCIHBAUD.all = 0x0002;

SciaRegs.SCIHBAUD.all = 0x0002;

ScibRegs.SCILBAUD.all = 0x008B;

SciaRegs.SCILBAUD.all = 0x008B;

ScibRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset

SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset

}

void scib_xmit(int a)

{

while (ScibRegs.SCIFFTX.bit.TXFFST != 0) {}

while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}

ScibRegs.SCITXBUF.all =a;

SciaRegs.SCITXBUF.all =a;

}

void scib_msg(char * msg)

{

int i;

i = 0;

while(msg[i] != '\0')

{

scib_xmit(msg[i]);

i++;

}

void scib_fifo_init()

{

ScibRegs.SCIFFTX.all = 0xE040;

SciaRegs.SCIFFTX.all = 0xE040;

ScibRegs.SCIFFRX.all = 0x2044;

SciaRegs.SCIFFRX.all = 0x2044;

ScibRegs.SCIFFCT.all = 0x0;

SciaRegs.SCIFFCT.all = 0x0;

}

已保存差异

原始文本

打开文件

#include "F28x_Project.h"

void scib_echoback_init(void);
void scib_fifo_init(void);
void scib_xmit(int a);
void scib_msg(char *msg);

void main(void)
{
    char *msg;

InitSysCtrl();

// GPIO
    InitGpio();

EALLOW;
    // Set the mux to SCITXDB on GPIO 18
    GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0;
    GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2;
    // Select CPU 1
    GpioCtrlRegs.GPACSEL3.bit.GPIO18 = 0;
    // Async mode
    GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3;
    EDIS;

// Interrupts
    DINT;
    InitPieCtrl();
    IER = 0x0000;
    IFR = 0x0000;
    InitPieVectTable();
    EINT;

// SCI
    scib_fifo_init();
    scib_echoback_init();

for (;;) {
        msg = "Salut\n\0";
        scib_msg(msg);
    }
}

void scib_echoback_init()
{
    ScibRegs.SCICCR.all = 0x0007;   // 1 stop bit,  No loopback
                                    // No parity,8 char bits,
                                    // async mode, idle-line protocol
    ScibRegs.SCICTL1.all = 0x0003;  // enable TX, RX, internal SCICLK,
                                    // Disable RX ERR, SLEEP, TXWAKE
    ScibRegs.SCICTL2.all = 0x0003;  // Enable RXBKINTENA and TXINTENA

//
    // SCIB at 9600 baud
    // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B.
    // @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86.
    //
    ScibRegs.SCIHBAUD.all = 0x0002;
    ScibRegs.SCILBAUD.all = 0x008B;

ScibRegs.SCICTL1.all = 0x0023;  // Relinquish SCI from Reset
}

void scib_xmit(int a)
{
    while (ScibRegs.SCIFFTX.bit.TXFFST != 0) {}
    ScibRegs.SCITXBUF.all =a;
}

void scib_msg(char * msg)
{
    int i;
    i = 0;
    while(msg[i] != '\0')
    {
        scib_xmit(msg[i]);
        i++;
    }
}

void scib_fifo_init()
{
    ScibRegs.SCIFFTX.all = 0xE040;
    ScibRegs.SCIFFRX.all = 0x2044;
    ScibRegs.SCIFFCT.all = 0x0;
}

更改后文本

打开文件

#include "F28x_Project.h"

void scib_echoback_init(void);
void scib_fifo_init(void);
void scib_xmit(int a);
void scib_msg(char *msg);

void main(void)
{
    char *msg;

InitSysCtrl();

// GPIO
    InitGpio();

EALLOW;
    // Set the mux to SCITXDB on GPIO 29
    GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 0;
    GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1;
    // Select CPU 1
    GpioCtrlRegs.GPACSEL4.bit.GPIO29 = 0;
    // Async mode
    GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3;
    EDIS;

// Interrupts
    DINT;
    InitPieCtrl();
    IER = 0x0000;
    IFR = 0x0000;
    InitPieVectTable();
    EINT;

// SCI
    scib_fifo_init();
    scib_echoback_init();

for (;;) {
        msg = "Salut\n\0";
        scib_msg(msg);
    }
}

void scib_echoback_init()
{
    SciaRegs.SCICCR.all = 0x0007;   // 1 stop bit,  No loopback
                                    // No parity,8 char bits,
                                    // async mode, idle-line protocol
    SciaRegs.SCICTL1.all = 0x0003;  // enable TX, RX, internal SCICLK,
                                    // Disable RX ERR, SLEEP, TXWAKE
    SciaRegs.SCICTL2.all = 0x0003;  // Enable RXBKINTENA and TXINTENA

//
    // SCIB at 9600 baud
    // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B.
    // @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86.
    //
    SciaRegs.SCIHBAUD.all = 0x0002;
    SciaRegs.SCILBAUD.all = 0x008B;

SciaRegs.SCICTL1.all = 0x0023;  // Relinquish SCI from Reset
}

void scib_xmit(int a)
{
    while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}
    SciaRegs.SCITXBUF.all =a;
}

void scib_msg(char * msg)
{
    int i;
    i = 0;
    while(msg[i] != '\0')
    {
        scib_xmit(msg[i]);
        i++;
    }
}

void scib_fifo_init()
{
    SciaRegs.SCIFFTX.all = 0xE040;
    SciaRegs.SCIFFRX.all = 0x2044;
    SciaRegs.SCIFFCT.all = 0x0;
}