serial CRC verilog implementation
创建于 差异永不过期
module crc_serial_optimized(clk, reset, data, crc);
module crc_serial_long_division(clk, reset, data, crc);
//=============================================================
//=============================================================
// Verilog function that implements serial USB CRC5
// Verilog function that implements serial USB CRC5
//=============================================================
//=============================================================
input clk, reset;
input clk, reset;
input data;
input data;
output reg [4:0] crc;
output reg [4:0] crc;
always @(posedge clk)
always @(posedge clk)
begin
begin
if(reset) crc <= 0;
if(reset) crc <= 0;
else begin
else begin
crc[0] <= crc[4] ^ data;
crc[0] <= crc[4] ^ data;
crc[1] <= crc[0];
crc[1] <= crc[0];
crc[2] <= crc[1] ^ crc[4] ^ data;
crc[2] <= crc[1] ^ crc[4];
crc[3] <= crc[2];
crc[3] <= crc[2];
crc[4] <= crc[3];
crc[4] <= crc[3];
end
end
end
end
//============================================================
//============================================================
endmodule
endmodule