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Untitled Diff
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3 years ago
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10 removals
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29 lines
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10 additions
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28 lines
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Iterations: 100
Iterations: 100
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Instructions:
9
00
Instructions:
8
00
Total Cycles: 26
1
Total Cycles: 26
4
Total uOps:
1000
Total uOps:
900
Dispatch Width: 6
Dispatch Width: 6
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uOps Per Cycle: 3.
83
uOps Per Cycle: 3.
41
IPC: 3.
45
IPC: 3.
03
Block RThroughput: 2.5
Block RThroughput: 2.5
Instruction Info:
Instruction Info:
[1]: #uOps
[1]: #uOps
[2]: Latency
[2]: Latency
[3]: RThroughput
[3]: RThroughput
[4]: MayLoad
[4]: MayLoad
[5]: MayStore
[5]: MayStore
[6]: HasSideEffects (U)
[6]: HasSideEffects (U)
[1] [2] [3] [4] [5] [6] Instructions:
[1] [2] [3] [4] [5] [6] Instructions:
1 8 0.50 * vmovdqu ymm0, ymmword ptr [rdi]
1 8 0.50 * vmovdqu ymm0, ymmword ptr [rdi]
1 8 0.50 * vmovdqu ymm1, ymmword ptr [rdi + 18]
1 8 0.50 * vmovdqu ymm1, ymmword ptr [rdi + 18]
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1 8 0.50 * vpxor ymm1, ymm1, ymmword ptr [rsi + 18]
1 8 0.50 * vpxor ymm0, ymm0, ymmword ptr [rsi]
1 8 0.50 * vpxor ymm0, ymm0, ymmword ptr [rsi]
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1
1
0.
25
vpor
ymm0, ymm
0, ymm1
1
8
0.
50
*
vpternlogq
ymm0, ymm
1, ymmword ptr [rsi + 18], 246
2 1 1.00 vptest ymm0, ymm0
2 1 1.00 vptest ymm0, ymm0
1 1 1.00 sete al
1 1 1.00 sete al
1 0 0.25 U vzeroupper
1 0 0.25 U vzeroupper
1 5 0.50 U ret
1 5 0.50 U ret
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Original text
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Iterations: 100 Instructions: 900 Total Cycles: 261 Total uOps: 1000 Dispatch Width: 6 uOps Per Cycle: 3.83 IPC: 3.45 Block RThroughput: 2.5 Instruction Info: [1]: #uOps [2]: Latency [3]: RThroughput [4]: MayLoad [5]: MayStore [6]: HasSideEffects (U) [1] [2] [3] [4] [5] [6] Instructions: 1 8 0.50 * vmovdqu ymm0, ymmword ptr [rdi] 1 8 0.50 * vmovdqu ymm1, ymmword ptr [rdi + 18] 1 8 0.50 * vpxor ymm1, ymm1, ymmword ptr [rsi + 18] 1 8 0.50 * vpxor ymm0, ymm0, ymmword ptr [rsi] 1 1 0.25 vpor ymm0, ymm0, ymm1 2 1 1.00 vptest ymm0, ymm0 1 1 1.00 sete al 1 0 0.25 U vzeroupper 1 5 0.50 U ret
Changed text
Open file
Iterations: 100 Instructions: 800 Total Cycles: 264 Total uOps: 900 Dispatch Width: 6 uOps Per Cycle: 3.41 IPC: 3.03 Block RThroughput: 2.5 Instruction Info: [1]: #uOps [2]: Latency [3]: RThroughput [4]: MayLoad [5]: MayStore [6]: HasSideEffects (U) [1] [2] [3] [4] [5] [6] Instructions: 1 8 0.50 * vmovdqu ymm0, ymmword ptr [rdi] 1 8 0.50 * vmovdqu ymm1, ymmword ptr [rdi + 18] 1 8 0.50 * vpxor ymm0, ymm0, ymmword ptr [rsi] 1 8 0.50 * vpternlogq ymm0, ymm1, ymmword ptr [rsi + 18], 246 2 1 1.00 vptest ymm0, ymm0 1 1 1.00 sete al 1 0 0.25 U vzeroupper 1 5 0.50 U ret
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